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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_int.v] - Blame information for rev 21

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE AC 97 Controller                                  ////
////  Interrupt Logic                                            ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ac97_int.v,v 1.3 2002-09-19 06:30:56 rudi Exp $
//
//  $Date: 2002-09-19 06:30:56 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2002/03/05 04:44:05  rudi
//
//               - Fixed the order of the thrash hold bits to match the spec.
//               - Many minor synthesis cleanup items ...
//
//               Revision 1.1  2001/08/03 06:54:50  rudi
//
//
//               - Changed to new directory structure
//
//               Revision 1.1.1.1  2001/05/19 02:29:18  rudi
//               Initial Checkin
//
//
//
//
 
`include "ac97_defines.v"
 
module ac97_int(clk, rst,
 
                // Register File Interface
                int_set,
 
                // FIFO Interface
                cfg, status, full_empty, full, empty, re, we
                );
 
input           clk, rst;
output  [2:0]    int_set;
 
input   [7:0]    cfg;
input   [1:0]    status;
input           full_empty, full, empty, re, we;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [2:0]    int_set;
 
////////////////////////////////////////////////////////////////////
//
// Interrupt Logic
//
 
always @(posedge clk or negedge rst)
        if(!rst)        int_set[0] <= #1 1'b0;
        else
        case(cfg[5:4])  // synopsys parallel_case full_case
                        // 1/4 full/empty
           2'h2: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'h0));
                        // 1/2 full/empty
           2'h1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'h0));
                        // 3/4 full/empty
           2'h0: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'h3));
           2'h3: int_set[0] <= #1 cfg[0] & full_empty;
        endcase
 
always @(posedge clk or negedge rst)
        if(!rst)        int_set[1] <= #1 1'b0;
        else
        if(empty & re)  int_set[1] <= #1 1'b1;
        else int_set[1] <= #1 1'b0;
 
always @(posedge clk or negedge rst)
        if(!rst)        int_set[2] <= #1 1'b0;
        else
        if(full & we)   int_set[2] <= #1 1'b1;
        else int_set[2] <= #1 1'b0;
 
endmodule

Line No.	Rev	Author	Line
1	4	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE AC 97 Controller ////`
4			`//// Interrupt Logic ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	14	rudi	`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
16			`//// www.asics.ws ////`
17			`//// rudi@asics.ws ////`
18	4	rudi	`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer.////`
23			`//// ////`
24			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
25			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
26			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
27			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
28			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
29			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
30			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
31			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
32			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
33			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
34			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
35			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
36			`//// POSSIBILITY OF SUCH DAMAGE. ////`
37			`//// ////`
38			`/////////////////////////////////////////////////////////////////////`
39
40			`// CVS Log`
41			`//`
42	14	rudi	`// $Id: ac97_int.v,v 1.3 2002-09-19 06:30:56 rudi Exp $`
43	4	rudi	`//`
44	14	rudi	`// $Date: 2002-09-19 06:30:56 $`
45			`// $Revision: 1.3 $`
46	4	rudi	`// $Author: rudi $`
47			`// $Locker: $`
48			`// $State: Exp $`
49			`//`
50			`// Change History:`
51			`// $Log: not supported by cvs2svn $`
52	14	rudi	`// Revision 1.2 2002/03/05 04:44:05 rudi`
53			`//`
54			`// - Fixed the order of the thrash hold bits to match the spec.`
55			`// - Many minor synthesis cleanup items ...`
56			`//`
57	10	rudi	`// Revision 1.1 2001/08/03 06:54:50 rudi`
58			`//`
59			`//`
60			`// - Changed to new directory structure`
61			`//`
62	4	rudi	`// Revision 1.1.1.1 2001/05/19 02:29:18 rudi`
63			`// Initial Checkin`
64			`//`
65			`//`
66			`//`
67			`//`
68
69			`include "ac97_defines.v"
70
71			`module ac97_int(clk, rst,`
72
73			`// Register File Interface`
74			`int_set,`
75
76			`// FIFO Interface`
77			`cfg, status, full_empty, full, empty, re, we`
78			`);`
79
80			`input clk, rst;`
81			`output [2:0] int_set;`
82
83			`input [7:0] cfg;`
84			`input [1:0] status;`
85			`input full_empty, full, empty, re, we;`
86
87			`////////////////////////////////////////////////////////////////////`
88			`//`
89			`// Local Wires`
90			`//`
91
92			`reg [2:0] int_set;`
93
94			`////////////////////////////////////////////////////////////////////`
95			`//`
96			`// Interrupt Logic`
97			`//`
98
99			`always @(posedge clk or negedge rst)`
100	10	rudi	`if(!rst) int_set[0] <= #1 1'b0;`
101	4	rudi	`else`
102			`case(cfg[5:4]) // synopsys parallel_case full_case`
103			`// 1/4 full/empty`
104	10	rudi	`2'h2: int_set[0] <= #1 cfg[0] & (full_empty \| (status == 2'h0));`
105	4	rudi	`// 1/2 full/empty`
106	10	rudi	`2'h1: int_set[0] <= #1 cfg[0] & (full_empty \| (status[1] == 1'h0));`
107	4	rudi	`// 3/4 full/empty`
108	10	rudi	`2'h0: int_set[0] <= #1 cfg[0] & (full_empty \| (status < 2'h3));`
109			`2'h3: int_set[0] <= #1 cfg[0] & full_empty;`
110	4	rudi	`endcase`
111
112			`always @(posedge clk or negedge rst)`
113	10	rudi	`if(!rst) int_set[1] <= #1 1'b0;`
114	4	rudi	`else`
115	10	rudi	`if(empty & re) int_set[1] <= #1 1'b1;`
116	21	stekern	`else int_set[1] <= #1 1'b0;`
117	4	rudi
118			`always @(posedge clk or negedge rst)`
119	10	rudi	`if(!rst) int_set[2] <= #1 1'b0;`
120	4	rudi	`else`
121	10	rudi	`if(full & we) int_set[2] <= #1 1'b1;`
122	21	stekern	`else int_set[2] <= #1 1'b0;`
123	4	rudi
124			`endmodule`

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[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_int.v] - Blame information for rev 21