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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_or1k_status_reg.v] - Blame information for rev 69

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  adbg_or1k_status_reg.v                                      ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////       Nathan Yawn (nyawn@opencores.org)                      ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2011 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_or1k_status_reg.v,v $
// Revision 1.3  2011-10-24 02:25:11  natey
// Removed extraneous '#1' delays, which were a holdover from the original
// versions in the previous dbg_if core.
//
// Revision 1.2  2010-01-10 22:54:10  Nathan
// Update copyright dates
//
// Revision 1.1  2008/07/22 20:28:31  Nathan
// Changed names of all files and modules (prefixed an a, for advanced).  Cleanup, indenting.  No functional changes.
//
// Revision 1.3  2008/07/06 20:02:54  Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with 
// Quartus II 7.0).  Ran through dos2unix.
//
// Revision 1.2  2008/06/26 20:52:32  Nathan
// OR1K module tested and working.  Added copyright / license info 
// to _define files.  Other cleanup.
//
//
//
//
 
`include "adbg_or1k_defines.v"
 
module adbg_or1k_status_reg  (
                              data_i,
                              we_i,
                              tck_i,
                              bp_i,
                              rst_i,
                              cpu_clk_i,
                              ctrl_reg_o,
                              cpu_stall_o,
                              cpu_rst_o
                              );
 
 
   input  [`DBG_OR1K_STATUS_LEN - 1:0] data_i;
   input                               we_i;
   input                               tck_i;
   input                               bp_i;
   input                               rst_i;
   input                               cpu_clk_i;
 
   output [`DBG_OR1K_STATUS_LEN - 1:0] ctrl_reg_o;
   output                              cpu_stall_o;
   output                              cpu_rst_o;
 
   reg                                 cpu_reset;
   wire [2:1]                          cpu_op_out;
 
   reg                                 stall_bp, stall_bp_csff, stall_bp_tck;
   reg                                 stall_reg, stall_reg_csff, stall_reg_cpu;
   reg                                 cpu_reset_csff;
   reg                                 cpu_rst_o;
 
 
 
   // Breakpoint is latched and synchronized. Stall is set and latched.
   // This is done in the CPU clock domain, because the JTAG clock (TCK) is
   // irregular.  By only allowing bp_i to set (but not reset) the stall_bp
   // signal, we insure that the CPU will remain in the stalled state until
   // the debug host can read the state.
   always @ (posedge cpu_clk_i or posedge rst_i)
     begin
        if(rst_i)
          stall_bp <= 1'b0;
        else if(bp_i)
          stall_bp <= 1'b1;
        else if(stall_reg_cpu)
          stall_bp <= 1'b0;
     end
 
 
   // Synchronizing
   always @ (posedge tck_i or posedge rst_i)
     begin
        if (rst_i)
          begin
             stall_bp_csff <= 1'b0;
             stall_bp_tck  <= 1'b0;
          end
        else
          begin
             stall_bp_csff <= stall_bp;
             stall_bp_tck  <= stall_bp_csff;
          end
     end
 
 
   always @ (posedge cpu_clk_i or posedge rst_i)
     begin
        if (rst_i)
          begin
             stall_reg_csff <= 1'b0;
             stall_reg_cpu  <= 1'b0;
          end
        else
          begin
             stall_reg_csff <= stall_reg;
             stall_reg_cpu  <= stall_reg_csff;
          end
     end
 
   // bp_i forces a stall immediately on a breakpoint
   // stall_bp holds the stall until the debug host acts
   // stall_reg_cpu allows the debug host to control a stall.
   assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
 
 
   // Writing data to the control registers (stall)
   // This can be set either by the debug host, or by
   // a CPU breakpoint.  It can only be cleared by the host.
   always @ (posedge tck_i or posedge rst_i)
     begin
        if (rst_i)
          stall_reg <= 1'b0;
        else if (stall_bp_tck)
          stall_reg <= 1'b1;
        else if (we_i)
          stall_reg <= data_i[0];
     end
 
 
   // Writing data to the control registers (reset)
   always @ (posedge tck_i or posedge rst_i)
     begin
        if (rst_i)
          cpu_reset  <= 1'b0;
        else if(we_i)
          cpu_reset  <= data_i[1];
     end
 
 
   // Synchronizing signals from registers
   always @ (posedge cpu_clk_i or posedge rst_i)
     begin
        if (rst_i)
          begin
             cpu_reset_csff      <= 1'b0;
             cpu_rst_o           <= 1'b0;
          end
        else
          begin
             cpu_reset_csff      <= cpu_reset;
             cpu_rst_o           <= cpu_reset_csff;
          end
     end
 
 
 
   // Value for read back
   assign ctrl_reg_o = {cpu_reset, stall_reg};
 
 
endmodule
 

Line No.	Rev	Author	Line
1	3	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// adbg_or1k_status_reg.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Igor Mohor (igorm@opencores.org) ////`
10	69	nyawn	`//// Nathan Yawn (nyawn@opencores.org) ////`
11	3	nyawn	`//// ////`
12			`//// ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16	69	nyawn	`//// Copyright (C) 2000 - 2011 Authors ////`
17	3	nyawn	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: adbg_or1k_status_reg.v,v $`
44	69	nyawn	`// Revision 1.3 2011-10-24 02:25:11 natey`
45			`// Removed extraneous '#1' delays, which were a holdover from the original`
46			`// versions in the previous dbg_if core.`
47			`//`
48	32	nyawn	`// Revision 1.2 2010-01-10 22:54:10 Nathan`
49			`// Update copyright dates`
50			`//`
51	3	nyawn	`// Revision 1.1 2008/07/22 20:28:31 Nathan`
52			`// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.`
53			`//`
54			`// Revision 1.3 2008/07/06 20:02:54 Nathan`
55			`// Fixes for synthesis with Xilinx ISE (also synthesizable with`
56			`// Quartus II 7.0). Ran through dos2unix.`
57			`//`
58			`// Revision 1.2 2008/06/26 20:52:32 Nathan`
59			`// OR1K module tested and working. Added copyright / license info`
60			`// to _define files. Other cleanup.`
61			`//`
62			`//`
63			`//`
64			`//`
65
66			`include "adbg_or1k_defines.v"
67
68			`module adbg_or1k_status_reg (`
69			`data_i,`
70			`we_i,`
71			`tck_i,`
72			`bp_i,`
73			`rst_i,`
74			`cpu_clk_i,`
75			`ctrl_reg_o,`
76			`cpu_stall_o,`
77			`cpu_rst_o`
78			`);`
79
80
81			input [`DBG_OR1K_STATUS_LEN - 1:0] data_i;
82			`input we_i;`
83			`input tck_i;`
84			`input bp_i;`
85			`input rst_i;`
86			`input cpu_clk_i;`
87
88			output [`DBG_OR1K_STATUS_LEN - 1:0] ctrl_reg_o;
89			`output cpu_stall_o;`
90			`output cpu_rst_o;`
91
92			`reg cpu_reset;`
93			`wire [2:1] cpu_op_out;`
94
95			`reg stall_bp, stall_bp_csff, stall_bp_tck;`
96			`reg stall_reg, stall_reg_csff, stall_reg_cpu;`
97			`reg cpu_reset_csff;`
98			`reg cpu_rst_o;`
99
100
101
102			`// Breakpoint is latched and synchronized. Stall is set and latched.`
103			`// This is done in the CPU clock domain, because the JTAG clock (TCK) is`
104			`// irregular. By only allowing bp_i to set (but not reset) the stall_bp`
105			`// signal, we insure that the CPU will remain in the stalled state until`
106			`// the debug host can read the state.`
107			`always @ (posedge cpu_clk_i or posedge rst_i)`
108			`begin`
109			`if(rst_i)`
110	69	nyawn	`stall_bp <= 1'b0;`
111	3	nyawn	`else if(bp_i)`
112	69	nyawn	`stall_bp <= 1'b1;`
113	3	nyawn	`else if(stall_reg_cpu)`
114	69	nyawn	`stall_bp <= 1'b0;`
115	3	nyawn	`end`
116
117
118			`// Synchronizing`
119			`always @ (posedge tck_i or posedge rst_i)`
120			`begin`
121			`if (rst_i)`
122			`begin`
123	69	nyawn	`stall_bp_csff <= 1'b0;`
124			`stall_bp_tck <= 1'b0;`
125	3	nyawn	`end`
126			`else`
127			`begin`
128	69	nyawn	`stall_bp_csff <= stall_bp;`
129			`stall_bp_tck <= stall_bp_csff;`
130	3	nyawn	`end`
131			`end`
132
133
134			`always @ (posedge cpu_clk_i or posedge rst_i)`
135			`begin`
136			`if (rst_i)`
137			`begin`
138	69	nyawn	`stall_reg_csff <= 1'b0;`
139			`stall_reg_cpu <= 1'b0;`
140	3	nyawn	`end`
141			`else`
142			`begin`
143	69	nyawn	`stall_reg_csff <= stall_reg;`
144			`stall_reg_cpu <= stall_reg_csff;`
145	3	nyawn	`end`
146			`end`
147
148			`// bp_i forces a stall immediately on a breakpoint`
149			`// stall_bp holds the stall until the debug host acts`
150			`// stall_reg_cpu allows the debug host to control a stall.`
151			`assign cpu_stall_o = bp_i \| stall_bp \| stall_reg_cpu;`
152
153
154			`// Writing data to the control registers (stall)`
155			`// This can be set either by the debug host, or by`
156			`// a CPU breakpoint. It can only be cleared by the host.`
157			`always @ (posedge tck_i or posedge rst_i)`
158			`begin`
159			`if (rst_i)`
160	69	nyawn	`stall_reg <= 1'b0;`
161	3	nyawn	`else if (stall_bp_tck)`
162	69	nyawn	`stall_reg <= 1'b1;`
163	3	nyawn	`else if (we_i)`
164	69	nyawn	`stall_reg <= data_i[0];`
165	3	nyawn	`end`
166
167
168			`// Writing data to the control registers (reset)`
169			`always @ (posedge tck_i or posedge rst_i)`
170			`begin`
171			`if (rst_i)`
172	69	nyawn	`cpu_reset <= 1'b0;`
173	3	nyawn	`else if(we_i)`
174	69	nyawn	`cpu_reset <= data_i[1];`
175	3	nyawn	`end`
176
177
178			`// Synchronizing signals from registers`
179			`always @ (posedge cpu_clk_i or posedge rst_i)`
180			`begin`
181			`if (rst_i)`
182			`begin`
183	69	nyawn	`cpu_reset_csff <= 1'b0;`
184			`cpu_rst_o <= 1'b0;`
185	3	nyawn	`end`
186			`else`
187			`begin`
188	69	nyawn	`cpu_reset_csff <= cpu_reset;`
189			`cpu_rst_o <= cpu_reset_csff;`
190	3	nyawn	`end`
191			`end`
192
193
194
195			`// Value for read back`
196			`assign ctrl_reg_o = {cpu_reset, stall_reg};`
197
198
199			`endmodule`
200

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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_or1k_status_reg.v] - Blame information for rev 69