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[/] [adv_debug_sys/] [trunk/] [Hardware/] [jtag/] [tap/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 69

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the JTAG Test Access Port (TAP)        ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the jtag.pdf     ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2008 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: tap_top.v,v $
// Revision 1.6  2011-10-24 02:18:58  natey
// Removed '#1' delays, which were a holdover from the original version. Ran
// through dos2unix.
//
// Revision 1.5  2009-06-16 02:53:58  Nathan
// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.
//
// Revision 1.4  2009/05/17 20:54:38  Nathan
// Changed email address to opencores.org
//
// Revision 1.3  2008/06/18 18:45:07  Nathan
// Improved reset slightly.  Cleanup.
//
//
// Revision 1.2 2008/05/14 13:13:24 Nathan
// Rewrote TAP FSM in canonical form, for readability.  Switched
// from one-hot to binary encoding.  Made reset signal active-
// low, per JTAG spec.  Removed FF chain for 5 TMS reset - reset
// done in Test Logic Reset mode.  Added test_logic_reset_o and
// run_test_idle_o signals.  Removed double registers from IR data
// path.  Unified the registers at the output of each data register
// to a single shared FF.
//
 
`include "tap_defines.v"
 
// Top module
module tap_top(
                // JTAG pads
                tms_pad_i,
                tck_pad_i,
                trstn_pad_i,
                tdi_pad_i,
                tdo_pad_o,
                tdo_padoe_o,
 
                // TAP states
                                test_logic_reset_o,
                                run_test_idle_o,
                shift_dr_o,
                pause_dr_o,
                update_dr_o,
                capture_dr_o,
 
                // Select signals for boundary scan or mbist
                extest_select_o,
                sample_preload_select_o,
                mbist_select_o,
                debug_select_o,
 
                // TDO signal that is connected to TDI of sub-modules.
                tdi_o,
 
                // TDI signals from sub-modules
                debug_tdo_i,    // from debug module
                bs_chain_tdo_i, // from Boundary Scan Chain
                mbist_tdo_i     // from Mbist Chain
              );
 
 
// JTAG pins
input   tms_pad_i;      // JTAG test mode select pad
input   tck_pad_i;      // JTAG test clock pad
input   trstn_pad_i;     // JTAG test reset pad
input   tdi_pad_i;      // JTAG test data input pad
output  tdo_pad_o;      // JTAG test data output pad
output  tdo_padoe_o;    // Output enable for JTAG test data output pad 
 
// TAP states
output  test_logic_reset_o;
output  run_test_idle_o;
output  shift_dr_o;
output  pause_dr_o;
output  update_dr_o;
output  capture_dr_o;
 
// Select signals for boundary scan or mbist
output  extest_select_o;
output  sample_preload_select_o;
output  mbist_select_o;
output  debug_select_o;
 
// TDO signal that is connected to TDI of sub-modules.
output  tdi_o;
 
// TDI signals from sub-modules
input   debug_tdo_i;    // from debug module
input   bs_chain_tdo_i; // from Boundary Scan Chain
input   mbist_tdo_i;    // from Mbist Chain
 
// Wires which depend on the state of the TAP FSM
reg     test_logic_reset;
reg     run_test_idle;
reg     select_dr_scan;
reg     capture_dr;
reg     shift_dr;
reg     exit1_dr;
reg     pause_dr;
reg     exit2_dr;
reg     update_dr;
reg     select_ir_scan;
reg     capture_ir;
reg     shift_ir;
reg     exit1_ir;
reg     pause_ir;
reg     exit2_ir;
reg     update_ir;
 
// Wires which depend on the current value in the IR
reg     extest_select;
reg     sample_preload_select;
reg     idcode_select;
reg     mbist_select;
reg     debug_select;
reg     bypass_select;
 
// TDO and enable
reg     tdo_pad_o;
reg     tdo_padoe_o;
 
assign tdi_o = tdi_pad_i;
 
assign test_logic_reset_o = test_logic_reset;
assign run_test_idle_o = run_test_idle;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
 
assign extest_select_o = extest_select;
assign sample_preload_select_o = sample_preload_select;
assign mbist_select_o = mbist_select;
assign debug_select_o = debug_select;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
// Definition of machine state values.  We could one-hot encode this, and use 16
// registers, but this uses binary encoding for the minimum of 4 DFF's instead.
`define STATE_test_logic_reset 4'hF
`define STATE_run_test_idle    4'hC
`define STATE_select_dr_scan   4'h7
`define STATE_capture_dr       4'h6
`define STATE_shift_dr         4'h2
`define STATE_exit1_dr         4'h1
`define STATE_pause_dr         4'h3
`define STATE_exit2_dr         4'h0
`define STATE_update_dr        4'h5
`define STATE_select_ir_scan   4'h4
`define STATE_capture_ir       4'hE
`define STATE_shift_ir         4'hA
`define STATE_exit1_ir         4'h9
`define STATE_pause_ir         4'hB
`define STATE_exit2_ir         4'h8
`define STATE_update_ir        4'hD
 
reg [3:0] TAP_state = `STATE_test_logic_reset;  // current state of the TAP controller
reg [3:0] next_TAP_state;  // state TAP will take at next rising TCK, combinational signal
 
// sequential part of the FSM
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
        if(trstn_pad_i == 0)
                TAP_state = `STATE_test_logic_reset;
        else
                TAP_state = next_TAP_state;
end
 
 
// Determination of next state; purely combinatorial
always @ (TAP_state or tms_pad_i)
begin
        case(TAP_state)
                `STATE_test_logic_reset:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_run_test_idle:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_select_dr_scan:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
                        else next_TAP_state = `STATE_capture_dr;
                        end
                `STATE_capture_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_shift_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_exit1_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_dr;
                        else next_TAP_state = `STATE_pause_dr;
                        end
                `STATE_pause_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
                        else next_TAP_state = `STATE_pause_dr;
                        end
                `STATE_exit2_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_dr;
                        else next_TAP_state = `STATE_shift_dr;
                        end
                `STATE_update_dr:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                `STATE_select_ir_scan:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
                        else next_TAP_state = `STATE_capture_ir;
                        end
                `STATE_capture_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_shift_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_exit1_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_ir;
                        else next_TAP_state = `STATE_pause_ir;
                        end
                `STATE_pause_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
                        else next_TAP_state = `STATE_pause_ir;
                        end
                `STATE_exit2_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_update_ir;
                        else next_TAP_state = `STATE_shift_ir;
                        end
                `STATE_update_ir:
                        begin
                        if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
                        else next_TAP_state = `STATE_run_test_idle;
                        end
                default: next_TAP_state = `STATE_test_logic_reset;  // can't actually happen
        endcase
end
 
 
// Outputs of state machine, pure combinatorial
always @ (TAP_state)
begin
        // Default everything to 0, keeps the case statement simple
        test_logic_reset = 1'b0;
        run_test_idle = 1'b0;
        select_dr_scan = 1'b0;
        capture_dr = 1'b0;
        shift_dr = 1'b0;
        exit1_dr = 1'b0;
        pause_dr = 1'b0;
        exit2_dr = 1'b0;
        update_dr = 1'b0;
        select_ir_scan = 1'b0;
        capture_ir = 1'b0;
        shift_ir = 1'b0;
        exit1_ir = 1'b0;
        pause_ir = 1'b0;
        exit2_ir = 1'b0;
        update_ir = 1'b0;
 
        case(TAP_state)
                `STATE_test_logic_reset: test_logic_reset = 1'b1;
                `STATE_run_test_idle:    run_test_idle = 1'b1;
                `STATE_select_dr_scan:   select_dr_scan = 1'b1;
                `STATE_capture_dr:       capture_dr = 1'b1;
                `STATE_shift_dr:         shift_dr = 1'b1;
                `STATE_exit1_dr:         exit1_dr = 1'b1;
                `STATE_pause_dr:         pause_dr = 1'b1;
                `STATE_exit2_dr:         exit2_dr = 1'b1;
                `STATE_update_dr:        update_dr = 1'b1;
                `STATE_select_ir_scan:   select_ir_scan = 1'b1;
                `STATE_capture_ir:       capture_ir = 1'b1;
                `STATE_shift_ir:         shift_ir = 1'b1;
                `STATE_exit1_ir:         exit1_ir = 1'b1;
                `STATE_pause_ir:         pause_ir = 1'b1;
                `STATE_exit2_ir:         exit2_ir = 1'b1;
                `STATE_update_ir:        update_ir = 1'b1;
                default: ;
        endcase
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   jtag_ir:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
reg [`IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [`IR_LENGTH-1:0]  latched_jtag_ir; //, latched_jtag_ir_neg;
wire                  instruction_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
  else if (test_logic_reset == 1)
        jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
  else if(capture_ir)
    jtag_ir <= 4'b0101;          // This value is fixed for easier fault detection
  else if(shift_ir)
    jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
 
assign instruction_tdo = jtag_ir[0];  // This is latched on a negative TCK edge after the output MUX
 
// Updating jtag_ir (Instruction Register)
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
always @ (negedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    latched_jtag_ir <= `IDCODE;   // IDCODE selected after reset
  else if (test_logic_reset)
    latched_jtag_ir <= `IDCODE;   // IDCODE selected after reset
  else if(update_ir)
    latched_jtag_ir <= jtag_ir;
end
 
/**********************************************************************************
*                                                                                 *
*   End: jtag_ir                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   idcode logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg [31:0] idcode_reg;
wire        idcode_tdo;
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if(trstn_pad_i == 0)
    idcode_reg <= `IDCODE_VALUE;   // IDCODE selected after reset
  else if (test_logic_reset)
    idcode_reg <= `IDCODE_VALUE;   // IDCODE selected after reset
  else if(idcode_select & capture_dr)
    idcode_reg <=  `IDCODE_VALUE;
  else if(idcode_select & shift_dr)
    idcode_reg <=  {tdi_pad_i, idcode_reg[31:1]};
 
end
 
assign idcode_tdo = idcode_reg[0];   // This is latched on a negative TCK edge after the output MUX
 
/**********************************************************************************
*                                                                                 *
*   End: idcode logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
wire  bypassed_tdo;
reg   bypass_reg;  // This is a 1-bit register
 
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
  if (trstn_pad_i == 0)
     bypass_reg <=  1'b0;
  else if (test_logic_reset == 1)
     bypass_reg <=  1'b0;
  else if (bypass_select & capture_dr)
    bypass_reg<= 1'b0;
  else if(bypass_select & shift_dr)
    bypass_reg<= tdi_pad_i;
end
 
assign bypassed_tdo = bypass_reg;   // This is latched on a negative TCK edge after the output MUX
 
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   Selecting active data register                                                *
*                                                                                 *
**********************************************************************************/
always @ (latched_jtag_ir)
begin
  extest_select           = 1'b0;
  sample_preload_select   = 1'b0;
  idcode_select           = 1'b0;
  mbist_select            = 1'b0;
  debug_select            = 1'b0;
  bypass_select           = 1'b0;
 
  case(latched_jtag_ir)    /* synthesis parallel_case */
    `EXTEST:            extest_select           = 1'b1;    // External test
    `SAMPLE_PRELOAD:    sample_preload_select   = 1'b1;    // Sample preload
    `IDCODE:            idcode_select           = 1'b1;    // ID Code
    `MBIST:             mbist_select            = 1'b1;    // Mbist test
    `DEBUG:             debug_select            = 1'b1;    // Debug
    `BYPASS:            bypass_select           = 1'b1;    // BYPASS
    default:            bypass_select           = 1'b1;    // BYPASS
  endcase
end
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
reg tdo_mux_out;  // really just a wire
 
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
          debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or
                        bs_chain_tdo_i)
begin
  if(shift_ir)
    tdo_mux_out = instruction_tdo;
  else
    begin
      case(latched_jtag_ir)    // synthesis parallel_case
        `IDCODE:            tdo_mux_out = idcode_tdo;       // Reading ID code
        `DEBUG:             tdo_mux_out = debug_tdo_i;      // Debug
        `SAMPLE_PRELOAD:    tdo_mux_out = bs_chain_tdo_i;   // Sampling/Preloading
        `EXTEST:            tdo_mux_out = bs_chain_tdo_i;   // External test
        `MBIST:             tdo_mux_out = mbist_tdo_i;      // Mbist test
        default:            tdo_mux_out = bypassed_tdo;     // BYPASS instruction
      endcase
    end
end
 
 
// TDO changes state at negative edge of TCK
always @ (negedge tck_pad_i)
begin
        tdo_pad_o = tdo_mux_out;
end
 
 
// Tristate control for tdo_pad_o pin
always @ (posedge tck_pad_i)
begin
  tdo_padoe_o <= shift_ir | shift_dr;
end
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
endmodule

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Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [jtag/] [tap/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 69

Line No.	Rev	Author	Line
1	69	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the JTAG Test Access Port (TAP) ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Igor Mohor (igorm@opencores.org) ////`
10			`//// Nathan Yawn (nathan.yawn@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the jtag.pdf ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2008 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45	3	nyawn	`// $Log: tap_top.v,v $`
46	69	nyawn	`// Revision 1.6 2011-10-24 02:18:58 natey`
47			`// Removed '#1' delays, which were a holdover from the original version. Ran`
48			`// through dos2unix.`
49			`//`
50	32	nyawn	`// Revision 1.5 2009-06-16 02:53:58 Nathan`
51	14	nyawn	`// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.`
52	69	nyawn	`//`
53			`// Revision 1.4 2009/05/17 20:54:38 Nathan`
54			`// Changed email address to opencores.org`
55			`//`
56			`// Revision 1.3 2008/06/18 18:45:07 Nathan`
57			`// Improved reset slightly. Cleanup.`
58			`//`
59			`//`
60			`// Revision 1.2 2008/05/14 13:13:24 Nathan`
61			`// Rewrote TAP FSM in canonical form, for readability. Switched`
62			`// from one-hot to binary encoding. Made reset signal active-`
63			`// low, per JTAG spec. Removed FF chain for 5 TMS reset - reset`
64			`// done in Test Logic Reset mode. Added test_logic_reset_o and`
65			`// run_test_idle_o signals. Removed double registers from IR data`
66			`// path. Unified the registers at the output of each data register`
67			`// to a single shared FF.`
68			`//`
69
70			`include "tap_defines.v"
71
72			`// Top module`
73			`module tap_top(`
74			`// JTAG pads`
75			`tms_pad_i,`
76			`tck_pad_i,`
77			`trstn_pad_i,`
78			`tdi_pad_i,`
79			`tdo_pad_o,`
80			`tdo_padoe_o,`
81
82			`// TAP states`
83			`test_logic_reset_o,`
84			`run_test_idle_o,`
85			`shift_dr_o,`
86			`pause_dr_o,`
87			`update_dr_o,`
88			`capture_dr_o,`
89
90			`// Select signals for boundary scan or mbist`
91			`extest_select_o,`
92			`sample_preload_select_o,`
93			`mbist_select_o,`
94			`debug_select_o,`
95
96			`// TDO signal that is connected to TDI of sub-modules.`
97			`tdi_o,`
98
99			`// TDI signals from sub-modules`
100			`debug_tdo_i, // from debug module`
101			`bs_chain_tdo_i, // from Boundary Scan Chain`
102			`mbist_tdo_i // from Mbist Chain`
103			`);`
104
105
106			`// JTAG pins`
107			`input tms_pad_i; // JTAG test mode select pad`
108			`input tck_pad_i; // JTAG test clock pad`
109			`input trstn_pad_i; // JTAG test reset pad`
110			`input tdi_pad_i; // JTAG test data input pad`
111			`output tdo_pad_o; // JTAG test data output pad`
112			`output tdo_padoe_o; // Output enable for JTAG test data output pad`
113
114			`// TAP states`
115			`output test_logic_reset_o;`
116			`output run_test_idle_o;`
117			`output shift_dr_o;`
118			`output pause_dr_o;`
119			`output update_dr_o;`
120			`output capture_dr_o;`
121
122			`// Select signals for boundary scan or mbist`
123			`output extest_select_o;`
124			`output sample_preload_select_o;`
125			`output mbist_select_o;`
126			`output debug_select_o;`
127
128			`// TDO signal that is connected to TDI of sub-modules.`
129			`output tdi_o;`
130
131			`// TDI signals from sub-modules`
132			`input debug_tdo_i; // from debug module`
133			`input bs_chain_tdo_i; // from Boundary Scan Chain`
134			`input mbist_tdo_i; // from Mbist Chain`
135
136			`// Wires which depend on the state of the TAP FSM`
137			`reg test_logic_reset;`
138			`reg run_test_idle;`
139			`reg select_dr_scan;`
140			`reg capture_dr;`
141			`reg shift_dr;`
142			`reg exit1_dr;`
143			`reg pause_dr;`
144			`reg exit2_dr;`
145			`reg update_dr;`
146			`reg select_ir_scan;`
147			`reg capture_ir;`
148			`reg shift_ir;`
149			`reg exit1_ir;`
150			`reg pause_ir;`
151			`reg exit2_ir;`
152			`reg update_ir;`
153
154			`// Wires which depend on the current value in the IR`
155			`reg extest_select;`
156			`reg sample_preload_select;`
157			`reg idcode_select;`
158			`reg mbist_select;`
159			`reg debug_select;`
160			`reg bypass_select;`
161
162			`// TDO and enable`
163			`reg tdo_pad_o;`
164			`reg tdo_padoe_o;`
165
166			`assign tdi_o = tdi_pad_i;`
167
168			`assign test_logic_reset_o = test_logic_reset;`
169			`assign run_test_idle_o = run_test_idle;`
170			`assign shift_dr_o = shift_dr;`
171			`assign pause_dr_o = pause_dr;`
172			`assign update_dr_o = update_dr;`
173			`assign capture_dr_o = capture_dr;`
174
175			`assign extest_select_o = extest_select;`
176			`assign sample_preload_select_o = sample_preload_select;`
177			`assign mbist_select_o = mbist_select;`
178			`assign debug_select_o = debug_select;`
179
180
181			`/**********************************************************************************`
182			`* *`
183			`* TAP State Machine: Fully JTAG compliant *`
184			`* *`
185			`**********************************************************************************/`
186			`// Definition of machine state values. We could one-hot encode this, and use 16`
187			`// registers, but this uses binary encoding for the minimum of 4 DFF's instead.`
188			`define STATE_test_logic_reset 4'hF
189			`define STATE_run_test_idle 4'hC
190			`define STATE_select_dr_scan 4'h7
191			`define STATE_capture_dr 4'h6
192			`define STATE_shift_dr 4'h2
193			`define STATE_exit1_dr 4'h1
194			`define STATE_pause_dr 4'h3
195			`define STATE_exit2_dr 4'h0
196			`define STATE_update_dr 4'h5
197			`define STATE_select_ir_scan 4'h4
198			`define STATE_capture_ir 4'hE
199			`define STATE_shift_ir 4'hA
200			`define STATE_exit1_ir 4'h9
201			`define STATE_pause_ir 4'hB
202			`define STATE_exit2_ir 4'h8
203			`define STATE_update_ir 4'hD
204
205			reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller
206			`reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal`
207
208			`// sequential part of the FSM`
209			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
210			`begin`
211			`if(trstn_pad_i == 0)`
212			TAP_state = `STATE_test_logic_reset;
213			`else`
214			`TAP_state = next_TAP_state;`
215			`end`
216
217
218			`// Determination of next state; purely combinatorial`
219			`always @ (TAP_state or tms_pad_i)`
220			`begin`
221			`case(TAP_state)`
222			`STATE_test_logic_reset:
223			`begin`
224			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
225			else next_TAP_state = `STATE_run_test_idle;
226			`end`
227			`STATE_run_test_idle:
228			`begin`
229			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
230			else next_TAP_state = `STATE_run_test_idle;
231			`end`
232			`STATE_select_dr_scan:
233			`begin`
234			if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
235			else next_TAP_state = `STATE_capture_dr;
236			`end`
237			`STATE_capture_dr:
238			`begin`
239			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
240			else next_TAP_state = `STATE_shift_dr;
241			`end`
242			`STATE_shift_dr:
243			`begin`
244			if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
245			else next_TAP_state = `STATE_shift_dr;
246			`end`
247			`STATE_exit1_dr:
248			`begin`
249			if(tms_pad_i) next_TAP_state = `STATE_update_dr;
250			else next_TAP_state = `STATE_pause_dr;
251			`end`
252			`STATE_pause_dr:
253			`begin`
254			if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
255			else next_TAP_state = `STATE_pause_dr;
256			`end`
257			`STATE_exit2_dr:
258			`begin`
259			if(tms_pad_i) next_TAP_state = `STATE_update_dr;
260			else next_TAP_state = `STATE_shift_dr;
261			`end`
262			`STATE_update_dr:
263			`begin`
264			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
265			else next_TAP_state = `STATE_run_test_idle;
266			`end`
267			`STATE_select_ir_scan:
268			`begin`
269			if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
270			else next_TAP_state = `STATE_capture_ir;
271			`end`
272			`STATE_capture_ir:
273			`begin`
274			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
275			else next_TAP_state = `STATE_shift_ir;
276			`end`
277			`STATE_shift_ir:
278			`begin`
279			if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
280			else next_TAP_state = `STATE_shift_ir;
281			`end`
282			`STATE_exit1_ir:
283			`begin`
284			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
285			else next_TAP_state = `STATE_pause_ir;
286			`end`
287			`STATE_pause_ir:
288			`begin`
289			if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
290			else next_TAP_state = `STATE_pause_ir;
291			`end`
292			`STATE_exit2_ir:
293			`begin`
294			if(tms_pad_i) next_TAP_state = `STATE_update_ir;
295			else next_TAP_state = `STATE_shift_ir;
296			`end`
297			`STATE_update_ir:
298			`begin`
299			if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
300			else next_TAP_state = `STATE_run_test_idle;
301			`end`
302			default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen
303			`endcase`
304			`end`
305
306
307			`// Outputs of state machine, pure combinatorial`
308			`always @ (TAP_state)`
309			`begin`
310			`// Default everything to 0, keeps the case statement simple`
311			`test_logic_reset = 1'b0;`
312			`run_test_idle = 1'b0;`
313			`select_dr_scan = 1'b0;`
314			`capture_dr = 1'b0;`
315			`shift_dr = 1'b0;`
316			`exit1_dr = 1'b0;`
317			`pause_dr = 1'b0;`
318			`exit2_dr = 1'b0;`
319			`update_dr = 1'b0;`
320			`select_ir_scan = 1'b0;`
321			`capture_ir = 1'b0;`
322			`shift_ir = 1'b0;`
323			`exit1_ir = 1'b0;`
324			`pause_ir = 1'b0;`
325			`exit2_ir = 1'b0;`
326			`update_ir = 1'b0;`
327
328			`case(TAP_state)`
329			`STATE_test_logic_reset: test_logic_reset = 1'b1;
330			`STATE_run_test_idle: run_test_idle = 1'b1;
331			`STATE_select_dr_scan: select_dr_scan = 1'b1;
332			`STATE_capture_dr: capture_dr = 1'b1;
333			`STATE_shift_dr: shift_dr = 1'b1;
334			`STATE_exit1_dr: exit1_dr = 1'b1;
335			`STATE_pause_dr: pause_dr = 1'b1;
336			`STATE_exit2_dr: exit2_dr = 1'b1;
337			`STATE_update_dr: update_dr = 1'b1;
338			`STATE_select_ir_scan: select_ir_scan = 1'b1;
339			`STATE_capture_ir: capture_ir = 1'b1;
340			`STATE_shift_ir: shift_ir = 1'b1;
341			`STATE_exit1_ir: exit1_ir = 1'b1;
342			`STATE_pause_ir: pause_ir = 1'b1;
343			`STATE_exit2_ir: exit2_ir = 1'b1;
344			`STATE_update_ir: update_ir = 1'b1;
345			`default: ;`
346			`endcase`
347			`end`
348
349			`/**********************************************************************************`
350			`* *`
351			`* End: TAP State Machine *`
352			`* *`
353			`**********************************************************************************/`
354
355
356
357			`/**********************************************************************************`
358			`* *`
359			`* jtag_ir: JTAG Instruction Register *`
360			`* *`
361			`**********************************************************************************/`
362			reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
363			reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg;
364			`wire instruction_tdo;`
365
366			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
367			`begin`
368			`if(trstn_pad_i == 0)`
369			jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
370			`else if (test_logic_reset == 1)`
371			jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
372			`else if(capture_ir)`
373			`jtag_ir <= 4'b0101; // This value is fixed for easier fault detection`
374			`else if(shift_ir)`
375			jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
376			`end`
377
378			`assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX`
379
380			`// Updating jtag_ir (Instruction Register)`
381			`// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1`
382			`always @ (negedge tck_pad_i or negedge trstn_pad_i)`
383			`begin`
384			`if(trstn_pad_i == 0)`
385			latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
386			`else if (test_logic_reset)`
387			latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
388			`else if(update_ir)`
389			`latched_jtag_ir <= jtag_ir;`
390			`end`
391
392			`/**********************************************************************************`
393			`* *`
394			`* End: jtag_ir *`
395			`* *`
396			`**********************************************************************************/`
397
398
399
400			`/**********************************************************************************`
401			`* *`
402			`* idcode logic *`
403			`* *`
404			`**********************************************************************************/`
405			`reg [31:0] idcode_reg;`
406			`wire idcode_tdo;`
407
408			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
409			`begin`
410			`if(trstn_pad_i == 0)`
411			idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
412			`else if (test_logic_reset)`
413			idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
414			`else if(idcode_select & capture_dr)`
415			idcode_reg <= `IDCODE_VALUE;
416			`else if(idcode_select & shift_dr)`
417			`idcode_reg <= {tdi_pad_i, idcode_reg[31:1]};`
418
419			`end`
420
421			`assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX`
422
423			`/**********************************************************************************`
424			`* *`
425			`* End: idcode logic *`
426			`* *`
427			`**********************************************************************************/`
428
429
430			`/**********************************************************************************`
431			`* *`
432			`* Bypass logic *`
433			`* *`
434			`**********************************************************************************/`
435			`wire bypassed_tdo;`
436			`reg bypass_reg; // This is a 1-bit register`
437
438			`always @ (posedge tck_pad_i or negedge trstn_pad_i)`
439			`begin`
440			`if (trstn_pad_i == 0)`
441			`bypass_reg <= 1'b0;`
442			`else if (test_logic_reset == 1)`
443			`bypass_reg <= 1'b0;`
444			`else if (bypass_select & capture_dr)`
445			`bypass_reg<= 1'b0;`
446			`else if(bypass_select & shift_dr)`
447			`bypass_reg<= tdi_pad_i;`
448			`end`
449
450			`assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX`
451
452			`/**********************************************************************************`
453			`* *`
454			`* End: Bypass logic *`
455			`* *`
456			`**********************************************************************************/`
457
458
459			`/**********************************************************************************`
460			`* *`
461			`* Selecting active data register *`
462			`* *`
463			`**********************************************************************************/`
464			`always @ (latched_jtag_ir)`
465			`begin`
466			`extest_select = 1'b0;`
467			`sample_preload_select = 1'b0;`
468			`idcode_select = 1'b0;`
469			`mbist_select = 1'b0;`
470			`debug_select = 1'b0;`
471			`bypass_select = 1'b0;`
472
473			`case(latched_jtag_ir) /* synthesis parallel_case */`
474			`EXTEST: extest_select = 1'b1; // External test
475			`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
476			`IDCODE: idcode_select = 1'b1; // ID Code
477			`MBIST: mbist_select = 1'b1; // Mbist test
478			`DEBUG: debug_select = 1'b1; // Debug
479			`BYPASS: bypass_select = 1'b1; // BYPASS
480			`default: bypass_select = 1'b1; // BYPASS`
481			`endcase`
482			`end`
483
484
485			`/**********************************************************************************`
486			`* *`
487			`* Multiplexing TDO data *`
488			`* *`
489			`**********************************************************************************/`
490			`reg tdo_mux_out; // really just a wire`
491
492			`always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or`
493			`debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or`
494			`bs_chain_tdo_i)`
495			`begin`
496			`if(shift_ir)`
497			`tdo_mux_out = instruction_tdo;`
498			`else`
499			`begin`
500			`case(latched_jtag_ir) // synthesis parallel_case`
501			`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
502			`DEBUG: tdo_mux_out = debug_tdo_i; // Debug
503			`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdo_i; // Sampling/Preloading
504			`EXTEST: tdo_mux_out = bs_chain_tdo_i; // External test
505			`MBIST: tdo_mux_out = mbist_tdo_i; // Mbist test
506			`default: tdo_mux_out = bypassed_tdo; // BYPASS instruction`
507			`endcase`
508			`end`
509			`end`
510
511
512			`// TDO changes state at negative edge of TCK`
513			`always @ (negedge tck_pad_i)`
514			`begin`
515			`tdo_pad_o = tdo_mux_out;`
516			`end`
517
518
519			`// Tristate control for tdo_pad_o pin`
520			`always @ (posedge tck_pad_i)`
521			`begin`
522			`tdo_padoe_o <= shift_ir \| shift_dr;`
523			`end`
524			`/**********************************************************************************`
525			`* *`
526			`* End: Multiplexing TDO data *`
527			`* *`
528			`**********************************************************************************/`
529
530			`endmodule`