OpenCores
URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.cache/] [ip/] [2017.4/] [077a94985ac208e4.logs/] [runme.log] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 vv_gulyaev 
 
2 
*** Running vivado
3 
    with args -log axi_uartlite_module.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source axi_uartlite_module.tcl
4 
 
5 
 
6 
****** Vivado v2017.4 (64-bit)
7 
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
8 
  **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
9 
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
10 
 
11 
source axi_uartlite_module.tcl -notrace
12 
Command: synth_design -top axi_uartlite_module -part xc7k325tffg900-2 -mode out_of_context
13 
Starting synth_design
14 
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
15 
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
16 
INFO: Launching helper process for spawning children vivado processes
17 
INFO: Helper process launched with PID 5822
18 
---------------------------------------------------------------------------------
19 
Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1398.680 ; gain = 86.000 ; free physical = 1033 ; free virtual = 93527
20 
---------------------------------------------------------------------------------
21 
INFO: [Synth 8-638] synthesizing module 'axi_uartlite_module' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:86]
22 
        Parameter C_FAMILY bound to: kintex7 - type: string
23 
        Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
24 
        Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
25 
        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
26 
        Parameter C_BAUDRATE bound to: 38400 - type: integer
27 
        Parameter C_DATA_BITS bound to: 8 - type: integer
28 
        Parameter C_USE_PARITY bound to: 0 - type: integer
29 
        Parameter C_ODD_PARITY bound to: 0 - type: integer
30 
INFO: [Synth 8-3491] module 'axi_uartlite' declared at '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2090' bound to instance 'U0' of component 'axi_uartlite' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:161]
31 
INFO: [Synth 8-638] synthesizing module 'axi_uartlite' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2160]
32 
        Parameter C_FAMILY bound to: kintex7 - type: string
33 
        Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
34 
        Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
35 
        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
36 
        Parameter C_BAUDRATE bound to: 38400 - type: integer
37 
        Parameter C_DATA_BITS bound to: 8 - type: integer
38 
        Parameter C_USE_PARITY bound to: 0 - type: integer
39 
        Parameter C_ODD_PARITY bound to: 0 - type: integer
40 
INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2109]
41 
INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2110]
42 
INFO: [Synth 8-638] synthesizing module 'uartlite_core' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1615]
43 
        Parameter C_FAMILY bound to: kintex7 - type: string
44 
        Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
45 
        Parameter C_BAUDRATE bound to: 38400 - type: integer
46 
        Parameter C_DATA_BITS bound to: 8 - type: integer
47 
        Parameter C_USE_PARITY bound to: 0 - type: integer
48 
        Parameter C_ODD_PARITY bound to: 0 - type: integer
49 
INFO: [Synth 8-638] synthesizing module 'baudrate' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1418]
50 
        Parameter C_RATIO bound to: 163 - type: integer
51 
INFO: [Synth 8-256] done synthesizing module 'baudrate' (1#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1418]
52 
INFO: [Synth 8-3919] null assignment ignored [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1881]
53 
INFO: [Synth 8-638] synthesizing module 'uartlite_rx' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:909]
54 
        Parameter C_FAMILY bound to: kintex7 - type: string
55 
        Parameter C_DATA_BITS bound to: 8 - type: integer
56 
        Parameter C_USE_PARITY bound to: 0 - type: integer
57 
        Parameter C_ODD_PARITY bound to: 0 - type: integer
58 
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:106]
59 
        Parameter C_CDC_TYPE bound to: 1 - type: integer
60 
        Parameter C_RESET_STATE bound to: 0 - type: integer
61 
        Parameter C_SINGLE_BIT bound to: 1 - type: integer
62 
        Parameter C_FLOP_INPUT bound to: 0 - type: integer
63 
        Parameter C_VECTOR_WIDTH bound to: 32 - type: integer
64 
        Parameter C_MTBF_STAGES bound to: 4 - type: integer
65 
        Parameter INIT bound to: 1'b0
66 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:514]
67 
        Parameter INIT bound to: 1'b0
68 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:545]
69 
        Parameter INIT bound to: 1'b0
70 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:554]
71 
        Parameter INIT bound to: 1'b0
72 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:564]
73 
        Parameter INIT bound to: 1'b0
74 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:574]
75 
        Parameter INIT bound to: 1'b0
76 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:584]
77 
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (2#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:106]
78 
INFO: [Synth 8-638] synthesizing module 'dynshreg_i_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
79 
        Parameter C_DEPTH bound to: 16 - type: integer
80 
        Parameter C_DWIDTH bound to: 1 - type: integer
81 
        Parameter C_INIT_VALUE bound to: 1'b0
82 
        Parameter C_FAMILY bound to: kintex7 - type: string
83 
INFO: [Synth 8-256] done synthesizing module 'dynshreg_i_f' (3#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
84 
INFO: [Synth 8-638] synthesizing module 'srl_fifo_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
85 
        Parameter C_DWIDTH bound to: 8 - type: integer
86 
        Parameter C_DEPTH bound to: 16 - type: integer
87 
        Parameter C_FAMILY bound to: kintex7 - type: string
88 
INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
89 
        Parameter C_DWIDTH bound to: 8 - type: integer
90 
        Parameter C_DEPTH bound to: 16 - type: integer
91 
        Parameter C_FAMILY bound to: kintex7 - type: string
92 
INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
93 
        Parameter C_SIZE bound to: 5 - type: integer
94 
        Parameter C_FAMILY bound to: kintex7 - type: string
95 
INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (4#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
96 
INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
97 
        Parameter C_DEPTH bound to: 16 - type: integer
98 
        Parameter C_DWIDTH bound to: 8 - type: integer
99 
        Parameter C_FAMILY bound to: kintex7 - type: string
100 
INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (5#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
101 
INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (6#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
102 
INFO: [Synth 8-256] done synthesizing module 'srl_fifo_f' (7#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
103 
INFO: [Synth 8-256] done synthesizing module 'uartlite_rx' (8#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:909]
104 
INFO: [Synth 8-638] synthesizing module 'uartlite_tx' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
105 
        Parameter C_FAMILY bound to: kintex7 - type: string
106 
        Parameter C_DATA_BITS bound to: 8 - type: integer
107 
        Parameter C_USE_PARITY bound to: 0 - type: integer
108 
        Parameter C_ODD_PARITY bound to: 0 - type: integer
109 
INFO: [Synth 8-638] synthesizing module 'dynshreg_i_f__parameterized0' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
110 
        Parameter C_DEPTH bound to: 16 - type: integer
111 
        Parameter C_DWIDTH bound to: 1 - type: integer
112 
        Parameter C_INIT_VALUE bound to: 16'b1000000000000000
113 
        Parameter C_FAMILY bound to: kintex7 - type: string
114 
INFO: [Synth 8-256] done synthesizing module 'dynshreg_i_f__parameterized0' (8#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
115 
INFO: [Synth 8-256] done synthesizing module 'uartlite_tx' (9#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
116 
INFO: [Synth 8-256] done synthesizing module 'uartlite_core' (10#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1615]
117 
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
118 
        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
119 
        Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
120 
        Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000000001111
121 
        Parameter C_USE_WSTRB bound to: 0 - type: integer
122 
        Parameter C_DPHASE_TIMEOUT bound to: 0 - type: integer
123 
        Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
124 
        Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
125 
        Parameter C_FAMILY bound to: kintex7 - type: string
126 
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
127 
        Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
128 
        Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
129 
        Parameter C_IPIF_ABUS_WIDTH bound to: 4 - type: integer
130 
        Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
131 
        Parameter C_S_AXI_MIN_SIZE bound to: 15 - type: integer
132 
        Parameter C_USE_WSTRB bound to: 0 - type: integer
133 
        Parameter C_DPHASE_TIMEOUT bound to: 0 - type: integer
134 
        Parameter C_FAMILY bound to: kintex7 - type: string
135 
INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
136 
        Parameter C_BUS_AWIDTH bound to: 4 - type: integer
137 
        Parameter C_S_AXI_MIN_SIZE bound to: 15 - type: integer
138 
        Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
139 
        Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
140 
        Parameter C_FAMILY bound to: nofamily - type: string
141 
INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
142 
        Parameter C_AB bound to: 2 - type: integer
143 
        Parameter C_AW bound to: 2 - type: integer
144 
        Parameter C_BAR bound to: 2'b00
145 
        Parameter C_FAMILY bound to: nofamily - type: string
146 
INFO: [Synth 8-256] done synthesizing module 'pselect_f' (11#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
147 
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
148 
        Parameter C_AB bound to: 2 - type: integer
149 
        Parameter C_AW bound to: 2 - type: integer
150 
        Parameter C_BAR bound to: 2'b01
151 
        Parameter C_FAMILY bound to: nofamily - type: string
152 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (11#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
153 
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
154 
        Parameter C_AB bound to: 2 - type: integer
155 
        Parameter C_AW bound to: 2 - type: integer
156 
        Parameter C_BAR bound to: 2'b10
157 
        Parameter C_FAMILY bound to: nofamily - type: string
158 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (11#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
159 
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
160 
        Parameter C_AB bound to: 2 - type: integer
161 
        Parameter C_AW bound to: 2 - type: integer
162 
        Parameter C_BAR bound to: 2'b11
163 
        Parameter C_FAMILY bound to: nofamily - type: string
164 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (11#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
165 
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (12#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
166 
INFO: [Synth 8-226] default block is never used [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
167 
WARNING: [Synth 8-6014] Unused sequential element is_read_reg was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2447]
168 
WARNING: [Synth 8-6014] Unused sequential element is_write_reg was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2448]
169 
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (13#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
170 
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (14#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
171 
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite' (15#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2160]
172 
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite_module' (16#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:86]
173 
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[2]
174 
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[3]
175 
WARNING: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW
176 
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3]
177 
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2]
178 
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1]
179 
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0]
180 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk
181 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn
182 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[31]
183 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[30]
184 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[29]
185 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[28]
186 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[27]
187 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[26]
188 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[25]
189 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[24]
190 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[23]
191 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[22]
192 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[21]
193 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[20]
194 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[19]
195 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[18]
196 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[17]
197 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[16]
198 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[15]
199 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[14]
200 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[13]
201 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[12]
202 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[11]
203 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[10]
204 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[9]
205 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[8]
206 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[7]
207 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[6]
208 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[5]
209 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[4]
210 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[3]
211 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[2]
212 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[1]
213 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[0]
214 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn
215 
WARNING: [Synth 8-3331] design uartlite_core has unconnected port bus2ip_cs
216 
---------------------------------------------------------------------------------
217 
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1441.219 ; gain = 128.539 ; free physical = 1041 ; free virtual = 93536
218 
---------------------------------------------------------------------------------
219 
 
220 
Report Check Netlist:
221 
+------+------------------+-------+---------+-------+------------------+
222 
|      |Item              |Errors |Warnings |Status |Description       |
223 
+------+------------------+-------+---------+-------+------------------+
224 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
225 
+------+------------------+-------+---------+-------+------------------+
226 
---------------------------------------------------------------------------------
227 
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1441.219 ; gain = 128.539 ; free physical = 1040 ; free virtual = 93536
228 
---------------------------------------------------------------------------------
229 
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
230 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
231 
INFO: [Device 21-403] Loading part xc7k325tffg900-2
232 
INFO: [Project 1-570] Preparing netlist for logic optimization
233 
 
234 
Processing XDC Constraints
235 
Initializing timing engine
236 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc] for cell 'U0'
237 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc] for cell 'U0'
238 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'U0'
239 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'U0'
240 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'U0'
241 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'U0'
242 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc]
243 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc]
244 
Completed Processing XDC Constraints
245 
 
246 
INFO: [Project 1-111] Unisim Transformation Summary:
247 
  A total of 6 instances were transformed.
248 
  FDR => FDRE: 6 instances
249 
 
250 
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1866.391 ; gain = 1.000 ; free physical = 764 ; free virtual = 93145
251 
---------------------------------------------------------------------------------
252 
Finished Constraint Validation : Time (s): cpu = 00:00:29 ; elapsed = 00:00:59 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 947 ; free virtual = 93323
253 
---------------------------------------------------------------------------------
254 
---------------------------------------------------------------------------------
255 
Start Loading Part and Timing Information
256 
---------------------------------------------------------------------------------
257 
Loading part: xc7k325tffg900-2
258 
---------------------------------------------------------------------------------
259 
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:29 ; elapsed = 00:00:59 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 947 ; free virtual = 93323
260 
---------------------------------------------------------------------------------
261 
---------------------------------------------------------------------------------
262 
Start Applying 'set_property' XDC Constraints
263 
---------------------------------------------------------------------------------
264 
Applied set_property DONT_TOUCH = true for U0. (constraint file  /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc, line 9).
265 
---------------------------------------------------------------------------------
266 
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:59 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 948 ; free virtual = 93325
267 
---------------------------------------------------------------------------------
268 
INFO: [Synth 8-5546] ROM "EN_16x_Baud" won't be mapped to RAM because it is too sparse
269 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
270 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
271 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
272 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
273 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
274 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
275 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
276 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
277 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
278 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
279 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
280 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
281 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
282 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
283 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
284 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
285 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
286 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
287 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
288 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
289 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
290 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
291 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
292 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
293 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
294 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
295 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
296 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
297 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
298 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
299 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
300 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
301 
INFO: [Synth 8-5546] ROM "fifo_full_p1" won't be mapped to RAM because it is too sparse
302 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
303 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
304 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
305 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
306 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
307 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
308 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
309 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
310 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
311 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
312 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
313 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
314 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
315 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
316 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
317 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
318 
INFO: [Synth 8-5544] ROM "mux_sel_is_zero" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
319 
INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
320 
INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
321 
INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
322 
INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
323 
---------------------------------------------------------------------------------
324 
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:59 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 940 ; free virtual = 93317
325 
---------------------------------------------------------------------------------
326 
 
327 
Report RTL Partitions:
328 
+-+--------------+------------+----------+
329 
| |RTL Partition |Replication |Instances |
330 
+-+--------------+------------+----------+
331 
+-+--------------+------------+----------+
332 
---------------------------------------------------------------------------------
333 
Start RTL Component Statistics
334 
---------------------------------------------------------------------------------
335 
Detailed RTL Component Info :
336 
+---Adders :
337 
           2 Input      8 Bit       Adders := 1
338 
           3 Input      5 Bit       Adders := 2
339 
           2 Input      3 Bit       Adders := 1
340 
+---Registers :
341 
                       32 Bit    Registers := 1
342 
                        8 Bit    Registers := 1
343 
                        5 Bit    Registers := 2
344 
                        4 Bit    Registers := 1
345 
                        3 Bit    Registers := 1
346 
                        2 Bit    Registers := 3
347 
                        1 Bit    Registers := 46
348 
+---Muxes :
349 
           2 Input      8 Bit        Muxes := 3
350 
           2 Input      4 Bit        Muxes := 1
351 
           2 Input      3 Bit        Muxes := 1
352 
           7 Input      2 Bit        Muxes := 1
353 
           2 Input      2 Bit        Muxes := 2
354 
           2 Input      1 Bit        Muxes := 43
355 
---------------------------------------------------------------------------------
356 
Finished RTL Component Statistics
357 
---------------------------------------------------------------------------------
358 
---------------------------------------------------------------------------------
359 
Start RTL Hierarchical Component Statistics
360 
---------------------------------------------------------------------------------
361 
Hierarchical RTL Component report
362 
Module baudrate
363 
Detailed RTL Component Info :
364 
+---Adders :
365 
           2 Input      8 Bit       Adders := 1
366 
+---Registers :
367 
                        8 Bit    Registers := 1
368 
                        1 Bit    Registers := 1
369 
+---Muxes :
370 
           2 Input      8 Bit        Muxes := 1
371 
           2 Input      1 Bit        Muxes := 1
372 
Module cntr_incr_decr_addn_f
373 
Detailed RTL Component Info :
374 
+---Adders :
375 
           3 Input      5 Bit       Adders := 1
376 
+---Registers :
377 
                        5 Bit    Registers := 1
378 
Module srl_fifo_rbu_f
379 
Detailed RTL Component Info :
380 
+---Registers :
381 
                        1 Bit    Registers := 3
382 
+---Muxes :
383 
           2 Input      1 Bit        Muxes := 3
384 
Module uartlite_rx
385 
Detailed RTL Component Info :
386 
+---Registers :
387 
                        1 Bit    Registers := 15
388 
+---Muxes :
389 
           2 Input      1 Bit        Muxes := 12
390 
Module uartlite_tx
391 
Detailed RTL Component Info :
392 
+---Adders :
393 
           2 Input      3 Bit       Adders := 1
394 
+---Registers :
395 
                        3 Bit    Registers := 1
396 
                        1 Bit    Registers := 6
397 
+---Muxes :
398 
           2 Input      3 Bit        Muxes := 1
399 
           2 Input      1 Bit        Muxes := 10
400 
Module uartlite_core
401 
Detailed RTL Component Info :
402 
+---Registers :
403 
                        1 Bit    Registers := 7
404 
+---Muxes :
405 
           2 Input      8 Bit        Muxes := 2
406 
           2 Input      1 Bit        Muxes := 2
407 
Module pselect_f
408 
Detailed RTL Component Info :
409 
+---Muxes :
410 
           2 Input      1 Bit        Muxes := 1
411 
Module pselect_f__parameterized0
412 
Detailed RTL Component Info :
413 
+---Muxes :
414 
           2 Input      1 Bit        Muxes := 1
415 
Module pselect_f__parameterized1
416 
Detailed RTL Component Info :
417 
+---Muxes :
418 
           2 Input      1 Bit        Muxes := 1
419 
Module pselect_f__parameterized2
420 
Detailed RTL Component Info :
421 
+---Muxes :
422 
           2 Input      1 Bit        Muxes := 1
423 
Module address_decoder
424 
Detailed RTL Component Info :
425 
+---Registers :
426 
                        1 Bit    Registers := 6
427 
Module slave_attachment
428 
Detailed RTL Component Info :
429 
+---Registers :
430 
                       32 Bit    Registers := 1
431 
                        4 Bit    Registers := 1
432 
                        2 Bit    Registers := 3
433 
                        1 Bit    Registers := 5
434 
+---Muxes :
435 
           2 Input      4 Bit        Muxes := 1
436 
           7 Input      2 Bit        Muxes := 1
437 
           2 Input      2 Bit        Muxes := 2
438 
           2 Input      1 Bit        Muxes := 8
439 
---------------------------------------------------------------------------------
440 
Finished RTL Hierarchical Component Statistics
441 
---------------------------------------------------------------------------------
442 
---------------------------------------------------------------------------------
443 
Start Part Resource Summary
444 
---------------------------------------------------------------------------------
445 
Part Resources:
446 
DSPs: 840 (col length:140)
447 
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
448 
---------------------------------------------------------------------------------
449 
Finished Part Resource Summary
450 
---------------------------------------------------------------------------------
451 
---------------------------------------------------------------------------------
452 
Start Cross Boundary and Area Optimization
453 
---------------------------------------------------------------------------------
454 
WARNING: [Synth 8-6014] Unused sequential element AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN[0].cs_out_i_reg was removed.  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2004]
455 
INFO: [Synth 8-5546] ROM "UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud" won't be mapped to RAM because it is too sparse
456 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[31]
457 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[30]
458 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[29]
459 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[28]
460 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[27]
461 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[26]
462 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[25]
463 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[24]
464 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[23]
465 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[22]
466 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[21]
467 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[20]
468 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[19]
469 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[18]
470 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[17]
471 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[16]
472 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[15]
473 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[14]
474 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[13]
475 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[12]
476 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[11]
477 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[10]
478 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[9]
479 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[8]
480 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[3]
481 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[2]
482 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[1]
483 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[0]
484 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_uartlite.
485 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_uartlite.
486 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/underflow_i_reg) is unused and will be removed from module axi_uartlite.
487 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/overflow_i_reg) is unused and will be removed from module axi_uartlite.
488 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/underflow_i_reg) is unused and will be removed from module axi_uartlite.
489 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/overflow_i_reg) is unused and will be removed from module axi_uartlite.
490 
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[1]) is unused and will be removed from module axi_uartlite.
491 
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[0]) is unused and will be removed from module axi_uartlite.
492 
---------------------------------------------------------------------------------
493 
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:01:00 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 930 ; free virtual = 93306
494 
---------------------------------------------------------------------------------
495 
 
496 
Report RTL Partitions:
497 
+-+--------------+------------+----------+
498 
| |RTL Partition |Replication |Instances |
499 
+-+--------------+------------+----------+
500 
+-+--------------+------------+----------+
501 
---------------------------------------------------------------------------------
502 
Start Applying XDC Timing Constraints
503 
---------------------------------------------------------------------------------
504 
---------------------------------------------------------------------------------
505 
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:01:11 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 804 ; free virtual = 93181
506 
---------------------------------------------------------------------------------
507 
---------------------------------------------------------------------------------
508 
Start Timing Optimization
509 
---------------------------------------------------------------------------------
510 
---------------------------------------------------------------------------------
511 
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 801 ; free virtual = 93177
512 
---------------------------------------------------------------------------------
513 
 
514 
Report RTL Partitions:
515 
+-+--------------+------------+----------+
516 
| |RTL Partition |Replication |Instances |
517 
+-+--------------+------------+----------+
518 
+-+--------------+------------+----------+
519 
---------------------------------------------------------------------------------
520 
Start Technology Mapping
521 
---------------------------------------------------------------------------------
522 
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0]) is unused and will be removed from module axi_uartlite.
523 
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0]) is unused and will be removed from module axi_uartlite.
524 
---------------------------------------------------------------------------------
525 
Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 801 ; free virtual = 93178
526 
---------------------------------------------------------------------------------
527 
 
528 
Report RTL Partitions:
529 
+-+--------------+------------+----------+
530 
| |RTL Partition |Replication |Instances |
531 
+-+--------------+------------+----------+
532 
+-+--------------+------------+----------+
533 
---------------------------------------------------------------------------------
534 
Start IO Insertion
535 
---------------------------------------------------------------------------------
536 
---------------------------------------------------------------------------------
537 
Start Flattening Before IO Insertion
538 
---------------------------------------------------------------------------------
539 
---------------------------------------------------------------------------------
540 
Finished Flattening Before IO Insertion
541 
---------------------------------------------------------------------------------
542 
---------------------------------------------------------------------------------
543 
Start Final Netlist Cleanup
544 
---------------------------------------------------------------------------------
545 
---------------------------------------------------------------------------------
546 
Finished Final Netlist Cleanup
547 
---------------------------------------------------------------------------------
548 
---------------------------------------------------------------------------------
549 
Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 801 ; free virtual = 93178
550 
---------------------------------------------------------------------------------
551 
 
552 
Report Check Netlist:
553 
+------+------------------+-------+---------+-------+------------------+
554 
|      |Item              |Errors |Warnings |Status |Description       |
555 
+------+------------------+-------+---------+-------+------------------+
556 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
557 
+------+------------------+-------+---------+-------+------------------+
558 
---------------------------------------------------------------------------------
559 
Start Renaming Generated Instances
560 
---------------------------------------------------------------------------------
561 
---------------------------------------------------------------------------------
562 
Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 801 ; free virtual = 93178
563 
---------------------------------------------------------------------------------
564 
 
565 
Report RTL Partitions:
566 
+-+--------------+------------+----------+
567 
| |RTL Partition |Replication |Instances |
568 
+-+--------------+------------+----------+
569 
+-+--------------+------------+----------+
570 
---------------------------------------------------------------------------------
571 
Start Rebuilding User Hierarchy
572 
---------------------------------------------------------------------------------
573 
---------------------------------------------------------------------------------
574 
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
575 
---------------------------------------------------------------------------------
576 
---------------------------------------------------------------------------------
577 
Start Renaming Generated Ports
578 
---------------------------------------------------------------------------------
579 
---------------------------------------------------------------------------------
580 
Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
581 
---------------------------------------------------------------------------------
582 
---------------------------------------------------------------------------------
583 
Start Handling Custom Attributes
584 
---------------------------------------------------------------------------------
585 
---------------------------------------------------------------------------------
586 
Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
587 
---------------------------------------------------------------------------------
588 
---------------------------------------------------------------------------------
589 
Start Renaming Generated Nets
590 
---------------------------------------------------------------------------------
591 
---------------------------------------------------------------------------------
592 
Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
593 
---------------------------------------------------------------------------------
594 
---------------------------------------------------------------------------------
595 
Start ROM, RAM, DSP and Shift Register Reporting
596 
---------------------------------------------------------------------------------
597 
 
598 
Static Shift Register Report:
599 
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
600 
|Module Name  | RTL Name                                                                         | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
601 
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
602 
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[15][0]            | 16     | 1     | NO           | NO                 | YES               | 1      | 0       |
603 
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[15][0] | 16     | 1     | NO           | NO                 | YES               | 1      | 0       |
604 
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
605 
 
606 
 
607 
Dynamic Shift Register Report:
608 
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
609 
|Module Name | RTL Name                  | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
610 
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
611 
|dsrl        | INFERRED_GEN.data_reg[15] | 16     | 1          | 1      | 0       | 0      | 0      | 0      |
612 
|dsrl__1     | INFERRED_GEN.data_reg[15] | 16     | 8          | 8      | 0       | 0      | 0      | 0      |
613 
|dsrl__2     | INFERRED_GEN.data_reg[15] | 16     | 1          | 1      | 0       | 0      | 0      | 0      |
614 
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
615 
 
616 
---------------------------------------------------------------------------------
617 
Finished ROM, RAM, DSP and Shift Register Reporting
618 
---------------------------------------------------------------------------------
619 
---------------------------------------------------------------------------------
620 
Start Writing Synthesis Report
621 
---------------------------------------------------------------------------------
622 
 
623 
Report BlackBoxes:
624 
+-+--------------+----------+
625 
| |BlackBox name |Instances |
626 
+-+--------------+----------+
627 
+-+--------------+----------+
628 
 
629 
Report Cell Usage:
630 
+------+-------+------+
631 
|      |Cell   |Count |
632 
+------+-------+------+
633 
|1     |LUT1   |     1|
634 
|2     |LUT2   |    14|
635 
|3     |LUT3   |    19|
636 
|4     |LUT4   |    17|
637 
|5     |LUT5   |    44|
638 
|6     |LUT6   |    17|
639 
|7     |SRL16E |    18|
640 
|8     |FDR    |     4|
641 
|9     |FDRE   |    72|
642 
|10    |FDSE   |    16|
643 
+------+-------+------+
644 
 
645 
Report Instance Areas:
646 
+------+--------------------------------------------------------------------------+-----------------------------+------+
647 
|      |Instance                                                                  |Module                       |Cells |
648 
+------+--------------------------------------------------------------------------+-----------------------------+------+
649 
|1     |top                                                                       |                             |   222|
650 
|2     |  U0                                                                      |axi_uartlite                 |   222|
651 
|3     |    AXI_LITE_IPIF_I                                                       |axi_lite_ipif                |    65|
652 
|4     |      I_SLAVE_ATTACHMENT                                                  |slave_attachment             |    65|
653 
|5     |        I_DECODER                                                         |address_decoder              |    37|
654 
|6     |          \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I  |pselect_f                    |     1|
655 
|7     |          \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I  |pselect_f__parameterized1    |     1|
656 
|8     |    UARTLITE_CORE_I                                                       |uartlite_core                |   157|
657 
|9     |      BAUD_RATE_I                                                         |baudrate                     |    22|
658 
|10    |      UARTLITE_RX_I                                                       |uartlite_rx                  |    77|
659 
|11    |        DELAY_16_I                                                        |dynshreg_i_f                 |    17|
660 
|12    |        INPUT_DOUBLE_REGS3                                                |cdc_sync                     |     5|
661 
|13    |        SRL_FIFO_I                                                        |srl_fifo_f_0                 |    28|
662 
|14    |          I_SRL_FIFO_RBU_F                                                |srl_fifo_rbu_f_1             |    28|
663 
|15    |            CNTR_INCR_DECR_ADDN_F_I                                       |cntr_incr_decr_addn_f_2      |    17|
664 
|16    |            DYNSHREG_F_I                                                  |dynshreg_f_3                 |     9|
665 
|17    |      UARTLITE_TX_I                                                       |uartlite_tx                  |    49|
666 
|18    |        MID_START_BIT_SRL16_I                                             |dynshreg_i_f__parameterized0 |     3|
667 
|19    |        SRL_FIFO_I                                                        |srl_fifo_f                   |    31|
668 
|20    |          I_SRL_FIFO_RBU_F                                                |srl_fifo_rbu_f               |    31|
669 
|21    |            CNTR_INCR_DECR_ADDN_F_I                                       |cntr_incr_decr_addn_f        |    17|
670 
|22    |            DYNSHREG_F_I                                                  |dynshreg_f                   |    13|
671 
+------+--------------------------------------------------------------------------+-----------------------------+------+
672 
---------------------------------------------------------------------------------
673 
Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:01:12 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 802 ; free virtual = 93178
674 
---------------------------------------------------------------------------------
675 
Synthesis finished with 0 errors, 0 critical warnings and 77 warnings.
676 
Synthesis Optimization Runtime : Time (s): cpu = 00:00:26 ; elapsed = 00:00:34 . Memory (MB): peak = 1866.391 ; gain = 128.539 ; free physical = 855 ; free virtual = 93231
677 
Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:01:13 . Memory (MB): peak = 1866.391 ; gain = 553.711 ; free physical = 855 ; free virtual = 93231
678 
INFO: [Project 1-571] Translating synthesized netlist
679 
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
680 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
681 
INFO: [Project 1-570] Preparing netlist for logic optimization
682 
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
683 
INFO: [Project 1-111] Unisim Transformation Summary:
684 
  A total of 4 instances were transformed.
685 
  FDR => FDRE: 4 instances
686 
 
687 
INFO: [Common 17-83] Releasing license: Synthesis
688 
82 Infos, 122 Warnings, 0 Critical Warnings and 0 Errors encountered.
689 
synth_design completed successfully
690 
synth_design: Time (s): cpu = 00:00:40 ; elapsed = 00:01:14 . Memory (MB): peak = 1866.391 ; gain = 589.535 ; free physical = 843 ; free virtual = 93220
691 
INFO: [Common 17-1381] The checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/axi_uartlite_module_synth_1/axi_uartlite_module.dcp' has been generated.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.