OpenCores
URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.cache/] [ip/] [2017.4/] [9f55fc6c5f1def66.logs/] [runme.log] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev 
 
2 
*** Running vivado
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    with args -log microblaze_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source microblaze_0.tcl
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5 
 
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****** Vivado v2017.4 (64-bit)
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  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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  **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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source microblaze_0.tcl -notrace
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Command: synth_design -top microblaze_0 -part xc7k325tffg900-2 -mode out_of_context
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 18140
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1400.574 ; gain = 88.004 ; free physical = 807 ; free virtual = 93482
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---------------------------------------------------------------------------------
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INFO: [Synth 8-638] synthesizing module 'microblaze_0' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/synth/microblaze_0.vhd:107]
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        Parameter C_SCO bound to: 0 - type: integer
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        Parameter C_FREQ bound to: 0 - type: integer
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        Parameter C_USE_CONFIG_RESET bound to: 0 - type: integer
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        Parameter C_NUM_SYNC_FF_CLK bound to: 2 - type: integer
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        Parameter C_NUM_SYNC_FF_CLK_IRQ bound to: 1 - type: integer
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        Parameter C_NUM_SYNC_FF_CLK_DEBUG bound to: 2 - type: integer
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        Parameter C_NUM_SYNC_FF_DBG_CLK bound to: 1 - type: integer
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        Parameter C_NUM_SYNC_FF_DBG_TRACE_CLK bound to: 2 - type: integer
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        Parameter C_FAULT_TOLERANT bound to: 0 - type: integer
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        Parameter C_ECC_USE_CE_EXCEPTION bound to: 0 - type: integer
32 
        Parameter C_LOCKSTEP_SLAVE bound to: 0 - type: integer
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        Parameter C_LOCKSTEP_MASTER bound to: 0 - type: integer
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        Parameter C_ENDIANNESS bound to: 1 - type: integer
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        Parameter C_FAMILY bound to: kintex7 - type: string
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        Parameter C_DATA_SIZE bound to: 32 - type: integer
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        Parameter C_INSTR_SIZE bound to: 32 - type: integer
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        Parameter C_IADDR_SIZE bound to: 32 - type: integer
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        Parameter C_PIADDR_SIZE bound to: 32 - type: integer
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        Parameter C_DADDR_SIZE bound to: 32 - type: integer
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        Parameter C_INSTANCE bound to: microblaze_0 - type: string
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        Parameter C_AVOID_PRIMITIVES bound to: 0 - type: integer
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        Parameter C_AREA_OPTIMIZED bound to: 0 - type: integer
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        Parameter C_OPTIMIZATION bound to: 0 - type: integer
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        Parameter C_INTERCONNECT bound to: 2 - type: integer
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        Parameter C_BASE_VECTORS bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000
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        Parameter C_M_AXI_DP_THREAD_ID_WIDTH bound to: 1 - type: integer
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        Parameter C_M_AXI_DP_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M_AXI_DP_ADDR_WIDTH bound to: 32 - type: integer
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        Parameter C_M_AXI_DP_EXCLUSIVE_ACCESS bound to: 0 - type: integer
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        Parameter C_M_AXI_D_BUS_EXCEPTION bound to: 0 - type: integer
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        Parameter C_M_AXI_IP_THREAD_ID_WIDTH bound to: 1 - type: integer
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        Parameter C_M_AXI_IP_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M_AXI_IP_ADDR_WIDTH bound to: 32 - type: integer
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        Parameter C_M_AXI_I_BUS_EXCEPTION bound to: 0 - type: integer
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        Parameter C_D_LMB bound to: 1 - type: integer
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        Parameter C_D_AXI bound to: 1 - type: integer
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        Parameter C_I_LMB bound to: 1 - type: integer
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        Parameter C_I_AXI bound to: 0 - type: integer
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        Parameter C_USE_MSR_INSTR bound to: 0 - type: integer
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        Parameter C_USE_PCMP_INSTR bound to: 0 - type: integer
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        Parameter C_USE_BARREL bound to: 0 - type: integer
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        Parameter C_USE_DIV bound to: 0 - type: integer
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        Parameter C_USE_HW_MUL bound to: 1 - type: integer
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        Parameter C_USE_FPU bound to: 0 - type: integer
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        Parameter C_USE_REORDER_INSTR bound to: 0 - type: integer
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        Parameter C_UNALIGNED_EXCEPTIONS bound to: 0 - type: integer
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        Parameter C_ILL_OPCODE_EXCEPTION bound to: 0 - type: integer
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        Parameter C_DIV_ZERO_EXCEPTION bound to: 0 - type: integer
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        Parameter C_FPU_EXCEPTION bound to: 0 - type: integer
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        Parameter C_FSL_LINKS bound to: 0 - type: integer
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        Parameter C_USE_EXTENDED_FSL_INSTR bound to: 0 - type: integer
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        Parameter C_FSL_EXCEPTION bound to: 0 - type: integer
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        Parameter C_USE_STACK_PROTECTION bound to: 0 - type: integer
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        Parameter C_IMPRECISE_EXCEPTIONS bound to: 0 - type: integer
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        Parameter C_USE_INTERRUPT bound to: 0 - type: integer
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        Parameter C_USE_EXT_BRK bound to: 1 - type: integer
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        Parameter C_USE_EXT_NM_BRK bound to: 1 - type: integer
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        Parameter C_USE_NON_SECURE bound to: 1 - type: integer
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        Parameter C_USE_MMU bound to: 0 - type: integer
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        Parameter C_MMU_DTLB_SIZE bound to: 4 - type: integer
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        Parameter C_MMU_ITLB_SIZE bound to: 2 - type: integer
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        Parameter C_MMU_TLB_ACCESS bound to: 3 - type: integer
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        Parameter C_MMU_ZONES bound to: 2 - type: integer
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        Parameter C_MMU_PRIVILEGED_INSTR bound to: 0 - type: integer
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        Parameter C_USE_BRANCH_TARGET_CACHE bound to: 0 - type: integer
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        Parameter C_BRANCH_TARGET_CACHE_SIZE bound to: 0 - type: integer
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        Parameter C_PC_WIDTH bound to: 32 - type: integer
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        Parameter C_PVR bound to: 0 - type: integer
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        Parameter C_PVR_USER1 bound to: 8'b00000000
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        Parameter C_PVR_USER2 bound to: 32'b00000000000000000000000000000000
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        Parameter C_DYNAMIC_BUS_SIZING bound to: 0 - type: integer
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        Parameter C_RESET_MSR bound to: 32'b00000000000000000000000000000000
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        Parameter C_OPCODE_0x0_ILLEGAL bound to: 0 - type: integer
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        Parameter C_DEBUG_ENABLED bound to: 0 - type: integer
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        Parameter C_DEBUG_INTERFACE bound to: 0 - type: integer
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        Parameter C_NUMBER_OF_PC_BRK bound to: 2 - type: integer
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        Parameter C_NUMBER_OF_RD_ADDR_BRK bound to: 0 - type: integer
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        Parameter C_NUMBER_OF_WR_ADDR_BRK bound to: 0 - type: integer
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        Parameter C_DEBUG_EVENT_COUNTERS bound to: 5 - type: integer
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        Parameter C_DEBUG_LATENCY_COUNTERS bound to: 1 - type: integer
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        Parameter C_DEBUG_COUNTER_WIDTH bound to: 32 - type: integer
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        Parameter C_DEBUG_TRACE_SIZE bound to: 8192 - type: integer
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        Parameter C_DEBUG_EXTERNAL_TRACE bound to: 0 - type: integer
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        Parameter C_DEBUG_TRACE_ASYNC_RESET bound to: 0 - type: integer
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        Parameter C_DEBUG_PROFILE_SIZE bound to: 0 - type: integer
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        Parameter C_INTERRUPT_IS_EDGE bound to: 0 - type: integer
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        Parameter C_EDGE_IS_POSITIVE bound to: 1 - type: integer
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        Parameter C_ASYNC_INTERRUPT bound to: 1 - type: integer
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        Parameter C_ASYNC_WAKEUP bound to: 1 - type: integer
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        Parameter C_M0_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S0_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M1_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S1_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M2_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S2_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M3_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S3_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M4_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S4_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M5_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S5_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M6_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S6_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M7_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S7_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M8_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S8_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M9_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S9_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M10_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S10_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M11_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S11_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M12_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S12_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M13_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S13_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M14_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S14_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M15_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S15_AXIS_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_ICACHE_BASEADDR bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000
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        Parameter C_ICACHE_HIGHADDR bound to: 64'b0000000000000000000000000000000000111111111111111111111111111111
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        Parameter C_USE_ICACHE bound to: 0 - type: integer
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        Parameter C_ALLOW_ICACHE_WR bound to: 1 - type: integer
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        Parameter C_ADDR_TAG_BITS bound to: 0 - type: integer
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        Parameter C_CACHE_BYTE_SIZE bound to: 8192 - type: integer
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        Parameter C_ICACHE_LINE_LEN bound to: 8 - type: integer
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        Parameter C_ICACHE_ALWAYS_USED bound to: 0 - type: integer
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        Parameter C_ICACHE_STREAMS bound to: 0 - type: integer
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        Parameter C_ICACHE_VICTIMS bound to: 0 - type: integer
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        Parameter C_ICACHE_FORCE_TAG_LUTRAM bound to: 0 - type: integer
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        Parameter C_ICACHE_DATA_WIDTH bound to: 0 - type: integer
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        Parameter C_M_AXI_IC_THREAD_ID_WIDTH bound to: 1 - type: integer
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        Parameter C_M_AXI_IC_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M_AXI_IC_ADDR_WIDTH bound to: 32 - type: integer
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        Parameter C_M_AXI_IC_USER_VALUE bound to: 31 - type: integer
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        Parameter C_M_AXI_IC_AWUSER_WIDTH bound to: 5 - type: integer
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        Parameter C_M_AXI_IC_ARUSER_WIDTH bound to: 5 - type: integer
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        Parameter C_M_AXI_IC_WUSER_WIDTH bound to: 1 - type: integer
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        Parameter C_M_AXI_IC_RUSER_WIDTH bound to: 1 - type: integer
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        Parameter C_M_AXI_IC_BUSER_WIDTH bound to: 1 - type: integer
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        Parameter C_DCACHE_BASEADDR bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000
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        Parameter C_DCACHE_HIGHADDR bound to: 64'b0000000000000000000000000000000000111111111111111111111111111111
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        Parameter C_USE_DCACHE bound to: 0 - type: integer
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        Parameter C_ALLOW_DCACHE_WR bound to: 1 - type: integer
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        Parameter C_DCACHE_ADDR_TAG bound to: 0 - type: integer
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        Parameter C_DCACHE_BYTE_SIZE bound to: 8192 - type: integer
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        Parameter C_DCACHE_LINE_LEN bound to: 4 - type: integer
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        Parameter C_DCACHE_ALWAYS_USED bound to: 0 - type: integer
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        Parameter C_DCACHE_USE_WRITEBACK bound to: 0 - type: integer
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        Parameter C_DCACHE_VICTIMS bound to: 0 - type: integer
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        Parameter C_DCACHE_FORCE_TAG_LUTRAM bound to: 0 - type: integer
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        Parameter C_DCACHE_DATA_WIDTH bound to: 0 - type: integer
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        Parameter C_M_AXI_DC_THREAD_ID_WIDTH bound to: 1 - type: integer
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        Parameter C_M_AXI_DC_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_M_AXI_DC_ADDR_WIDTH bound to: 32 - type: integer
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        Parameter C_M_AXI_DC_EXCLUSIVE_ACCESS bound to: 0 - type: integer
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        Parameter C_M_AXI_DC_USER_VALUE bound to: 31 - type: integer
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        Parameter C_M_AXI_DC_AWUSER_WIDTH bound to: 5 - type: integer
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        Parameter C_M_AXI_DC_ARUSER_WIDTH bound to: 5 - type: integer
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        Parameter C_M_AXI_DC_WUSER_WIDTH bound to: 1 - type: integer
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        Parameter C_M_AXI_DC_RUSER_WIDTH bound to: 1 - type: integer
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        Parameter C_M_AXI_DC_BUSER_WIDTH bound to: 1 - type: integer
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INFO: [Synth 8-3491] module 'MicroBlaze' declared at '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/hdl/microblaze_v10_0_vh_rfs.vhd:157134' bound to instance 'U0' of component 'MicroBlaze' [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/synth/microblaze_0.vhd:786]
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INFO: [Synth 8-256] done synthesizing module 'microblaze_0' (49#1) [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/synth/microblaze_0.vhd:107]
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WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_BID[0]
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WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_BRESP[0]
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WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_RID[0]
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WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_RRESP[0]
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WARNING: [Synth 8-3331] design DAXI_interface has unconnected port M_AXI_DP_RLAST
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WARNING: [Synth 8-3331] design DAXI_interface has unconnected port MEM_DataBus_Exclusive
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WARNING: [Synth 8-3331] design DAXI_interface has unconnected port MEM_UMode
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WARNING: [Synth 8-3331] design MMU has unconnected port Clk
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WARNING: [Synth 8-3331] design MMU has unconnected port Reset
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WARNING: [Synth 8-3331] design MMU has unconnected port IB_VMode
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WARNING: [Synth 8-3331] design MMU has unconnected port IB_UMode
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_VMode
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_UMode
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_DataBus_Write
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Write_DCache_Instr
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Unmask_EA
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WARNING: [Synth 8-3331] design MMU has unconnected port ICACHE_Valid_Addr
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WARNING: [Synth 8-3331] design MMU has unconnected port OF_PipeRun
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_PID
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_ZPR
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_TLBX
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_TLBLO
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_TLBHI
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_TLBSX
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_MTS_EA
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[0]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[1]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[2]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[3]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[4]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[5]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[6]
220 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[7]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[8]
222 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[9]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[10]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[11]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[12]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[13]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[14]
228 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[15]
229 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[16]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[17]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[18]
232 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[19]
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WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[20]
234 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[21]
235 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[22]
236 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[23]
237 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[24]
238 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[25]
239 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[26]
240 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[27]
241 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[28]
242 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[29]
243 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[30]
244 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Op1[31]
245 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_PipeRun
246 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Sel_SPR_TLBLO
247 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Sel_SPR_TLBHI
248 
WARNING: [Synth 8-3331] design MMU has unconnected port EX_Sel_SPR_EA
249 
WARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_PID
250 
WARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_ZPR
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WARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_TLBX
252 
WARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_TLBLO
253 
WARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_TLBHI
254 
WARNING: [Synth 8-3331] design MMU has unconnected port MEM_Sel_SPR_EA
255 
WARNING: [Synth 8-3331] design MMU has unconnected port MEM_PipeRun
256 
WARNING: [Synth 8-3331] design MMU has unconnected port MEM_potential_exception
257 
WARNING: [Synth 8-3331] design MMU has unconnected port WB_exception
258 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_Req_TLB_Done
259 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Invalidate
260 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[0]
261 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[1]
262 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[2]
263 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[3]
264 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[4]
265 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[5]
266 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[6]
267 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[7]
268 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[8]
269 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[9]
270 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[10]
271 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[11]
272 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[12]
273 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[13]
274 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[14]
275 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[15]
276 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[16]
277 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[17]
278 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[18]
279 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[19]
280 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[20]
281 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[21]
282 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[22]
283 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[23]
284 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[24]
285 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[25]
286 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[26]
287 
WARNING: [Synth 8-3331] design MMU has unconnected port Snoop_TLB_Addr[27]
288 
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
289 
---------------------------------------------------------------------------------
290 
Finished RTL Elaboration : Time (s): cpu = 00:00:19 ; elapsed = 00:00:36 . Memory (MB): peak = 1693.844 ; gain = 381.273 ; free physical = 578 ; free virtual = 93255
291 
---------------------------------------------------------------------------------
292 
 
293 
Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
295 
|      |Item              |Errors |Warnings |Status |Description       |
296 
+------+------------------+-------+---------+-------+------------------+
297 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
298 
+------+------------------+-------+---------+-------+------------------+
299 
---------------------------------------------------------------------------------
300 
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:37 . Memory (MB): peak = 1693.844 ; gain = 381.273 ; free physical = 586 ; free virtual = 93262
301 
---------------------------------------------------------------------------------
302 
INFO: [Netlist 29-17] Analyzing 589 Unisim elements for replacement
303 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
304 
INFO: [Device 21-403] Loading part xc7k325tffg900-2
305 
INFO: [Project 1-570] Preparing netlist for logic optimization
306 
 
307 
Processing XDC Constraints
308 
Initializing timing engine
309 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0_ooc_debug.xdc] for cell 'U0'
310 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0_ooc_debug.xdc] for cell 'U0'
311 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0_ooc.xdc] for cell 'U0'
312 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0_ooc.xdc] for cell 'U0'
313 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0.xdc] for cell 'U0'
314 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0.xdc] for cell 'U0'
315 
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/microblaze_0/microblaze_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/microblaze_0_propImpl.xdc].
316 
Resolution: To avoid this warning, move constraints listed in [.Xil/microblaze_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
317 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/microblaze_0_synth_1/dont_touch.xdc]
318 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/microblaze_0_synth_1/dont_touch.xdc]
319 
Completed Processing XDC Constraints
320 
 
321 
INFO: [Project 1-111] Unisim Transformation Summary:
322 
  A total of 384 instances were transformed.
323 
  FDE => FDRE: 32 instances
324 
  FDR => FDRE: 126 instances
325 
  FDS => FDSE: 1 instances
326 
  LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances
327 
  MULT_AND => LUT2: 1 instances
328 
  MUXCY_L => MUXCY: 128 instances
329 
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 16 instances
330 
 
331 
Constraint Validation Runtime : Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2004.602 ; gain = 1.000 ; free physical = 301 ; free virtual = 92977
332 
---------------------------------------------------------------------------------
333 
Finished Constraint Validation : Time (s): cpu = 00:00:51 ; elapsed = 00:01:31 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 451 ; free virtual = 93127
334 
---------------------------------------------------------------------------------
335 
---------------------------------------------------------------------------------
336 
Start Loading Part and Timing Information
337 
---------------------------------------------------------------------------------
338 
Loading part: xc7k325tffg900-2
339 
---------------------------------------------------------------------------------
340 
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:51 ; elapsed = 00:01:31 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 451 ; free virtual = 93127
341 
---------------------------------------------------------------------------------
342 
---------------------------------------------------------------------------------
343 
Start Applying 'set_property' XDC Constraints
344 
---------------------------------------------------------------------------------
345 
Applied set_property DONT_TOUCH = true for U0. (constraint file  /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/microblaze_0_synth_1/dont_touch.xdc, line 9).
346 
---------------------------------------------------------------------------------
347 
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:51 ; elapsed = 00:01:31 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 453 ; free virtual = 93129
348 
---------------------------------------------------------------------------------
349 
INFO: [Synth 8-5546] ROM "ext_nm_brk_hold_clr" won't be mapped to RAM because it is too sparse
350 
INFO: [Synth 8-5544] ROM "EX_Pattern_Cmp_Sel" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
351 
INFO: [Synth 8-5546] ROM "ex_gpr_write" won't be mapped to RAM because it is too sparse
352 
INFO: [Synth 8-5544] ROM "ex_move_to_MSR_instr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
353 
INFO: [Synth 8-5544] ROM "ex_move_to_FSR_instr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
354 
INFO: [Synth 8-5546] ROM "ext_nm_brk_hold_clr" won't be mapped to RAM because it is too sparse
355 
INFO: [Synth 8-5544] ROM "EX_Pattern_Cmp_Sel" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
356 
INFO: [Synth 8-5546] ROM "ex_gpr_write" won't be mapped to RAM because it is too sparse
357 
INFO: [Synth 8-5544] ROM "ex_move_to_MSR_instr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
358 
INFO: [Synth 8-5544] ROM "ex_move_to_FSR_instr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
359 
INFO: [Synth 8-5544] ROM "of_Sel_SPR_MSR" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
360 
INFO: [Synth 8-5544] ROM "dbg_stop_instr_fetch" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
361 
---------------------------------------------------------------------------------
362 
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:54 ; elapsed = 00:01:35 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 535 ; free virtual = 93211
363 
---------------------------------------------------------------------------------
364 
 
365 
Report RTL Partitions:
366 
+-+--------------+------------+----------+
367 
| |RTL Partition |Replication |Instances |
368 
+-+--------------+------------+----------+
369 
+-+--------------+------------+----------+
370 
---------------------------------------------------------------------------------
371 
Start RTL Component Statistics
372 
---------------------------------------------------------------------------------
373 
Detailed RTL Component Info :
374 
+---XORs :
375 
           2 Input      2 Bit         XORs := 1
376 
           2 Input      1 Bit         XORs := 2
377 
           3 Input      1 Bit         XORs := 1
378 
+---Registers :
379 
                     4096 Bit    Registers := 1
380 
                       32 Bit    Registers := 27
381 
                       16 Bit    Registers := 1
382 
                       15 Bit    Registers := 1
383 
                       13 Bit    Registers := 2
384 
                        6 Bit    Registers := 1
385 
                        5 Bit    Registers := 4
386 
                        4 Bit    Registers := 6
387 
                        3 Bit    Registers := 3
388 
                        2 Bit    Registers := 8
389 
                        1 Bit    Registers := 171
390 
+---Muxes :
391 
           2 Input     32 Bit        Muxes := 12
392 
           4 Input     32 Bit        Muxes := 3
393 
           2 Input     16 Bit        Muxes := 1
394 
           2 Input     15 Bit        Muxes := 9
395 
           2 Input     13 Bit        Muxes := 1
396 
           2 Input      8 Bit        Muxes := 9
397 
           2 Input      5 Bit        Muxes := 3
398 
           6 Input      5 Bit        Muxes := 1
399 
           7 Input      4 Bit        Muxes := 1
400 
           2 Input      3 Bit        Muxes := 1
401 
           2 Input      2 Bit        Muxes := 10
402 
           3 Input      2 Bit        Muxes := 1
403 
           8 Input      1 Bit        Muxes := 1
404 
           7 Input      1 Bit        Muxes := 6
405 
           2 Input      1 Bit        Muxes := 81
406 
           4 Input      1 Bit        Muxes := 1
407 
           3 Input      1 Bit        Muxes := 4
408 
---------------------------------------------------------------------------------
409 
Finished RTL Component Statistics
410 
---------------------------------------------------------------------------------
411 
---------------------------------------------------------------------------------
412 
Start RTL Hierarchical Component Statistics
413 
---------------------------------------------------------------------------------
414 
Hierarchical RTL Component report
415 
Module mb_sync_bit
416 
Detailed RTL Component Info :
417 
+---Registers :
418 
                        2 Bit    Registers := 1
419 
Module PC_Module_gti
420 
Detailed RTL Component Info :
421 
+---Registers :
422 
                       32 Bit    Registers := 3
423 
+---Muxes :
424 
           2 Input     32 Bit        Muxes := 1
425 
Module PreFetch_Buffer_gti
426 
Detailed RTL Component Info :
427 
+---Registers :
428 
                        1 Bit    Registers := 1
429 
+---Muxes :
430 
           2 Input      2 Bit        Muxes := 1
431 
Module jump_logic
432 
Detailed RTL Component Info :
433 
+---Registers :
434 
                        1 Bit    Registers := 9
435 
+---Muxes :
436 
           8 Input      1 Bit        Muxes := 1
437 
           7 Input      1 Bit        Muxes := 5
438 
           2 Input      1 Bit        Muxes := 2
439 
Module Decode_gti
440 
Detailed RTL Component Info :
441 
+---Registers :
442 
                       32 Bit    Registers := 4
443 
                        6 Bit    Registers := 1
444 
                        5 Bit    Registers := 4
445 
                        4 Bit    Registers := 2
446 
                        3 Bit    Registers := 3
447 
                        2 Bit    Registers := 4
448 
                        1 Bit    Registers := 142
449 
+---Muxes :
450 
           2 Input      5 Bit        Muxes := 2
451 
           6 Input      5 Bit        Muxes := 1
452 
           2 Input      2 Bit        Muxes := 5
453 
           3 Input      2 Bit        Muxes := 1
454 
           2 Input      1 Bit        Muxes := 54
455 
           4 Input      1 Bit        Muxes := 1
456 
           3 Input      1 Bit        Muxes := 4
457 
           7 Input      1 Bit        Muxes := 1
458 
Module Operand_Select_gti
459 
Detailed RTL Component Info :
460 
+---Registers :
461 
                       32 Bit    Registers := 4
462 
                       16 Bit    Registers := 1
463 
+---Muxes :
464 
           2 Input     32 Bit        Muxes := 6
465 
           4 Input     32 Bit        Muxes := 3
466 
Module ALU_Bit__parameterized2
467 
Detailed RTL Component Info :
468 
+---XORs :
469 
           2 Input      1 Bit         XORs := 1
470 
Module Shift_Logic_Module_gti
471 
Detailed RTL Component Info :
472 
+---Muxes :
473 
           2 Input     32 Bit        Muxes := 1
474 
           2 Input      8 Bit        Muxes := 4
475 
           2 Input      1 Bit        Muxes := 5
476 
Module mul_unit
477 
Detailed RTL Component Info :
478 
+---Registers :
479 
                       32 Bit    Registers := 1
480 
Module Byte_Doublet_Handle_gti
481 
Detailed RTL Component Info :
482 
+---XORs :
483 
           2 Input      2 Bit         XORs := 1
484 
           2 Input      1 Bit         XORs := 1
485 
           3 Input      1 Bit         XORs := 1
486 
+---Registers :
487 
                       32 Bit    Registers := 1
488 
                        4 Bit    Registers := 1
489 
                        2 Bit    Registers := 2
490 
+---Muxes :
491 
           2 Input     32 Bit        Muxes := 2
492 
           2 Input     16 Bit        Muxes := 1
493 
           2 Input      8 Bit        Muxes := 5
494 
           7 Input      4 Bit        Muxes := 1
495 
           2 Input      2 Bit        Muxes := 3
496 
Module Data_Flow_Logic
497 
Detailed RTL Component Info :
498 
+---Registers :
499 
                       32 Bit    Registers := 1
500 
                        4 Bit    Registers := 2
501 
                        1 Bit    Registers := 2
502 
Module msr_reg_gti
503 
Detailed RTL Component Info :
504 
+---Registers :
505 
                       15 Bit    Registers := 1
506 
+---Muxes :
507 
           2 Input     15 Bit        Muxes := 9
508 
           2 Input      2 Bit        Muxes := 1
509 
           2 Input      1 Bit        Muxes := 8
510 
Module exception_registers_gti
511 
Detailed RTL Component Info :
512 
+---Registers :
513 
                       32 Bit    Registers := 8
514 
                       13 Bit    Registers := 2
515 
+---Muxes :
516 
           2 Input     13 Bit        Muxes := 1
517 
           2 Input      5 Bit        Muxes := 1
518 
           2 Input      3 Bit        Muxes := 1
519 
           2 Input      1 Bit        Muxes := 1
520 
Module Data_Flow_gti
521 
Detailed RTL Component Info :
522 
+---Muxes :
523 
           2 Input     32 Bit        Muxes := 2
524 
Module DAXI_interface
525 
Detailed RTL Component Info :
526 
+---Registers :
527 
                       32 Bit    Registers := 1
528 
                        1 Bit    Registers := 10
529 
+---Muxes :
530 
           2 Input      1 Bit        Muxes := 7
531 
Module MicroBlaze_GTi
532 
Detailed RTL Component Info :
533 
+---Registers :
534 
                       32 Bit    Registers := 4
535 
                        4 Bit    Registers := 1
536 
                        1 Bit    Registers := 4
537 
Module MicroBlaze_Core
538 
Detailed RTL Component Info :
539 
+---Registers :
540 
                        1 Bit    Registers := 3
541 
+---Muxes :
542 
           2 Input      1 Bit        Muxes := 4
543 
Module MicroBlaze
544 
Detailed RTL Component Info :
545 
+---Registers :
546 
                     4096 Bit    Registers := 1
547 
---------------------------------------------------------------------------------
548 
Finished RTL Hierarchical Component Statistics
549 
---------------------------------------------------------------------------------
550 
---------------------------------------------------------------------------------
551 
Start Part Resource Summary
552 
---------------------------------------------------------------------------------
553 
Part Resources:
554 
DSPs: 840 (col length:140)
555 
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
556 
---------------------------------------------------------------------------------
557 
Finished Part Resource Summary
558 
---------------------------------------------------------------------------------
559 
---------------------------------------------------------------------------------
560 
Start Cross Boundary and Area Optimization
561 
---------------------------------------------------------------------------------
562 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/of_set_MSR_IE_hold_reg )
563 
INFO: [Synth 8-3886] merging instance 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_which_branch_reg[9]' (FDRE) to 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[3]'
564 
INFO: [Synth 8-3886] merging instance 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_bs_instr_reg' (FDRE) to 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_bt_hit_hold_reg'
565 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_bt_hit_hold_reg )
566 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_fpu_instr_reg )
567 
INFO: [Synth 8-3886] merging instance 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_which_branch_reg[8]' (FDRE) to 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[2]'
568 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/Using_FPGA.Gen_Bits[27].MEM_EX_Result_Inst/Using_FPGA.Native )
569 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Use_DBUS.DAXI_Interface_I1/mem_access_failed_reg )
570 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_MSR_set_decode_reg )
571 
INFO: [Synth 8-3886] merging instance 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_which_branch_reg[10]' (FDRE) to 'U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[4]'
572 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_Sel_SPR_EA_I_reg )
573 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/ex_Instr_Excep_combo_reg )
574 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4095] )
575 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4094] )
576 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4093] )
577 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4092] )
578 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4091] )
579 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4090] )
580 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4089] )
581 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4088] )
582 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4087] )
583 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4086] )
584 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4085] )
585 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4084] )
586 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4083] )
587 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4082] )
588 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4081] )
589 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4080] )
590 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4079] )
591 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4078] )
592 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4077] )
593 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4076] )
594 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4075] )
595 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4074] )
596 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4073] )
597 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4072] )
598 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4071] )
599 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4070] )
600 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4069] )
601 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4068] )
602 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4067] )
603 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4066] )
604 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4065] )
605 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4064] )
606 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4063] )
607 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4062] )
608 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4061] )
609 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4060] )
610 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4059] )
611 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4058] )
612 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4057] )
613 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4056] )
614 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4055] )
615 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4054] )
616 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4053] )
617 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4052] )
618 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4051] )
619 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4050] )
620 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4049] )
621 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4048] )
622 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4047] )
623 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4046] )
624 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4045] )
625 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4044] )
626 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4043] )
627 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4042] )
628 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4041] )
629 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4040] )
630 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4039] )
631 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4038] )
632 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4037] )
633 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4036] )
634 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4035] )
635 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4034] )
636 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4033] )
637 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4032] )
638 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4031] )
639 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4030] )
640 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4029] )
641 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4028] )
642 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4027] )
643 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4026] )
644 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4025] )
645 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4024] )
646 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4023] )
647 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4022] )
648 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4021] )
649 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4020] )
650 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4019] )
651 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4018] )
652 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4017] )
653 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4016] )
654 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4015] )
655 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4014] )
656 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4013] )
657 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4012] )
658 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4011] )
659 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4010] )
660 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4009] )
661 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4008] )
662 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4007] )
663 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4006] )
664 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4005] )
665 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\LOCKSTEP_Out_reg[4004] )
666 
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
667 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[715]' (FDR) to 'U0/LOCKSTEP_Out_reg[549]'
668 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[663]' (FDR) to 'U0/LOCKSTEP_Out_reg[497]'
669 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[662]' (FDR) to 'U0/LOCKSTEP_Out_reg[496]'
670 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[661]' (FDR) to 'U0/LOCKSTEP_Out_reg[495]'
671 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[660]' (FDR) to 'U0/LOCKSTEP_Out_reg[494]'
672 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[659]' (FDR) to 'U0/LOCKSTEP_Out_reg[493]'
673 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[658]' (FDR) to 'U0/LOCKSTEP_Out_reg[492]'
674 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[657]' (FDR) to 'U0/LOCKSTEP_Out_reg[491]'
675 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[656]' (FDR) to 'U0/LOCKSTEP_Out_reg[490]'
676 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[655]' (FDR) to 'U0/LOCKSTEP_Out_reg[489]'
677 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[654]' (FDR) to 'U0/LOCKSTEP_Out_reg[488]'
678 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[653]' (FDR) to 'U0/LOCKSTEP_Out_reg[487]'
679 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[652]' (FDR) to 'U0/LOCKSTEP_Out_reg[486]'
680 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[651]' (FDR) to 'U0/LOCKSTEP_Out_reg[485]'
681 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[650]' (FDR) to 'U0/LOCKSTEP_Out_reg[484]'
682 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[649]' (FDR) to 'U0/LOCKSTEP_Out_reg[483]'
683 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[648]' (FDR) to 'U0/LOCKSTEP_Out_reg[482]'
684 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[647]' (FDR) to 'U0/LOCKSTEP_Out_reg[481]'
685 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[646]' (FDR) to 'U0/LOCKSTEP_Out_reg[480]'
686 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[645]' (FDR) to 'U0/LOCKSTEP_Out_reg[479]'
687 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[644]' (FDR) to 'U0/LOCKSTEP_Out_reg[478]'
688 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[643]' (FDR) to 'U0/LOCKSTEP_Out_reg[477]'
689 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[642]' (FDR) to 'U0/LOCKSTEP_Out_reg[476]'
690 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[641]' (FDR) to 'U0/LOCKSTEP_Out_reg[475]'
691 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[640]' (FDR) to 'U0/LOCKSTEP_Out_reg[474]'
692 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[639]' (FDR) to 'U0/LOCKSTEP_Out_reg[473]'
693 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[638]' (FDR) to 'U0/LOCKSTEP_Out_reg[472]'
694 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[637]' (FDR) to 'U0/LOCKSTEP_Out_reg[471]'
695 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[636]' (FDR) to 'U0/LOCKSTEP_Out_reg[470]'
696 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[635]' (FDR) to 'U0/LOCKSTEP_Out_reg[469]'
697 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[634]' (FDR) to 'U0/LOCKSTEP_Out_reg[468]'
698 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[633]' (FDR) to 'U0/LOCKSTEP_Out_reg[467]'
699 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[632]' (FDR) to 'U0/LOCKSTEP_Out_reg[466]'
700 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/Using_FPGA_2.ex_reverse_mem_access_inst/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
701 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/Using_FPGA.Gen_Bits[27].MEM_EX_Result_Inst/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
702 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/wb_exception_kind_i_reg[27]) is unused and will be removed from module MicroBlaze.
703 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_MSR_set_decode_reg) is unused and will be removed from module MicroBlaze.
704 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_Sel_SPR_EA_I_reg) is unused and will be removed from module MicroBlaze.
705 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Op_reg[0]) is unused and will be removed from module MicroBlaze.
706 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Op_reg[1]) is unused and will be removed from module MicroBlaze.
707 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Sign_Extend_Sel_reg) is unused and will be removed from module MicroBlaze.
708 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Pattern_Cmp_Sel_reg) is unused and will be removed from module MicroBlaze.
709 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_SWAP_BYTE_Instr_reg) is unused and will be removed from module MicroBlaze.
710 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Sel_reg) is unused and will be removed from module MicroBlaze.
711 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/of_set_MSR_IE_hold_reg) is unused and will be removed from module MicroBlaze.
712 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_set_MSR_IE_instr_reg) is unused and will be removed from module MicroBlaze.
713 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/of_set_MSR_EE_hold_reg) is unused and will be removed from module MicroBlaze.
714 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_set_MSR_EE_instr_reg) is unused and will be removed from module MicroBlaze.
715 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_move_to_FSR_instr_reg) is unused and will be removed from module MicroBlaze.
716 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_start_div_i_reg) is unused and will be removed from module MicroBlaze.
717 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_fpu_instr_reg) is unused and will be removed from module MicroBlaze.
718 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Left_Shift_reg) is unused and will be removed from module MicroBlaze.
719 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Arith_Shift_reg) is unused and will be removed from module MicroBlaze.
720 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Bit_Insert_reg) is unused and will be removed from module MicroBlaze.
721 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Bit_Extract_reg) is unused and will be removed from module MicroBlaze.
722 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg) is unused and will be removed from module MicroBlaze.
723 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Op_reg[22]) is unused and will be removed from module MicroBlaze.
724 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Op_reg[23]) is unused and will be removed from module MicroBlaze.
725 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Op_reg[24]) is unused and will be removed from module MicroBlaze.
726 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Cond_reg[25]) is unused and will be removed from module MicroBlaze.
727 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Cond_reg[26]) is unused and will be removed from module MicroBlaze.
728 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_FPU_Cond_reg[27]) is unused and will be removed from module MicroBlaze.
729 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_start_fpu_i_reg) is unused and will be removed from module MicroBlaze.
730 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Not_FPU_Instr_reg) is unused and will be removed from module MicroBlaze.
731 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_FSR_I_reg) is unused and will be removed from module MicroBlaze.
732 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_potential_exception_i_reg) is unused and will be removed from module MicroBlaze.
733 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_SLR_I_reg) is unused and will be removed from module MicroBlaze.
734 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_SHR_I_reg) is unused and will be removed from module MicroBlaze.
735 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/wb_is_fpu_instr_reg) is unused and will be removed from module MicroBlaze.
736 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_PVR_I_reg) is unused and will be removed from module MicroBlaze.
737 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Sel_SPR_PVR_reg) is unused and will be removed from module MicroBlaze.
738 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_load_instr_reg) is unused and will be removed from module MicroBlaze.
739 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Sel_DataBus_Read_Data_i_reg) is unused and will be removed from module MicroBlaze.
740 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Sel_MEM_Res_i_reg) is unused and will be removed from module MicroBlaze.
741 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_mul_instr_reg) is unused and will be removed from module MicroBlaze.
742 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/wb_is_mul_instr_reg) is unused and will be removed from module MicroBlaze.
743 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_PVR_Select_reg[0]) is unused and will be removed from module MicroBlaze.
744 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_PVR_Select_reg[1]) is unused and will be removed from module MicroBlaze.
745 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_PVR_Select_reg[2]) is unused and will be removed from module MicroBlaze.
746 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_PVR_Select_reg[3]) is unused and will be removed from module MicroBlaze.
747 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_PVR_Select_reg[0]) is unused and will be removed from module MicroBlaze.
748 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_PVR_Select_reg[1]) is unused and will be removed from module MicroBlaze.
749 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_PVR_Select_reg[2]) is unused and will be removed from module MicroBlaze.
750 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_PVR_Select_reg[3]) is unused and will be removed from module MicroBlaze.
751 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_EA_I_reg) is unused and will be removed from module MicroBlaze.
752 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_write_icache_done_i_reg) is unused and will be removed from module MicroBlaze.
753 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_dbg_reg) is unused and will be removed from module MicroBlaze.
754 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_dbg_reg) is unused and will be removed from module MicroBlaze.
755 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_dbg_reg) is unused and will be removed from module MicroBlaze.
756 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_read_imm_reg_reg) is unused and will be removed from module MicroBlaze.
757 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_read_imm_reg_reg) is unused and will be removed from module MicroBlaze.
758 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Read_Imm_Reg_reg) is unused and will be removed from module MicroBlaze.
759 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_read_imm_reg_1_reg) is unused and will be removed from module MicroBlaze.
760 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_read_imm_reg_1_reg) is unused and will be removed from module MicroBlaze.
761 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Read_Imm_Reg_1_reg) is unused and will be removed from module MicroBlaze.
762 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_PC_Valid_reg) is unused and will be removed from module MicroBlaze.
763 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/Dbg_Clean_Stop_reg) is unused and will be removed from module MicroBlaze.
764 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_BTR_I_reg) is unused and will be removed from module MicroBlaze.
765 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_ESR_I_reg) is unused and will be removed from module MicroBlaze.
766 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_EAR_I_reg) is unused and will be removed from module MicroBlaze.
767 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_Sel_SPR_EDR_I_reg) is unused and will be removed from module MicroBlaze.
768 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_store_instr_reg) is unused and will be removed from module MicroBlaze.
769 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_SW_Instr_reg) is unused and will be removed from module MicroBlaze.
770 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_word_access_reg) is unused and will be removed from module MicroBlaze.
771 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Word_Access_reg) is unused and will be removed from module MicroBlaze.
772 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/mem_jump_hit_reg) is unused and will be removed from module MicroBlaze.
773 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/Trace_WB_Jump_Hit_reg) is unused and will be removed from module MicroBlaze.
774 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_Instr_Excep_combo_reg) is unused and will be removed from module MicroBlaze.
775 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Sel_EX_reg) is unused and will be removed from module MicroBlaze.
776 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Decode_I/ex_bt_hit_hold_reg) is unused and will be removed from module MicroBlaze.
777 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[17].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
778 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[18].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
779 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[19].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
780 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[20].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
781 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[21].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
782 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[22].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
783 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[23].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
784 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[24].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
785 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[25].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
786 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[26].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
787 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[27].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
788 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/MEM_MSR_Bits[31].Using_FDR.MSR_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
789 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[17].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
790 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[17].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
791 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[18].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
792 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[18].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
793 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[19].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
794 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[19].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
795 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[20].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
796 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[20].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
797 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[21].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
798 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[21].Using_FDR.MSR_of_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
799 
INFO: [Synth 8-3332] Sequential element (MicroBlaze_Core_I/Performance.Core/Data_Flow_I/msr_reg_i/OF_EX_MSR_Bits[22].Using_FDR.MSR_ex_I/Using_FPGA.Native) is unused and will be removed from module MicroBlaze.
800 
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
801 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[722]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
802 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[717]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
803 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[713]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
804 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[712]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
805 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[708]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
806 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[705]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
807 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[630]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
808 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[628]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
809 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[551]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
810 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[547]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
811 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[546]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
812 
INFO: [Synth 8-3886] merging instance 'U0/LOCKSTEP_Out_reg[542]' (FDR) to 'U0/LOCKSTEP_Out_reg[539]'
813 
---------------------------------------------------------------------------------
814 
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:02 ; elapsed = 00:01:44 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 518 ; free virtual = 93194
815 
---------------------------------------------------------------------------------
816 
 
817 
Report RTL Partitions:
818 
+-+--------------+------------+----------+
819 
| |RTL Partition |Replication |Instances |
820 
+-+--------------+------------+----------+
821 
+-+--------------+------------+----------+
822 
---------------------------------------------------------------------------------
823 
Start Applying XDC Timing Constraints
824 
---------------------------------------------------------------------------------
825 
---------------------------------------------------------------------------------
826 
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:12 ; elapsed = 00:01:58 . Memory (MB): peak = 2004.602 ; gain = 692.031 ; free physical = 370 ; free virtual = 93047
827 
---------------------------------------------------------------------------------
828 
---------------------------------------------------------------------------------
829 
Start Timing Optimization
830 
---------------------------------------------------------------------------------
831 
---------------------------------------------------------------------------------
832 
Finished Timing Optimization : Time (s): cpu = 00:01:52 ; elapsed = 00:02:42 . Memory (MB): peak = 2152.676 ; gain = 840.105 ; free physical = 903 ; free virtual = 92876
833 
---------------------------------------------------------------------------------
834 
 
835 
Report RTL Partitions:
836 
+-+--------------+------------+----------+
837 
| |RTL Partition |Replication |Instances |
838 
+-+--------------+------------+----------+
839 
+-+--------------+------------+----------+
840 
---------------------------------------------------------------------------------
841 
Start Technology Mapping
842 
---------------------------------------------------------------------------------
843 
---------------------------------------------------------------------------------
844 
Finished Technology Mapping : Time (s): cpu = 00:01:54 ; elapsed = 00:02:43 . Memory (MB): peak = 2152.676 ; gain = 840.105 ; free physical = 901 ; free virtual = 92875
845 
---------------------------------------------------------------------------------
846 
 
847 
Report RTL Partitions:
848 
+-+--------------+------------+----------+
849 
| |RTL Partition |Replication |Instances |
850 
+-+--------------+------------+----------+
851 
+-+--------------+------------+----------+
852 
---------------------------------------------------------------------------------
853 
Start IO Insertion
854 
---------------------------------------------------------------------------------
855 
---------------------------------------------------------------------------------
856 
Start Flattening Before IO Insertion
857 
---------------------------------------------------------------------------------
858 
---------------------------------------------------------------------------------
859 
Finished Flattening Before IO Insertion
860 
---------------------------------------------------------------------------------
861 
---------------------------------------------------------------------------------
862 
Start Final Netlist Cleanup
863 
---------------------------------------------------------------------------------
864 
---------------------------------------------------------------------------------
865 
Finished Final Netlist Cleanup
866 
---------------------------------------------------------------------------------
867 
---------------------------------------------------------------------------------
868 
Finished IO Insertion : Time (s): cpu = 00:01:54 ; elapsed = 00:02:44 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 902 ; free virtual = 92875
869 
---------------------------------------------------------------------------------
870 
 
871 
Report Check Netlist:
872 
+------+------------------+-------+---------+-------+------------------+
873 
|      |Item              |Errors |Warnings |Status |Description       |
874 
+------+------------------+-------+---------+-------+------------------+
875 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
876 
+------+------------------+-------+---------+-------+------------------+
877 
---------------------------------------------------------------------------------
878 
Start Renaming Generated Instances
879 
---------------------------------------------------------------------------------
880 
---------------------------------------------------------------------------------
881 
Finished Renaming Generated Instances : Time (s): cpu = 00:01:54 ; elapsed = 00:02:44 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 902 ; free virtual = 92875
882 
---------------------------------------------------------------------------------
883 
 
884 
Report RTL Partitions:
885 
+-+--------------+------------+----------+
886 
| |RTL Partition |Replication |Instances |
887 
+-+--------------+------------+----------+
888 
+-+--------------+------------+----------+
889 
---------------------------------------------------------------------------------
890 
Start Rebuilding User Hierarchy
891 
---------------------------------------------------------------------------------
892 
---------------------------------------------------------------------------------
893 
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:55 ; elapsed = 00:02:44 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873
894 
---------------------------------------------------------------------------------
895 
---------------------------------------------------------------------------------
896 
Start Renaming Generated Ports
897 
---------------------------------------------------------------------------------
898 
---------------------------------------------------------------------------------
899 
Finished Renaming Generated Ports : Time (s): cpu = 00:01:55 ; elapsed = 00:02:44 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873
900 
---------------------------------------------------------------------------------
901 
---------------------------------------------------------------------------------
902 
Start Handling Custom Attributes
903 
---------------------------------------------------------------------------------
904 
---------------------------------------------------------------------------------
905 
Finished Handling Custom Attributes : Time (s): cpu = 00:01:55 ; elapsed = 00:02:45 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873
906 
---------------------------------------------------------------------------------
907 
---------------------------------------------------------------------------------
908 
Start Renaming Generated Nets
909 
---------------------------------------------------------------------------------
910 
---------------------------------------------------------------------------------
911 
Finished Renaming Generated Nets : Time (s): cpu = 00:01:55 ; elapsed = 00:02:45 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873
912 
---------------------------------------------------------------------------------
913 
---------------------------------------------------------------------------------
914 
Start ROM, RAM, DSP and Shift Register Reporting
915 
---------------------------------------------------------------------------------
916 
 
917 
Dynamic Shift Register Report:
918 
+------------+------------------+--------+------------+--------+---------+--------+--------+--------+
919 
|Module Name | RTL Name         | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
920 
+------------+------------------+--------+------------+--------+---------+--------+--------+--------+
921 
|dsrl        | PC_Buffer_reg[3] | 4      | 32         | 32     | 0       | 0      | 0      | 0      |
922 
|dsrl__1     | ibuffer_reg[3]   | 4      | 43         | 43     | 0       | 0      | 0      | 0      |
923 
+------------+------------------+--------+------------+--------+---------+--------+--------+--------+
924 
 
925 
---------------------------------------------------------------------------------
926 
Finished ROM, RAM, DSP and Shift Register Reporting
927 
---------------------------------------------------------------------------------
928 
---------------------------------------------------------------------------------
929 
Start Writing Synthesis Report
930 
---------------------------------------------------------------------------------
931 
 
932 
Report BlackBoxes:
933 
+-+--------------+----------+
934 
| |BlackBox name |Instances |
935 
+-+--------------+----------+
936 
+-+--------------+----------+
937 
 
938 
Report Cell Usage:
939 
+------+----------+------+
940 
|      |Cell      |Count |
941 
+------+----------+------+
942 
|1     |AND2B1L   |     1|
943 
|2     |DSP48E1   |     1|
944 
|3     |DSP48E1_1 |     1|
945 
|4     |DSP48E1_2 |     1|
946 
|5     |LUT1      |    16|
947 
|6     |LUT2      |    75|
948 
|7     |LUT3      |   195|
949 
|8     |LUT4      |   134|
950 
|9     |LUT5      |   240|
951 
|10    |LUT6      |   254|
952 
|11    |LUT6_2    |    64|
953 
|12    |MULT_AND  |     1|
954 
|13    |MUXCY_L   |   126|
955 
|14    |MUXF7     |   108|
956 
|15    |RAM32M    |    16|
957 
|16    |SRL16E    |    75|
958 
|17    |XORCY     |    94|
959 
|18    |FDE       |    32|
960 
|19    |FDR       |    88|
961 
|20    |FDRE      |  1106|
962 
|21    |FDS       |     1|
963 
|22    |FDSE      |    36|
964 
+------+----------+------+
965 
 
966 
Report Instance Areas:
967 
+------+------------------------------------------------------------------------------+------------------------------+------+
968 
|      |Instance                                                                      |Module                        |Cells |
969 
+------+------------------------------------------------------------------------------+------------------------------+------+
970 
|1     |top                                                                           |                              |  2665|
971 
|2     |  U0                                                                          |MicroBlaze                    |  2665|
972 
|3     |    MicroBlaze_Core_I                                                         |MicroBlaze_Core               |  2300|
973 
|4     |      \Performance.Core                                                       |MicroBlaze_GTi                |  2290|
974 
|5     |        Data_Flow_I                                                           |Data_Flow_gti                 |   743|
975 
|6     |          ALU_I                                                               |ALU                           |   143|
976 
|7     |            \Use_Carry_Decoding.CarryIn_MUXCY                                 |MB_MUXCY_433                  |     1|
977 
|8     |            \Using_FPGA.ALL_Bits[0].ALU_Bit_I1                                |ALU_Bit__parameterized2       |     6|
978 
|9     |              \Last_Bit.I_ALU_LUT_2                                           |MB_LUT4                       |     1|
979 
|10    |              \Last_Bit.I_ALU_LUT_V5                                          |MB_LUT6__parameterized12      |     1|
980 
|11    |              \Last_Bit.MULT_AND_I                                            |MB_MULT_AND                   |     1|
981 
|12    |              \Last_Bit.MUXCY_XOR_I                                           |MB_MUXCY_XORCY_525            |     2|
982 
|13    |              \Last_Bit.Pre_MUXCY_I                                           |MB_MUXCY_526                  |     1|
983 
|14    |            \Using_FPGA.ALL_Bits[10].ALU_Bit_I1                               |ALU_Bit                       |     5|
984 
|15    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_523                 |     1|
985 
|16    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_524            |     4|
986 
|17    |            \Using_FPGA.ALL_Bits[11].ALU_Bit_I1                               |ALU_Bit_434                   |     5|
987 
|18    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_521                 |     1|
988 
|19    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_522            |     4|
989 
|20    |            \Using_FPGA.ALL_Bits[12].ALU_Bit_I1                               |ALU_Bit_435                   |     5|
990 
|21    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_519                 |     1|
991 
|22    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_520            |     4|
992 
|23    |            \Using_FPGA.ALL_Bits[13].ALU_Bit_I1                               |ALU_Bit_436                   |     5|
993 
|24    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_517                 |     1|
994 
|25    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_518            |     4|
995 
|26    |            \Using_FPGA.ALL_Bits[14].ALU_Bit_I1                               |ALU_Bit_437                   |     4|
996 
|27    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_515                 |     1|
997 
|28    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_516            |     3|
998 
|29    |            \Using_FPGA.ALL_Bits[15].ALU_Bit_I1                               |ALU_Bit_438                   |     5|
999 
|30    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_513                 |     1|
1000 
|31    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_514            |     4|
1001 
|32    |            \Using_FPGA.ALL_Bits[16].ALU_Bit_I1                               |ALU_Bit_439                   |     5|
1002 
|33    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_511                 |     1|
1003 
|34    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_512            |     4|
1004 
|35    |            \Using_FPGA.ALL_Bits[17].ALU_Bit_I1                               |ALU_Bit_440                   |     4|
1005 
|36    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_509                 |     1|
1006 
|37    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_510            |     3|
1007 
|38    |            \Using_FPGA.ALL_Bits[18].ALU_Bit_I1                               |ALU_Bit_441                   |     5|
1008 
|39    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_507                 |     1|
1009 
|40    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_508            |     4|
1010 
|41    |            \Using_FPGA.ALL_Bits[19].ALU_Bit_I1                               |ALU_Bit_442                   |     4|
1011 
|42    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_505                 |     1|
1012 
|43    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_506            |     3|
1013 
|44    |            \Using_FPGA.ALL_Bits[1].ALU_Bit_I1                                |ALU_Bit_443                   |     5|
1014 
|45    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_503                 |     1|
1015 
|46    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_504            |     4|
1016 
|47    |            \Using_FPGA.ALL_Bits[20].ALU_Bit_I1                               |ALU_Bit_444                   |     5|
1017 
|48    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_501                 |     1|
1018 
|49    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_502            |     4|
1019 
|50    |            \Using_FPGA.ALL_Bits[21].ALU_Bit_I1                               |ALU_Bit_445                   |     5|
1020 
|51    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_499                 |     1|
1021 
|52    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_500            |     4|
1022 
|53    |            \Using_FPGA.ALL_Bits[22].ALU_Bit_I1                               |ALU_Bit_446                   |     5|
1023 
|54    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_497                 |     1|
1024 
|55    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_498            |     4|
1025 
|56    |            \Using_FPGA.ALL_Bits[23].ALU_Bit_I1                               |ALU_Bit_447                   |     4|
1026 
|57    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_495                 |     1|
1027 
|58    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_496            |     3|
1028 
|59    |            \Using_FPGA.ALL_Bits[24].ALU_Bit_I1                               |ALU_Bit_448                   |     3|
1029 
|60    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_493                 |     1|
1030 
|61    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_494            |     2|
1031 
|62    |            \Using_FPGA.ALL_Bits[25].ALU_Bit_I1                               |ALU_Bit_449                   |     3|
1032 
|63    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_491                 |     1|
1033 
|64    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_492            |     2|
1034 
|65    |            \Using_FPGA.ALL_Bits[26].ALU_Bit_I1                               |ALU_Bit_450                   |     3|
1035 
|66    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_489                 |     1|
1036 
|67    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_490            |     2|
1037 
|68    |            \Using_FPGA.ALL_Bits[27].ALU_Bit_I1                               |ALU_Bit_451                   |     3|
1038 
|69    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_487                 |     1|
1039 
|70    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_488            |     2|
1040 
|71    |            \Using_FPGA.ALL_Bits[28].ALU_Bit_I1                               |ALU_Bit_452                   |     3|
1041 
|72    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_485                 |     1|
1042 
|73    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_486            |     2|
1043 
|74    |            \Using_FPGA.ALL_Bits[29].ALU_Bit_I1                               |ALU_Bit_453                   |     3|
1044 
|75    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_483                 |     1|
1045 
|76    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_484            |     2|
1046 
|77    |            \Using_FPGA.ALL_Bits[2].ALU_Bit_I1                                |ALU_Bit_454                   |     5|
1047 
|78    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_481                 |     1|
1048 
|79    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_482            |     4|
1049 
|80    |            \Using_FPGA.ALL_Bits[30].ALU_Bit_I1                               |ALU_Bit_455                   |     3|
1050 
|81    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_479                 |     1|
1051 
|82    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_480            |     2|
1052 
|83    |            \Using_FPGA.ALL_Bits[31].ALU_Bit_I1                               |ALU_Bit_456                   |     3|
1053 
|84    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_477                 |     1|
1054 
|85    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_478            |     2|
1055 
|86    |            \Using_FPGA.ALL_Bits[3].ALU_Bit_I1                                |ALU_Bit_457                   |     5|
1056 
|87    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_475                 |     1|
1057 
|88    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_476            |     4|
1058 
|89    |            \Using_FPGA.ALL_Bits[4].ALU_Bit_I1                                |ALU_Bit_458                   |     5|
1059 
|90    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_473                 |     1|
1060 
|91    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_474            |     4|
1061 
|92    |            \Using_FPGA.ALL_Bits[5].ALU_Bit_I1                                |ALU_Bit_459                   |     5|
1062 
|93    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_471                 |     1|
1063 
|94    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_472            |     4|
1064 
|95    |            \Using_FPGA.ALL_Bits[6].ALU_Bit_I1                                |ALU_Bit_460                   |     5|
1065 
|96    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_469                 |     1|
1066 
|97    |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_470            |     4|
1067 
|98    |            \Using_FPGA.ALL_Bits[7].ALU_Bit_I1                                |ALU_Bit_461                   |     4|
1068 
|99    |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_467                 |     1|
1069 
|100   |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_468            |     3|
1070 
|101   |            \Using_FPGA.ALL_Bits[8].ALU_Bit_I1                                |ALU_Bit_462                   |     6|
1071 
|102   |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2_465                 |     1|
1072 
|103   |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_466            |     5|
1073 
|104   |            \Using_FPGA.ALL_Bits[9].ALU_Bit_I1                                |ALU_Bit_463                   |     5|
1074 
|105   |              \Not_Last_Bit.I_ALU_LUT_V5                                      |MB_LUT6_2                     |     1|
1075 
|106   |              \Not_Last_Bit.MUXCY_XOR_I                                       |MB_MUXCY_XORCY_464            |     4|
1076 
|107   |          Byte_Doublet_Handle_gti_I                                           |Byte_Doublet_Handle_gti       |    50|
1077 
|108   |          Data_Flow_Logic_I                                                   |Data_Flow_Logic               |    65|
1078 
|109   |            \Gen_Bits[0].MEM_EX_Result_Inst                                   |MB_FDRE_401                   |     1|
1079 
|110   |            \Gen_Bits[10].MEM_EX_Result_Inst                                  |MB_FDRE_402                   |     1|
1080 
|111   |            \Gen_Bits[11].MEM_EX_Result_Inst                                  |MB_FDRE_403                   |     1|
1081 
|112   |            \Gen_Bits[12].MEM_EX_Result_Inst                                  |MB_FDRE_404                   |     1|
1082 
|113   |            \Gen_Bits[13].MEM_EX_Result_Inst                                  |MB_FDRE_405                   |     1|
1083 
|114   |            \Gen_Bits[14].MEM_EX_Result_Inst                                  |MB_FDRE_406                   |     1|
1084 
|115   |            \Gen_Bits[15].MEM_EX_Result_Inst                                  |MB_FDRE_407                   |     1|
1085 
|116   |            \Gen_Bits[16].MEM_EX_Result_Inst                                  |MB_FDRE_408                   |     1|
1086 
|117   |            \Gen_Bits[17].MEM_EX_Result_Inst                                  |MB_FDRE_409                   |     1|
1087 
|118   |            \Gen_Bits[18].MEM_EX_Result_Inst                                  |MB_FDRE_410                   |     1|
1088 
|119   |            \Gen_Bits[19].MEM_EX_Result_Inst                                  |MB_FDRE_411                   |     1|
1089 
|120   |            \Gen_Bits[1].MEM_EX_Result_Inst                                   |MB_FDRE_412                   |     1|
1090 
|121   |            \Gen_Bits[20].MEM_EX_Result_Inst                                  |MB_FDRE_413                   |     1|
1091 
|122   |            \Gen_Bits[21].MEM_EX_Result_Inst                                  |MB_FDRE_414                   |     1|
1092 
|123   |            \Gen_Bits[22].MEM_EX_Result_Inst                                  |MB_FDRE_415                   |     1|
1093 
|124   |            \Gen_Bits[23].MEM_EX_Result_Inst                                  |MB_FDRE_416                   |     1|
1094 
|125   |            \Gen_Bits[24].MEM_EX_Result_Inst                                  |MB_FDRE_417                   |     1|
1095 
|126   |            \Gen_Bits[25].MEM_EX_Result_Inst                                  |MB_FDRE_418                   |     1|
1096 
|127   |            \Gen_Bits[26].MEM_EX_Result_Inst                                  |MB_FDRE_419                   |     1|
1097 
|128   |            \Gen_Bits[27].MEM_EX_Result_Inst                                  |MB_FDRE_420                   |     1|
1098 
|129   |            \Gen_Bits[28].MEM_EX_Result_Inst                                  |MB_FDRE_421                   |     1|
1099 
|130   |            \Gen_Bits[29].MEM_EX_Result_Inst                                  |MB_FDRE_422                   |     1|
1100 
|131   |            \Gen_Bits[2].MEM_EX_Result_Inst                                   |MB_FDRE_423                   |     1|
1101 
|132   |            \Gen_Bits[30].MEM_EX_Result_Inst                                  |MB_FDRE_424                   |     1|
1102 
|133   |            \Gen_Bits[31].MEM_EX_Result_Inst                                  |MB_FDRE_425                   |     1|
1103 
|134   |            \Gen_Bits[3].MEM_EX_Result_Inst                                   |MB_FDRE_426                   |     1|
1104 
|135   |            \Gen_Bits[4].MEM_EX_Result_Inst                                   |MB_FDRE_427                   |     1|
1105 
|136   |            \Gen_Bits[5].MEM_EX_Result_Inst                                   |MB_FDRE_428                   |     1|
1106 
|137   |            \Gen_Bits[6].MEM_EX_Result_Inst                                   |MB_FDRE_429                   |     1|
1107 
|138   |            \Gen_Bits[7].MEM_EX_Result_Inst                                   |MB_FDRE_430                   |     1|
1108 
|139   |            \Gen_Bits[8].MEM_EX_Result_Inst                                   |MB_FDRE_431                   |     1|
1109 
|140   |            \Gen_Bits[9].MEM_EX_Result_Inst                                   |MB_FDRE_432                   |     1|
1110 
|141   |          MUL_Unit_I                                                          |mul_unit                      |    20|
1111 
|142   |            \Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2      |dsp_module__parameterized1    |     1|
1112 
|143   |              \Using_DSP48E1.DSP48E1_I1                                       |MB_DSP48E1__parameterized1    |     1|
1113 
|144   |            \Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3      |dsp_module__parameterized3    |     1|
1114 
|145   |              \Using_DSP48E1.DSP48E1_I1                                       |MB_DSP48E1__parameterized3    |     1|
1115 
|146   |            \Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1               |dsp_module                    |     1|
1116 
|147   |              \Using_DSP48E1.DSP48E1_I1                                       |MB_DSP48E1                    |     1|
1117 
|148   |          Operand_Select_I                                                    |Operand_Select_gti            |   246|
1118 
|149   |            \Gen_Bit[0].MUXF7_I1                                              |MB_MUXF7_369                  |     1|
1119 
|150   |            \Gen_Bit[10].MUXF7_I1                                             |MB_MUXF7_370                  |     2|
1120 
|151   |            \Gen_Bit[11].MUXF7_I1                                             |MB_MUXF7_371                  |     2|
1121 
|152   |            \Gen_Bit[12].MUXF7_I1                                             |MB_MUXF7_372                  |     2|
1122 
|153   |            \Gen_Bit[13].MUXF7_I1                                             |MB_MUXF7_373                  |     2|
1123 
|154   |            \Gen_Bit[14].MUXF7_I1                                             |MB_MUXF7_374                  |     2|
1124 
|155   |            \Gen_Bit[15].MUXF7_I1                                             |MB_MUXF7_375                  |     2|
1125 
|156   |            \Gen_Bit[16].MUXF7_I1                                             |MB_MUXF7_376                  |     2|
1126 
|157   |            \Gen_Bit[17].MUXF7_I1                                             |MB_MUXF7_377                  |     2|
1127 
|158   |            \Gen_Bit[18].MUXF7_I1                                             |MB_MUXF7_378                  |     2|
1128 
|159   |            \Gen_Bit[19].MUXF7_I1                                             |MB_MUXF7_379                  |     2|
1129 
|160   |            \Gen_Bit[1].MUXF7_I1                                              |MB_MUXF7_380                  |     2|
1130 
|161   |            \Gen_Bit[20].MUXF7_I1                                             |MB_MUXF7_381                  |     2|
1131 
|162   |            \Gen_Bit[21].MUXF7_I1                                             |MB_MUXF7_382                  |     2|
1132 
|163   |            \Gen_Bit[22].MUXF7_I1                                             |MB_MUXF7_383                  |     2|
1133 
|164   |            \Gen_Bit[23].MUXF7_I1                                             |MB_MUXF7_384                  |     2|
1134 
|165   |            \Gen_Bit[24].MUXF7_I1                                             |MB_MUXF7_385                  |     3|
1135 
|166   |            \Gen_Bit[25].MUXF7_I1                                             |MB_MUXF7_386                  |     3|
1136 
|167   |            \Gen_Bit[26].MUXF7_I1                                             |MB_MUXF7_387                  |     2|
1137 
|168   |            \Gen_Bit[27].MUXF7_I1                                             |MB_MUXF7_388                  |     2|
1138 
|169   |            \Gen_Bit[28].MUXF7_I1                                             |MB_MUXF7_389                  |     3|
1139 
|170   |            \Gen_Bit[29].MUXF7_I1                                             |MB_MUXF7_390                  |     2|
1140 
|171   |            \Gen_Bit[2].MUXF7_I1                                              |MB_MUXF7_391                  |     2|
1141 
|172   |            \Gen_Bit[30].MUXF7_I1                                             |MB_MUXF7_392                  |     2|
1142 
|173   |            \Gen_Bit[31].MUXF7_I1                                             |MB_MUXF7_393                  |     2|
1143 
|174   |            \Gen_Bit[3].MUXF7_I1                                              |MB_MUXF7_394                  |     2|
1144 
|175   |            \Gen_Bit[4].MUXF7_I1                                              |MB_MUXF7_395                  |     2|
1145 
|176   |            \Gen_Bit[5].MUXF7_I1                                              |MB_MUXF7_396                  |     2|
1146 
|177   |            \Gen_Bit[6].MUXF7_I1                                              |MB_MUXF7_397                  |     2|
1147 
|178   |            \Gen_Bit[7].MUXF7_I1                                              |MB_MUXF7_398                  |     2|
1148 
|179   |            \Gen_Bit[8].MUXF7_I1                                              |MB_MUXF7_399                  |     2|
1149 
|180   |            \Gen_Bit[9].MUXF7_I1                                              |MB_MUXF7_400                  |     2|
1150 
|181   |          Register_File_I                                                     |Register_File_gti             |    23|
1151 
|182   |            \Using_LUT6.All_RAM32M[0].ram32m_i                                |MB_RAM32M                     |     2|
1152 
|183   |            \Using_LUT6.All_RAM32M[10].ram32m_i                               |MB_RAM32M_354                 |     1|
1153 
|184   |            \Using_LUT6.All_RAM32M[11].ram32m_i                               |MB_RAM32M_355                 |     2|
1154 
|185   |            \Using_LUT6.All_RAM32M[12].ram32m_i                               |MB_RAM32M_356                 |     1|
1155 
|186   |            \Using_LUT6.All_RAM32M[13].ram32m_i                               |MB_RAM32M_357                 |     1|
1156 
|187   |            \Using_LUT6.All_RAM32M[14].ram32m_i                               |MB_RAM32M_358                 |     1|
1157 
|188   |            \Using_LUT6.All_RAM32M[15].ram32m_i                               |MB_RAM32M_359                 |     1|
1158 
|189   |            \Using_LUT6.All_RAM32M[1].ram32m_i                                |MB_RAM32M_360                 |     1|
1159 
|190   |            \Using_LUT6.All_RAM32M[2].ram32m_i                                |MB_RAM32M_361                 |     2|
1160 
|191   |            \Using_LUT6.All_RAM32M[3].ram32m_i                                |MB_RAM32M_362                 |     1|
1161 
|192   |            \Using_LUT6.All_RAM32M[4].ram32m_i                                |MB_RAM32M_363                 |     2|
1162 
|193   |            \Using_LUT6.All_RAM32M[5].ram32m_i                                |MB_RAM32M_364                 |     1|
1163 
|194   |            \Using_LUT6.All_RAM32M[6].ram32m_i                                |MB_RAM32M_365                 |     2|
1164 
|195   |            \Using_LUT6.All_RAM32M[7].ram32m_i                                |MB_RAM32M_366                 |     1|
1165 
|196   |            \Using_LUT6.All_RAM32M[8].ram32m_i                                |MB_RAM32M_367                 |     2|
1166 
|197   |            \Using_LUT6.All_RAM32M[9].ram32m_i                                |MB_RAM32M_368                 |     2|
1167 
|198   |          Shift_Logic_Module_I                                                |Shift_Logic_Module_gti        |     0|
1168 
|199   |          \Using_DAXI_ALU_Carry.Direct_MUXCY_I                                |MB_MUXCY_243                  |     1|
1169 
|200   |          \Using_DAXI_ALU_Carry.Post_MUXCY_I                                  |MB_MUXCY_244                  |     1|
1170 
|201   |          \Using_DAXI_ALU_Carry.direct_lut_INST                               |MB_LUT6_2__parameterized1     |     1|
1171 
|202   |          Zero_Detect_I                                                       |Zero_Detect_gti               |    12|
1172 
|203   |            Part_Of_Zero_Carry_Start                                          |MB_MUXCY_347                  |     1|
1173 
|204   |            \Zero_Detecting[0].I_Part_Of_Zero_Detect                          |MB_MUXCY_348                  |     1|
1174 
|205   |            \Zero_Detecting[1].I_Part_Of_Zero_Detect                          |MB_MUXCY_349                  |     1|
1175 
|206   |            \Zero_Detecting[2].I_Part_Of_Zero_Detect                          |MB_MUXCY_350                  |     1|
1176 
|207   |            \Zero_Detecting[3].I_Part_Of_Zero_Detect                          |MB_MUXCY_351                  |     1|
1177 
|208   |            \Zero_Detecting[4].I_Part_Of_Zero_Detect                          |MB_MUXCY_352                  |     1|
1178 
|209   |            \Zero_Detecting[5].I_Part_Of_Zero_Detect                          |MB_MUXCY_353                  |     1|
1179 
|210   |          exception_registers_I1                                              |exception_registers_gti       |   161|
1180 
|211   |            CarryIn_MUXCY                                                     |MB_MUXCY_252                  |     1|
1181 
|212   |            \Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5     |     1|
1182 
|213   |            \Using_FPGA_LUT6.Gen_Ret_Addr[0].MUXCY_XOR_I                      |MB_MUXCY_XORCY_253            |     2|
1183 
|214   |            \Using_FPGA_LUT6.Gen_Ret_Addr[0].WB_PC_FDE                        |MB_FDE                        |     1|
1184 
|215   |            \Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_254 |     1|
1185 
|216   |            \Using_FPGA_LUT6.Gen_Ret_Addr[10].MUXCY_XOR_I                     |MB_MUXCY_XORCY_255            |     4|
1186 
|217   |            \Using_FPGA_LUT6.Gen_Ret_Addr[10].WB_PC_FDE                       |MB_FDE_256                    |     1|
1187 
|218   |            \Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_257 |     1|
1188 
|219   |            \Using_FPGA_LUT6.Gen_Ret_Addr[11].MUXCY_XOR_I                     |MB_MUXCY_XORCY_258            |     4|
1189 
|220   |            \Using_FPGA_LUT6.Gen_Ret_Addr[11].WB_PC_FDE                       |MB_FDE_259                    |     1|
1190 
|221   |            \Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_260 |     1|
1191 
|222   |            \Using_FPGA_LUT6.Gen_Ret_Addr[12].MUXCY_XOR_I                     |MB_MUXCY_XORCY_261            |     3|
1192 
|223   |            \Using_FPGA_LUT6.Gen_Ret_Addr[12].WB_PC_FDE                       |MB_FDE_262                    |     1|
1193 
|224   |            \Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_263 |     1|
1194 
|225   |            \Using_FPGA_LUT6.Gen_Ret_Addr[13].MUXCY_XOR_I                     |MB_MUXCY_XORCY_264            |     3|
1195 
|226   |            \Using_FPGA_LUT6.Gen_Ret_Addr[13].WB_PC_FDE                       |MB_FDE_265                    |     1|
1196 
|227   |            \Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_266 |     1|
1197 
|228   |            \Using_FPGA_LUT6.Gen_Ret_Addr[14].MUXCY_XOR_I                     |MB_MUXCY_XORCY_267            |     3|
1198 
|229   |            \Using_FPGA_LUT6.Gen_Ret_Addr[14].WB_PC_FDE                       |MB_FDE_268                    |     1|
1199 
|230   |            \Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_269 |     1|
1200 
|231   |            \Using_FPGA_LUT6.Gen_Ret_Addr[15].MUXCY_XOR_I                     |MB_MUXCY_XORCY_270            |     3|
1201 
|232   |            \Using_FPGA_LUT6.Gen_Ret_Addr[15].WB_PC_FDE                       |MB_FDE_271                    |     1|
1202 
|233   |            \Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_272 |     1|
1203 
|234   |            \Using_FPGA_LUT6.Gen_Ret_Addr[16].MUXCY_XOR_I                     |MB_MUXCY_XORCY_273            |     3|
1204 
|235   |            \Using_FPGA_LUT6.Gen_Ret_Addr[16].WB_PC_FDE                       |MB_FDE_274                    |     1|
1205 
|236   |            \Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_275 |     1|
1206 
|237   |            \Using_FPGA_LUT6.Gen_Ret_Addr[17].MUXCY_XOR_I                     |MB_MUXCY_XORCY_276            |     3|
1207 
|238   |            \Using_FPGA_LUT6.Gen_Ret_Addr[17].WB_PC_FDE                       |MB_FDE_277                    |     1|
1208 
|239   |            \Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_278 |     1|
1209 
|240   |            \Using_FPGA_LUT6.Gen_Ret_Addr[18].MUXCY_XOR_I                     |MB_MUXCY_XORCY_279            |     3|
1210 
|241   |            \Using_FPGA_LUT6.Gen_Ret_Addr[18].WB_PC_FDE                       |MB_FDE_280                    |     1|
1211 
|242   |            \Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_281 |     1|
1212 
|243   |            \Using_FPGA_LUT6.Gen_Ret_Addr[19].MUXCY_XOR_I                     |MB_MUXCY_XORCY_282            |     3|
1213 
|244   |            \Using_FPGA_LUT6.Gen_Ret_Addr[19].WB_PC_FDE                       |MB_FDE_283                    |     1|
1214 
|245   |            \Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_284 |     1|
1215 
|246   |            \Using_FPGA_LUT6.Gen_Ret_Addr[1].MUXCY_XOR_I                      |MB_MUXCY_XORCY_285            |     3|
1216 
|247   |            \Using_FPGA_LUT6.Gen_Ret_Addr[1].WB_PC_FDE                        |MB_FDE_286                    |     1|
1217 
|248   |            \Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_287 |     1|
1218 
|249   |            \Using_FPGA_LUT6.Gen_Ret_Addr[20].MUXCY_XOR_I                     |MB_MUXCY_XORCY_288            |     4|
1219 
|250   |            \Using_FPGA_LUT6.Gen_Ret_Addr[20].WB_PC_FDE                       |MB_FDE_289                    |     1|
1220 
|251   |            \Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_290 |     1|
1221 
|252   |            \Using_FPGA_LUT6.Gen_Ret_Addr[21].MUXCY_XOR_I                     |MB_MUXCY_XORCY_291            |     4|
1222 
|253   |            \Using_FPGA_LUT6.Gen_Ret_Addr[21].WB_PC_FDE                       |MB_FDE_292                    |     1|
1223 
|254   |            \Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_293 |     1|
1224 
|255   |            \Using_FPGA_LUT6.Gen_Ret_Addr[22].MUXCY_XOR_I                     |MB_MUXCY_XORCY_294            |     3|
1225 
|256   |            \Using_FPGA_LUT6.Gen_Ret_Addr[22].WB_PC_FDE                       |MB_FDE_295                    |     1|
1226 
|257   |            \Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_296 |     1|
1227 
|258   |            \Using_FPGA_LUT6.Gen_Ret_Addr[23].MUXCY_XOR_I                     |MB_MUXCY_XORCY_297            |     3|
1228 
|259   |            \Using_FPGA_LUT6.Gen_Ret_Addr[23].WB_PC_FDE                       |MB_FDE_298                    |     1|
1229 
|260   |            \Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_299 |     1|
1230 
|261   |            \Using_FPGA_LUT6.Gen_Ret_Addr[24].MUXCY_XOR_I                     |MB_MUXCY_XORCY_300            |     2|
1231 
|262   |            \Using_FPGA_LUT6.Gen_Ret_Addr[24].WB_PC_FDE                       |MB_FDE_301                    |     1|
1232 
|263   |            \Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_302 |     1|
1233 
|264   |            \Using_FPGA_LUT6.Gen_Ret_Addr[25].MUXCY_XOR_I                     |MB_MUXCY_XORCY_303            |     4|
1234 
|265   |            \Using_FPGA_LUT6.Gen_Ret_Addr[25].WB_PC_FDE                       |MB_FDE_304                    |     1|
1235 
|266   |            \Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_305 |     1|
1236 
|267   |            \Using_FPGA_LUT6.Gen_Ret_Addr[26].MUXCY_XOR_I                     |MB_MUXCY_XORCY_306            |     3|
1237 
|268   |            \Using_FPGA_LUT6.Gen_Ret_Addr[26].WB_PC_FDE                       |MB_FDE_307                    |     1|
1238 
|269   |            \Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_308 |     1|
1239 
|270   |            \Using_FPGA_LUT6.Gen_Ret_Addr[27].MUXCY_XOR_I                     |MB_MUXCY_XORCY_309            |     2|
1240 
|271   |            \Using_FPGA_LUT6.Gen_Ret_Addr[27].WB_PC_FDE                       |MB_FDE_310                    |     1|
1241 
|272   |            \Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_311 |     1|
1242 
|273   |            \Using_FPGA_LUT6.Gen_Ret_Addr[28].MUXCY_XOR_I                     |MB_MUXCY_XORCY_312            |     2|
1243 
|274   |            \Using_FPGA_LUT6.Gen_Ret_Addr[28].WB_PC_FDE                       |MB_FDE_313                    |     1|
1244 
|275   |            \Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_314 |     1|
1245 
|276   |            \Using_FPGA_LUT6.Gen_Ret_Addr[29].MUXCY_XOR_I                     |MB_MUXCY_XORCY_315            |     2|
1246 
|277   |            \Using_FPGA_LUT6.Gen_Ret_Addr[29].WB_PC_FDE                       |MB_FDE_316                    |     1|
1247 
|278   |            \Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_317 |     1|
1248 
|279   |            \Using_FPGA_LUT6.Gen_Ret_Addr[2].MUXCY_XOR_I                      |MB_MUXCY_XORCY_318            |     3|
1249 
|280   |            \Using_FPGA_LUT6.Gen_Ret_Addr[2].WB_PC_FDE                        |MB_FDE_319                    |     1|
1250 
|281   |            \Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_320 |     1|
1251 
|282   |            \Using_FPGA_LUT6.Gen_Ret_Addr[30].MUXCY_XOR_I                     |MB_MUXCY_XORCY_321            |     3|
1252 
|283   |            \Using_FPGA_LUT6.Gen_Ret_Addr[30].WB_PC_FDE                       |MB_FDE_322                    |     1|
1253 
|284   |            \Using_FPGA_LUT6.Gen_Ret_Addr[31].I_RET_ADDR_WB                   |MB_LUT6_2__parameterized5_323 |     1|
1254 
|285   |            \Using_FPGA_LUT6.Gen_Ret_Addr[31].MUXCY_XOR_I                     |MB_MUXCY_XORCY_324            |     2|
1255 
|286   |            \Using_FPGA_LUT6.Gen_Ret_Addr[31].WB_PC_FDE                       |MB_FDE_325                    |     1|
1256 
|287   |            \Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_326 |     1|
1257 
|288   |            \Using_FPGA_LUT6.Gen_Ret_Addr[3].MUXCY_XOR_I                      |MB_MUXCY_XORCY_327            |     3|
1258 
|289   |            \Using_FPGA_LUT6.Gen_Ret_Addr[3].WB_PC_FDE                        |MB_FDE_328                    |     1|
1259 
|290   |            \Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_329 |     1|
1260 
|291   |            \Using_FPGA_LUT6.Gen_Ret_Addr[4].MUXCY_XOR_I                      |MB_MUXCY_XORCY_330            |     3|
1261 
|292   |            \Using_FPGA_LUT6.Gen_Ret_Addr[4].WB_PC_FDE                        |MB_FDE_331                    |     1|
1262 
|293   |            \Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_332 |     1|
1263 
|294   |            \Using_FPGA_LUT6.Gen_Ret_Addr[5].MUXCY_XOR_I                      |MB_MUXCY_XORCY_333            |     3|
1264 
|295   |            \Using_FPGA_LUT6.Gen_Ret_Addr[5].WB_PC_FDE                        |MB_FDE_334                    |     1|
1265 
|296   |            \Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_335 |     1|
1266 
|297   |            \Using_FPGA_LUT6.Gen_Ret_Addr[6].MUXCY_XOR_I                      |MB_MUXCY_XORCY_336            |     3|
1267 
|298   |            \Using_FPGA_LUT6.Gen_Ret_Addr[6].WB_PC_FDE                        |MB_FDE_337                    |     1|
1268 
|299   |            \Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_338 |     1|
1269 
|300   |            \Using_FPGA_LUT6.Gen_Ret_Addr[7].MUXCY_XOR_I                      |MB_MUXCY_XORCY_339            |     3|
1270 
|301   |            \Using_FPGA_LUT6.Gen_Ret_Addr[7].WB_PC_FDE                        |MB_FDE_340                    |     1|
1271 
|302   |            \Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_341 |     1|
1272 
|303   |            \Using_FPGA_LUT6.Gen_Ret_Addr[8].MUXCY_XOR_I                      |MB_MUXCY_XORCY_342            |     4|
1273 
|304   |            \Using_FPGA_LUT6.Gen_Ret_Addr[8].WB_PC_FDE                        |MB_FDE_343                    |     1|
1274 
|305   |            \Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB                    |MB_LUT6_2__parameterized5_344 |     1|
1275 
|306   |            \Using_FPGA_LUT6.Gen_Ret_Addr[9].MUXCY_XOR_I                      |MB_MUXCY_XORCY_345            |     3|
1276 
|307   |            \Using_FPGA_LUT6.Gen_Ret_Addr[9].WB_PC_FDE                        |MB_FDE_346                    |     1|
1277 
|308   |          msr_reg_i                                                           |msr_reg_gti                   |    20|
1278 
|309   |            \MEM_MSR_Bits[28].Using_FDR.MSR_I                                 |MB_FDR_245                    |     2|
1279 
|310   |            \MEM_MSR_Bits[29].Using_FDR.MSR_I                                 |MB_FDR_246                    |     3|
1280 
|311   |            \MEM_MSR_Bits[30].Using_FDR.MSR_I                                 |MB_FDR_247                    |     3|
1281 
|312   |            \OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I                            |MB_FDR_248                    |     1|
1282 
|313   |            \OF_EX_MSR_Bits[28].Using_FDR.MSR_of_I                            |MB_FDR_249                    |     1|
1283 
|314   |            \OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I                            |MB_FDR_250                    |     2|
1284 
|315   |            \OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I                            |MB_FDR_251                    |     2|
1285 
|316   |        Decode_I                                                              |Decode_gti                    |  1358|
1286 
|317   |          PC_Module_I                                                         |PC_Module_gti                 |   343|
1287 
|318   |            \Instruction_Prefetch_Mux[0].Gen_Instr_DFF                        |MB_FDR_150                    |     2|
1288 
|319   |            \Instruction_Prefetch_Mux[0].PC_Mux_MUXF7                         |MB_MUXF7_151                  |     2|
1289 
|320   |            \Instruction_Prefetch_Mux[10].Gen_Instr_DFF                       |MB_FDR_152                    |     3|
1290 
|321   |            \Instruction_Prefetch_Mux[10].PC_Mux_MUXF7                        |MB_MUXF7_153                  |     2|
1291 
|322   |            \Instruction_Prefetch_Mux[11].Gen_Instr_DFF                       |MB_FDR_154                    |     3|
1292 
|323   |            \Instruction_Prefetch_Mux[11].PC_Mux_MUXF7                        |MB_MUXF7_155                  |     2|
1293 
|324   |            \Instruction_Prefetch_Mux[12].Gen_Instr_DFF                       |MB_FDR_156                    |     3|
1294 
|325   |            \Instruction_Prefetch_Mux[12].PC_Mux_MUXF7                        |MB_MUXF7_157                  |     2|
1295 
|326   |            \Instruction_Prefetch_Mux[13].Gen_Instr_DFF                       |MB_FDR_158                    |     3|
1296 
|327   |            \Instruction_Prefetch_Mux[13].PC_Mux_MUXF7                        |MB_MUXF7_159                  |     2|
1297 
|328   |            \Instruction_Prefetch_Mux[14].Gen_Instr_DFF                       |MB_FDR_160                    |     3|
1298 
|329   |            \Instruction_Prefetch_Mux[14].PC_Mux_MUXF7                        |MB_MUXF7_161                  |     2|
1299 
|330   |            \Instruction_Prefetch_Mux[15].Gen_Instr_DFF                       |MB_FDR_162                    |     3|
1300 
|331   |            \Instruction_Prefetch_Mux[15].PC_Mux_MUXF7                        |MB_MUXF7_163                  |     2|
1301 
|332   |            \Instruction_Prefetch_Mux[16].Gen_Instr_DFF                       |MB_FDR_164                    |     3|
1302 
|333   |            \Instruction_Prefetch_Mux[16].PC_Mux_MUXF7                        |MB_MUXF7_165                  |     2|
1303 
|334   |            \Instruction_Prefetch_Mux[17].Gen_Instr_DFF                       |MB_FDR_166                    |     3|
1304 
|335   |            \Instruction_Prefetch_Mux[17].PC_Mux_MUXF7                        |MB_MUXF7_167                  |     2|
1305 
|336   |            \Instruction_Prefetch_Mux[18].Gen_Instr_DFF                       |MB_FDR_168                    |     3|
1306 
|337   |            \Instruction_Prefetch_Mux[18].PC_Mux_MUXF7                        |MB_MUXF7_169                  |     2|
1307 
|338   |            \Instruction_Prefetch_Mux[19].Gen_Instr_DFF                       |MB_FDR_170                    |     3|
1308 
|339   |            \Instruction_Prefetch_Mux[19].PC_Mux_MUXF7                        |MB_MUXF7_171                  |     2|
1309 
|340   |            \Instruction_Prefetch_Mux[1].Gen_Instr_DFF                        |MB_FDR_172                    |     3|
1310 
|341   |            \Instruction_Prefetch_Mux[1].PC_Mux_MUXF7                         |MB_MUXF7_173                  |     2|
1311 
|342   |            \Instruction_Prefetch_Mux[20].Gen_Instr_DFF                       |MB_FDR_174                    |     3|
1312 
|343   |            \Instruction_Prefetch_Mux[20].PC_Mux_MUXF7                        |MB_MUXF7_175                  |     2|
1313 
|344   |            \Instruction_Prefetch_Mux[21].Gen_Instr_DFF                       |MB_FDR_176                    |     3|
1314 
|345   |            \Instruction_Prefetch_Mux[21].PC_Mux_MUXF7                        |MB_MUXF7_177                  |     2|
1315 
|346   |            \Instruction_Prefetch_Mux[22].Gen_Instr_DFF                       |MB_FDR_178                    |     3|
1316 
|347   |            \Instruction_Prefetch_Mux[22].PC_Mux_MUXF7                        |MB_MUXF7_179                  |     2|
1317 
|348   |            \Instruction_Prefetch_Mux[23].Gen_Instr_DFF                       |MB_FDR_180                    |     3|
1318 
|349   |            \Instruction_Prefetch_Mux[23].PC_Mux_MUXF7                        |MB_MUXF7_181                  |     2|
1319 
|350   |            \Instruction_Prefetch_Mux[24].Gen_Instr_DFF                       |MB_FDR_182                    |     3|
1320 
|351   |            \Instruction_Prefetch_Mux[24].PC_Mux_MUXF7                        |MB_MUXF7_183                  |     2|
1321 
|352   |            \Instruction_Prefetch_Mux[25].Gen_Instr_DFF                       |MB_FDR_184                    |     3|
1322 
|353   |            \Instruction_Prefetch_Mux[25].PC_Mux_MUXF7                        |MB_MUXF7_185                  |     2|
1323 
|354   |            \Instruction_Prefetch_Mux[26].Gen_Instr_DFF                       |MB_FDR_186                    |     3|
1324 
|355   |            \Instruction_Prefetch_Mux[26].PC_Mux_MUXF7                        |MB_MUXF7_187                  |     2|
1325 
|356   |            \Instruction_Prefetch_Mux[27].Gen_Instr_DFF                       |MB_FDR_188                    |     3|
1326 
|357   |            \Instruction_Prefetch_Mux[27].PC_Mux_MUXF7                        |MB_MUXF7_189                  |     2|
1327 
|358   |            \Instruction_Prefetch_Mux[28].Gen_Instr_DFF                       |MB_FDR_190                    |     2|
1328 
|359   |            \Instruction_Prefetch_Mux[28].PC_Mux_MUXF7                        |MB_MUXF7_191                  |     2|
1329 
|360   |            \Instruction_Prefetch_Mux[29].Gen_Instr_DFF                       |MB_FDR_192                    |     2|
1330 
|361   |            \Instruction_Prefetch_Mux[29].PC_Mux_MUXF7                        |MB_MUXF7_193                  |     2|
1331 
|362   |            \Instruction_Prefetch_Mux[2].Gen_Instr_DFF                        |MB_FDR_194                    |     3|
1332 
|363   |            \Instruction_Prefetch_Mux[2].PC_Mux_MUXF7                         |MB_MUXF7_195                  |     2|
1333 
|364   |            \Instruction_Prefetch_Mux[30].Gen_Instr_DFF                       |MB_FDR_196                    |     2|
1334 
|365   |            \Instruction_Prefetch_Mux[30].PC_Mux_MUXF7                        |MB_MUXF7_197                  |     2|
1335 
|366   |            \Instruction_Prefetch_Mux[31].Gen_Instr_DFF                       |MB_FDR_198                    |     3|
1336 
|367   |            \Instruction_Prefetch_Mux[31].PC_Mux_MUXF7                        |MB_MUXF7_199                  |     2|
1337 
|368   |            \Instruction_Prefetch_Mux[3].Gen_Instr_DFF                        |MB_FDR_200                    |     3|
1338 
|369   |            \Instruction_Prefetch_Mux[3].PC_Mux_MUXF7                         |MB_MUXF7_201                  |     2|
1339 
|370   |            \Instruction_Prefetch_Mux[4].Gen_Instr_DFF                        |MB_FDR_202                    |     3|
1340 
|371   |            \Instruction_Prefetch_Mux[4].PC_Mux_MUXF7                         |MB_MUXF7_203                  |     2|
1341 
|372   |            \Instruction_Prefetch_Mux[5].Gen_Instr_DFF                        |MB_FDR_204                    |     3|
1342 
|373   |            \Instruction_Prefetch_Mux[5].PC_Mux_MUXF7                         |MB_MUXF7_205                  |     2|
1343 
|374   |            \Instruction_Prefetch_Mux[6].Gen_Instr_DFF                        |MB_FDR_206                    |     3|
1344 
|375   |            \Instruction_Prefetch_Mux[6].PC_Mux_MUXF7                         |MB_MUXF7_207                  |     2|
1345 
|376   |            \Instruction_Prefetch_Mux[7].Gen_Instr_DFF                        |MB_FDR_208                    |     3|
1346 
|377   |            \Instruction_Prefetch_Mux[7].PC_Mux_MUXF7                         |MB_MUXF7_209                  |     2|
1347 
|378   |            \Instruction_Prefetch_Mux[8].Gen_Instr_DFF                        |MB_FDR_210                    |     3|
1348 
|379   |            \Instruction_Prefetch_Mux[8].PC_Mux_MUXF7                         |MB_MUXF7_211                  |     2|
1349 
|380   |            \Instruction_Prefetch_Mux[9].Gen_Instr_DFF                        |MB_FDR_212                    |     3|
1350 
|381   |            \Instruction_Prefetch_Mux[9].PC_Mux_MUXF7                         |MB_MUXF7_213                  |     2|
1351 
|382   |            \Using_FPGA.Incr_PC[0].MUXCY_XOR_I                                |MB_MUXCY_XORCY                |     1|
1352 
|383   |            \Using_FPGA.Incr_PC[10].MUXCY_XOR_I                               |MB_MUXCY_XORCY_214            |     2|
1353 
|384   |            \Using_FPGA.Incr_PC[11].MUXCY_XOR_I                               |MB_MUXCY_XORCY_215            |     2|
1354 
|385   |            \Using_FPGA.Incr_PC[12].MUXCY_XOR_I                               |MB_MUXCY_XORCY_216            |     2|
1355 
|386   |            \Using_FPGA.Incr_PC[13].MUXCY_XOR_I                               |MB_MUXCY_XORCY_217            |     2|
1356 
|387   |            \Using_FPGA.Incr_PC[14].MUXCY_XOR_I                               |MB_MUXCY_XORCY_218            |     2|
1357 
|388   |            \Using_FPGA.Incr_PC[15].MUXCY_XOR_I                               |MB_MUXCY_XORCY_219            |     2|
1358 
|389   |            \Using_FPGA.Incr_PC[16].MUXCY_XOR_I                               |MB_MUXCY_XORCY_220            |     2|
1359 
|390   |            \Using_FPGA.Incr_PC[17].MUXCY_XOR_I                               |MB_MUXCY_XORCY_221            |     2|
1360 
|391   |            \Using_FPGA.Incr_PC[18].MUXCY_XOR_I                               |MB_MUXCY_XORCY_222            |     2|
1361 
|392   |            \Using_FPGA.Incr_PC[19].MUXCY_XOR_I                               |MB_MUXCY_XORCY_223            |     2|
1362 
|393   |            \Using_FPGA.Incr_PC[1].MUXCY_XOR_I                                |MB_MUXCY_XORCY_224            |     2|
1363 
|394   |            \Using_FPGA.Incr_PC[20].MUXCY_XOR_I                               |MB_MUXCY_XORCY_225            |     2|
1364 
|395   |            \Using_FPGA.Incr_PC[21].MUXCY_XOR_I                               |MB_MUXCY_XORCY_226            |     2|
1365 
|396   |            \Using_FPGA.Incr_PC[22].MUXCY_XOR_I                               |MB_MUXCY_XORCY_227            |     2|
1366 
|397   |            \Using_FPGA.Incr_PC[23].MUXCY_XOR_I                               |MB_MUXCY_XORCY_228            |     2|
1367 
|398   |            \Using_FPGA.Incr_PC[24].MUXCY_XOR_I                               |MB_MUXCY_XORCY_229            |     2|
1368 
|399   |            \Using_FPGA.Incr_PC[25].MUXCY_XOR_I                               |MB_MUXCY_XORCY_230            |     2|
1369 
|400   |            \Using_FPGA.Incr_PC[26].MUXCY_XOR_I                               |MB_MUXCY_XORCY_231            |     2|
1370 
|401   |            \Using_FPGA.Incr_PC[27].MUXCY_XOR_I                               |MB_MUXCY_XORCY_232            |     2|
1371 
|402   |            \Using_FPGA.Incr_PC[28].MUXCY_XOR_I                               |MB_MUXCY_XORCY_233            |     2|
1372 
|403   |            \Using_FPGA.Incr_PC[29].MUXCY_XOR_I                               |MB_MUXCY_XORCY_234            |     2|
1373 
|404   |            \Using_FPGA.Incr_PC[2].MUXCY_XOR_I                                |MB_MUXCY_XORCY_235            |     2|
1374 
|405   |            \Using_FPGA.Incr_PC[3].MUXCY_XOR_I                                |MB_MUXCY_XORCY_236            |     2|
1375 
|406   |            \Using_FPGA.Incr_PC[4].MUXCY_XOR_I                                |MB_MUXCY_XORCY_237            |     2|
1376 
|407   |            \Using_FPGA.Incr_PC[5].MUXCY_XOR_I                                |MB_MUXCY_XORCY_238            |     2|
1377 
|408   |            \Using_FPGA.Incr_PC[6].MUXCY_XOR_I                                |MB_MUXCY_XORCY_239            |     2|
1378 
|409   |            \Using_FPGA.Incr_PC[7].MUXCY_XOR_I                                |MB_MUXCY_XORCY_240            |     2|
1379 
|410   |            \Using_FPGA.Incr_PC[8].MUXCY_XOR_I                                |MB_MUXCY_XORCY_241            |     2|
1380 
|411   |            \Using_FPGA.Incr_PC[9].MUXCY_XOR_I                                |MB_MUXCY_XORCY_242            |     2|
1381 
|412   |          PreFetch_Buffer_I1                                                  |PreFetch_Buffer_gti           |   541|
1382 
|413   |            \Gen_Mux_Select_LUT6[1].Gen_Sel_DFF                               |MB_FDR_56                     |     5|
1383 
|414   |            \Gen_Mux_Select_LUT6[1].Mux_Select_LUT6                           |MB_LUT6                       |     1|
1384 
|415   |            \Gen_Mux_Select_LUT6[2].Gen_Sel_DFF                               |MB_FDR_57                     |     4|
1385 
|416   |            \Gen_Mux_Select_LUT6[2].Mux_Select_LUT6                           |MB_LUT6_58                    |     1|
1386 
|417   |            \Gen_Mux_Select_LUT6[3].Gen_Sel_DFF                               |MB_FDR_59                     |     1|
1387 
|418   |            \Gen_Mux_Select_LUT6[3].Mux_Select_LUT6                           |MB_LUT6_60                    |     1|
1388 
|419   |            \Gen_Mux_Select_LUT6[4].Gen_Sel_DFF                               |MB_FDR_61                     |    44|
1389 
|420   |            \Gen_Mux_Select_LUT6[4].Mux_Select_LUT6                           |MB_LUT6_62                    |     1|
1390 
|421   |            \Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Mux_Select_Delayslot_LUT6  |MB_LUT6__parameterized2       |     1|
1391 
|422   |            \Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Sel_Mux_MUXF7              |MB_MUXF7                      |     2|
1392 
|423   |            \Instruction_Prefetch_Mux[0].Gen_Instr_DFF                        |MB_FDR_63                     |     1|
1393 
|424   |            \Instruction_Prefetch_Mux[0].Instr_Mux_MUXF7                      |MB_MUXF7_64                   |     1|
1394 
|425   |            \Instruction_Prefetch_Mux[10].Gen_Instr_DFF                       |MB_FDR_65                     |     2|
1395 
|426   |            \Instruction_Prefetch_Mux[10].Instr_Mux_MUXF7                     |MB_MUXF7_66                   |     1|
1396 
|427   |            \Instruction_Prefetch_Mux[11].Gen_Instr_DFF                       |MB_FDR_67                     |     1|
1397 
|428   |            \Instruction_Prefetch_Mux[11].Instr_Mux_MUXF7                     |MB_MUXF7_68                   |     1|
1398 
|429   |            \Instruction_Prefetch_Mux[12].Gen_Instr_DFF                       |MB_FDR_69                     |     1|
1399 
|430   |            \Instruction_Prefetch_Mux[12].Instr_Mux_MUXF7                     |MB_MUXF7_70                   |     1|
1400 
|431   |            \Instruction_Prefetch_Mux[13].Gen_Instr_DFF                       |MB_FDR_71                     |     1|
1401 
|432   |            \Instruction_Prefetch_Mux[13].Instr_Mux_MUXF7                     |MB_MUXF7_72                   |     1|
1402 
|433   |            \Instruction_Prefetch_Mux[14].Gen_Instr_DFF                       |MB_FDR_73                     |     1|
1403 
|434   |            \Instruction_Prefetch_Mux[14].Instr_Mux_MUXF7                     |MB_MUXF7_74                   |     1|
1404 
|435   |            \Instruction_Prefetch_Mux[15].Gen_Instr_DFF                       |MB_FDR_75                     |     1|
1405 
|436   |            \Instruction_Prefetch_Mux[15].Instr_Mux_MUXF7                     |MB_MUXF7_76                   |     1|
1406 
|437   |            \Instruction_Prefetch_Mux[16].Gen_Instr_DFF                       |MB_FDR_77                     |    35|
1407 
|438   |            \Instruction_Prefetch_Mux[16].Instr_Mux_MUXF7                     |MB_MUXF7_78                   |     1|
1408 
|439   |            \Instruction_Prefetch_Mux[17].Gen_Instr_DFF                       |MB_FDR_79                     |     5|
1409 
|440   |            \Instruction_Prefetch_Mux[17].Instr_Mux_MUXF7                     |MB_MUXF7_80                   |     1|
1410 
|441   |            \Instruction_Prefetch_Mux[18].Gen_Instr_DFF                       |MB_FDR_81                     |     3|
1411 
|442   |            \Instruction_Prefetch_Mux[18].Instr_Mux_MUXF7                     |MB_MUXF7_82                   |     1|
1412 
|443   |            \Instruction_Prefetch_Mux[19].Gen_Instr_DFF                       |MB_FDR_83                     |     3|
1413 
|444   |            \Instruction_Prefetch_Mux[19].Instr_Mux_MUXF7                     |MB_MUXF7_84                   |     1|
1414 
|445   |            \Instruction_Prefetch_Mux[1].Gen_Instr_DFF                        |MB_FDR_85                     |    15|
1415 
|446   |            \Instruction_Prefetch_Mux[1].Instr_Mux_MUXF7                      |MB_MUXF7_86                   |     1|
1416 
|447   |            \Instruction_Prefetch_Mux[20].Gen_Instr_DFF                       |MB_FDR_87                     |     3|
1417 
|448   |            \Instruction_Prefetch_Mux[20].Instr_Mux_MUXF7                     |MB_MUXF7_88                   |     1|
1418 
|449   |            \Instruction_Prefetch_Mux[21].Gen_Instr_DFF                       |MB_FDR_89                     |     5|
1419 
|450   |            \Instruction_Prefetch_Mux[21].Instr_Mux_MUXF7                     |MB_MUXF7_90                   |     1|
1420 
|451   |            \Instruction_Prefetch_Mux[22].Gen_Instr_DFF                       |MB_FDR_91                     |     3|
1421 
|452   |            \Instruction_Prefetch_Mux[22].Instr_Mux_MUXF7                     |MB_MUXF7_92                   |     1|
1422 
|453   |            \Instruction_Prefetch_Mux[23].Gen_Instr_DFF                       |MB_FDR_93                     |     3|
1423 
|454   |            \Instruction_Prefetch_Mux[23].Instr_Mux_MUXF7                     |MB_MUXF7_94                   |     1|
1424 
|455   |            \Instruction_Prefetch_Mux[24].Gen_Instr_DFF                       |MB_FDR_95                     |     3|
1425 
|456   |            \Instruction_Prefetch_Mux[24].Instr_Mux_MUXF7                     |MB_MUXF7_96                   |     1|
1426 
|457   |            \Instruction_Prefetch_Mux[25].Gen_Instr_DFF                       |MB_FDR_97                     |     4|
1427 
|458   |            \Instruction_Prefetch_Mux[25].Instr_Mux_MUXF7                     |MB_MUXF7_98                   |     1|
1428 
|459   |            \Instruction_Prefetch_Mux[26].Gen_Instr_DFF                       |MB_FDR_99                     |     3|
1429 
|460   |            \Instruction_Prefetch_Mux[26].Instr_Mux_MUXF7                     |MB_MUXF7_100                  |     1|
1430 
|461   |            \Instruction_Prefetch_Mux[27].Gen_Instr_DFF                       |MB_FDR_101                    |     1|
1431 
|462   |            \Instruction_Prefetch_Mux[27].Instr_Mux_MUXF7                     |MB_MUXF7_102                  |     1|
1432 
|463   |            \Instruction_Prefetch_Mux[28].Gen_Instr_DFF                       |MB_FDR_103                    |     1|
1433 
|464   |            \Instruction_Prefetch_Mux[28].Instr_Mux_MUXF7                     |MB_MUXF7_104                  |     1|
1434 
|465   |            \Instruction_Prefetch_Mux[29].Gen_Instr_DFF                       |MB_FDR_105                    |     3|
1435 
|466   |            \Instruction_Prefetch_Mux[29].Instr_Mux_MUXF7                     |MB_MUXF7_106                  |     1|
1436 
|467   |            \Instruction_Prefetch_Mux[2].Gen_Instr_DFF                        |MB_FDR_107                    |    16|
1437 
|468   |            \Instruction_Prefetch_Mux[2].Instr_Mux_MUXF7                      |MB_MUXF7_108                  |     1|
1438 
|469   |            \Instruction_Prefetch_Mux[30].Gen_Instr_DFF                       |MB_FDR_109                    |     5|
1439 
|470   |            \Instruction_Prefetch_Mux[30].Instr_Mux_MUXF7                     |MB_MUXF7_110                  |     1|
1440 
|471   |            \Instruction_Prefetch_Mux[31].Gen_Instr_DFF                       |MB_FDR_111                    |     6|
1441 
|472   |            \Instruction_Prefetch_Mux[31].Instr_Mux_MUXF7                     |MB_MUXF7_112                  |     1|
1442 
|473   |            \Instruction_Prefetch_Mux[32].Gen_Instr_DFF                       |MB_FDR_113                    |     4|
1443 
|474   |            \Instruction_Prefetch_Mux[32].Instr_Mux_MUXF7                     |MB_MUXF7_114                  |     2|
1444 
|475   |            \Instruction_Prefetch_Mux[33].Gen_Instr_DFF                       |MB_FDR_115                    |    42|
1445 
|476   |            \Instruction_Prefetch_Mux[33].Instr_Mux_MUXF7                     |MB_MUXF7_116                  |     1|
1446 
|477   |            \Instruction_Prefetch_Mux[34].Gen_Instr_DFF                       |MB_FDR_117                    |     2|
1447 
|478   |            \Instruction_Prefetch_Mux[34].Instr_Mux_MUXF7                     |MB_MUXF7_118                  |     1|
1448 
|479   |            \Instruction_Prefetch_Mux[35].Gen_Instr_DFF                       |MB_FDR_119                    |     2|
1449 
|480   |            \Instruction_Prefetch_Mux[35].Instr_Mux_MUXF7                     |MB_MUXF7_120                  |     1|
1450 
|481   |            \Instruction_Prefetch_Mux[36].Gen_Instr_DFF                       |MB_FDR_121                    |     1|
1451 
|482   |            \Instruction_Prefetch_Mux[36].Instr_Mux_MUXF7                     |MB_MUXF7_122                  |     1|
1452 
|483   |            \Instruction_Prefetch_Mux[37].Gen_Instr_DFF                       |MB_FDR_123                    |     3|
1453 
|484   |            \Instruction_Prefetch_Mux[37].Instr_Mux_MUXF7                     |MB_MUXF7_124                  |     1|
1454 
|485   |            \Instruction_Prefetch_Mux[38].Gen_Instr_DFF                       |MB_FDR_125                    |    36|
1455 
|486   |            \Instruction_Prefetch_Mux[38].Instr_Mux_MUXF7                     |MB_MUXF7_126                  |     1|
1456 
|487   |            \Instruction_Prefetch_Mux[39].Gen_Instr_DFF                       |MB_FDR_127                    |     2|
1457 
|488   |            \Instruction_Prefetch_Mux[39].Instr_Mux_MUXF7                     |MB_MUXF7_128                  |     1|
1458 
|489   |            \Instruction_Prefetch_Mux[3].Gen_Instr_DFF                        |MB_FDR_129                    |    17|
1459 
|490   |            \Instruction_Prefetch_Mux[3].Instr_Mux_MUXF7                      |MB_MUXF7_130                  |     1|
1460 
|491   |            \Instruction_Prefetch_Mux[40].Gen_Instr_DFF                       |MB_FDR_131                    |     4|
1461 
|492   |            \Instruction_Prefetch_Mux[40].Instr_Mux_MUXF7                     |MB_MUXF7_132                  |     1|
1462 
|493   |            \Instruction_Prefetch_Mux[41].Gen_Instr_DFF                       |MB_FDR_133                    |     2|
1463 
|494   |            \Instruction_Prefetch_Mux[41].Instr_Mux_MUXF7                     |MB_MUXF7_134                  |     1|
1464 
|495   |            \Instruction_Prefetch_Mux[42].Gen_Instr_DFF                       |MB_FDR_135                    |     2|
1465 
|496   |            \Instruction_Prefetch_Mux[42].Instr_Mux_MUXF7                     |MB_MUXF7_136                  |     1|
1466 
|497   |            \Instruction_Prefetch_Mux[4].Gen_Instr_DFF                        |MB_FDR_137                    |     4|
1467 
|498   |            \Instruction_Prefetch_Mux[4].Instr_Mux_MUXF7                      |MB_MUXF7_138                  |     1|
1468 
|499   |            \Instruction_Prefetch_Mux[5].Gen_Instr_DFF                        |MB_FDR_139                    |     9|
1469 
|500   |            \Instruction_Prefetch_Mux[5].Instr_Mux_MUXF7                      |MB_MUXF7_140                  |     1|
1470 
|501   |            \Instruction_Prefetch_Mux[6].Gen_Instr_DFF                        |MB_FDR_141                    |     6|
1471 
|502   |            \Instruction_Prefetch_Mux[6].Instr_Mux_MUXF7                      |MB_MUXF7_142                  |     1|
1472 
|503   |            \Instruction_Prefetch_Mux[7].Gen_Instr_DFF                        |MB_FDR_143                    |    28|
1473 
|504   |            \Instruction_Prefetch_Mux[7].Instr_Mux_MUXF7                      |MB_MUXF7_144                  |     1|
1474 
|505   |            \Instruction_Prefetch_Mux[8].Gen_Instr_DFF                        |MB_FDR_145                    |    46|
1475 
|506   |            \Instruction_Prefetch_Mux[8].Instr_Mux_MUXF7                      |MB_MUXF7_146                  |     1|
1476 
|507   |            \Instruction_Prefetch_Mux[9].Gen_Instr_DFF                        |MB_FDR_147                    |     5|
1477 
|508   |            \Instruction_Prefetch_Mux[9].Instr_Mux_MUXF7                      |MB_MUXF7_148                  |     1|
1478 
|509   |            Last_Sel_DFF                                                      |MB_FDS                        |    44|
1479 
|510   |            Mux_Select_Empty_LUT6                                             |MB_LUT6__parameterized4       |     1|
1480 
|511   |            Mux_Select_OF_Valid_LUT6                                          |MB_LUT6__parameterized6       |     1|
1481 
|512   |            OF_Valid_DFF                                                      |MB_FDR_149                    |     4|
1482 
|513   |          \Use_MuxCy[10].OF_Piperun_Stage                                     |carry_and                     |     1|
1483 
|514   |            MUXCY_I                                                           |MB_MUXCY_55                   |     1|
1484 
|515   |          \Use_MuxCy[11].OF_Piperun_Stage                                     |carry_and_1                   |     7|
1485 
|516   |            MUXCY_I                                                           |MB_MUXCY_54                   |     7|
1486 
|517   |          \Use_MuxCy[1].OF_Piperun_Stage                                      |carry_and_2                   |     1|
1487 
|518   |            MUXCY_I                                                           |MB_MUXCY_53                   |     1|
1488 
|519   |          \Use_MuxCy[2].OF_Piperun_Stage                                      |carry_and_3                   |     2|
1489 
|520   |            MUXCY_I                                                           |MB_MUXCY_52                   |     2|
1490 
|521   |          \Use_MuxCy[3].OF_Piperun_Stage                                      |carry_and_4                   |    11|
1491 
|522   |            MUXCY_I                                                           |MB_MUXCY_51                   |    11|
1492 
|523   |          \Use_MuxCy[4].OF_Piperun_Stage                                      |carry_and_5                   |     1|
1493 
|524   |            MUXCY_I                                                           |MB_MUXCY_50                   |     1|
1494 
|525   |          \Use_MuxCy[5].OF_Piperun_Stage                                      |carry_and_6                   |     1|
1495 
|526   |            MUXCY_I                                                           |MB_MUXCY_49                   |     1|
1496 
|527   |          \Use_MuxCy[6].OF_Piperun_Stage                                      |carry_and_7                   |     1|
1497 
|528   |            MUXCY_I                                                           |MB_MUXCY_48                   |     1|
1498 
|529   |          \Use_MuxCy[7].OF_Piperun_Stage                                      |carry_and_8                   |     1|
1499 
|530   |            MUXCY_I                                                           |MB_MUXCY_47                   |     1|
1500 
|531   |          \Use_MuxCy[8].OF_Piperun_Stage                                      |carry_and_9                   |     1|
1501 
|532   |            MUXCY_I                                                           |MB_MUXCY_46                   |     1|
1502 
|533   |          \Use_MuxCy[9].OF_Piperun_Stage                                      |carry_and_10                  |     1|
1503 
|534   |            MUXCY_I                                                           |MB_MUXCY_45                   |     1|
1504 
|535   |          \Using_FPGA.Gen_Bits[28].MEM_EX_Result_Inst                         |MB_FDRE                       |     3|
1505 
|536   |          \Using_FPGA.Gen_Bits[29].MEM_EX_Result_Inst                         |MB_FDRE_11                    |     3|
1506 
|537   |          \Using_FPGA.Gen_Bits[30].MEM_EX_Result_Inst                         |MB_FDRE_12                    |     2|
1507 
|538   |          \Using_FPGA.Gen_Bits[31].MEM_EX_Result_Inst                         |MB_FDRE_13                    |     3|
1508 
|539   |          \Using_FPGA_2.ex_byte_access_i_Inst                                 |MB_FDRE_14                    |     1|
1509 
|540   |          \Using_FPGA_2.ex_doublet_access_i_Inst                              |MB_FDRE_15                    |     1|
1510 
|541   |          \Using_FPGA_2.ex_is_load_instr_Inst                                 |MB_FDRE_16                    |     5|
1511 
|542   |          \Using_FPGA_2.ex_is_lwx_instr_Inst                                  |MB_FDRE_17                    |     3|
1512 
|543   |          \Using_FPGA_2.ex_is_swx_instr_Inst                                  |MB_FDRE_18                    |     3|
1513 
|544   |          \Using_FPGA_2.ex_load_store_instr_Inst                              |MB_FDRE_19                    |     7|
1514 
|545   |          \Using_FPGA_3.ex_clear_MSR_BIP_instr_Inst                           |MB_FDRE_20                    |     5|
1515 
|546   |          \Using_FPGA_3.of_clear_MSR_BIP_hold_Inst                            |MB_FDR                        |     3|
1516 
|547   |          \Using_FPGA_4.of_read_ex_write_op1_conflict_INST1                   |MB_LUT6__parameterized8       |     1|
1517 
|548   |          \Using_FPGA_4.of_read_ex_write_op1_conflict_INST2                   |MB_LUT6__parameterized10      |     2|
1518 
|549   |          \Using_FPGA_4.of_read_ex_write_op2_conflict_INST1                   |MB_LUT6__parameterized8_21    |     1|
1519 
|550   |          \Using_FPGA_4.of_read_ex_write_op2_conflict_INST2                   |MB_LUT6__parameterized10_22   |     1|
1520 
|551   |          \Using_FPGA_4.of_read_ex_write_op3_conflict_INST1                   |MB_LUT6__parameterized8_23    |     1|
1521 
|552   |          \Using_FPGA_4.of_read_ex_write_op3_conflict_INST2                   |MB_LUT6__parameterized10_24   |     2|
1522 
|553   |          \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1                  |MB_LUT6__parameterized8_25    |     1|
1523 
|554   |          \Using_FPGA_4.of_read_mem_write_op1_conflict_INST2                  |MB_LUT6__parameterized10_26   |     2|
1524 
|555   |          \Using_FPGA_4.of_read_mem_write_op2_conflict_INST1                  |MB_LUT6__parameterized8_27    |     1|
1525 
|556   |          \Using_FPGA_4.of_read_mem_write_op2_conflict_INST2                  |MB_LUT6__parameterized10_28   |     1|
1526 
|557   |          \Using_FPGA_4.of_read_mem_write_op3_conflict_INST1                  |MB_LUT6__parameterized8_29    |     2|
1527 
|558   |          \Using_FPGA_4.of_read_mem_write_op3_conflict_INST2                  |MB_LUT6__parameterized10_30   |     1|
1528 
|559   |          if_pc_incr_carry_and_0                                              |carry_and_31                  |     2|
1529 
|560   |            MUXCY_I                                                           |MB_MUXCY_44                   |     2|
1530 
|561   |          if_pc_incr_carry_and_3                                              |carry_and_32                  |     1|
1531 
|562   |            MUXCY_I                                                           |MB_MUXCY_43                   |     1|
1532 
|563   |          jump_logic_I1                                                       |jump_logic                    |    68|
1533 
|564   |            MUXCY_JUMP_CARRY                                                  |MB_MUXCY_37                   |     3|
1534 
|565   |            MUXCY_JUMP_CARRY2                                                 |MB_MUXCY_38                   |     3|
1535 
|566   |            MUXCY_JUMP_CARRY3                                                 |MB_MUXCY_39                   |     3|
1536 
|567   |            MUXCY_JUMP_CARRY4                                                 |MB_MUXCY_40                   |     2|
1537 
|568   |            MUXCY_JUMP_CARRY5                                                 |MB_MUXCY_41                   |     1|
1538 
|569   |            MUXCY_JUMP_CARRY6                                                 |MB_MUXCY_42                   |    47|
1539 
|570   |          mem_PipeRun_carry_and                                               |carry_and_33                  |     4|
1540 
|571   |            MUXCY_I                                                           |MB_MUXCY_36                   |     4|
1541 
|572   |          mem_wait_on_ready_N_carry_or                                        |carry_or_34                   |     2|
1542 
|573   |            MUXCY_I                                                           |MB_MUXCY_35                   |     2|
1543 
|574   |        \Use_DBUS.DAXI_Interface_I1                                           |DAXI_interface                |    83|
1544 
|575   |        \Use_DLMB.Using_Latch_AS_Logic.AND2B1L_I1                             |MB_AND2B1L                    |     1|
1545 
|576   |        mem_databus_ready_sel_carry_or                                        |carry_or                      |     1|
1546 
|577   |          MUXCY_I                                                             |MB_MUXCY                      |     1|
1547 
|578   |      Reset_DFF                                                               |mb_sync_bit                   |     3|
1548 
|579   |      \Using_Async_Wakeup_1.Wakeup_DFF                                        |mb_sync_bit_0                 |     3|
1549 
+------+------------------------------------------------------------------------------+------------------------------+------+
1550 
---------------------------------------------------------------------------------
1551 
Finished Writing Synthesis Report : Time (s): cpu = 00:01:55 ; elapsed = 00:02:45 . Memory (MB): peak = 2152.680 ; gain = 840.109 ; free physical = 900 ; free virtual = 92873
1552 
---------------------------------------------------------------------------------
1553 
Synthesis finished with 0 errors, 0 critical warnings and 26899 warnings.
1554 
Synthesis Optimization Runtime : Time (s): cpu = 00:01:33 ; elapsed = 00:02:01 . Memory (MB): peak = 2152.680 ; gain = 529.352 ; free physical = 963 ; free virtual = 92936
1555 
Synthesis Optimization Complete : Time (s): cpu = 00:01:55 ; elapsed = 00:02:45 . Memory (MB): peak = 2152.684 ; gain = 840.109 ; free physical = 966 ; free virtual = 92939
1556 
INFO: [Project 1-571] Translating synthesized netlist
1557 
INFO: [Netlist 29-17] Analyzing 533 Unisim elements for replacement
1558 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
1559 
INFO: [Project 1-570] Preparing netlist for logic optimization
1560 
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
1561 
INFO: [Project 1-111] Unisim Transformation Summary:
1562 
  A total of 236 instances were transformed.
1563 
  (MUXCY,XORCY) => CARRY4: 34 instances
1564 
  FDE => FDRE: 32 instances
1565 
  FDR => FDRE: 88 instances
1566 
  FDS => FDSE: 1 instances
1567 
  LUT6_2 => LUT6_2 (LUT5, LUT6): 64 instances
1568 
  MULT_AND => LUT2: 1 instances
1569 
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 16 instances
1570 
 
1571 
INFO: [Common 17-83] Releasing license: Synthesis
1572 
281 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
1573 
synth_design completed successfully
1574 
synth_design: Time (s): cpu = 00:02:00 ; elapsed = 00:02:50 . Memory (MB): peak = 2203.695 ; gain = 926.949 ; free physical = 1119 ; free virtual = 93094
1575 
INFO: [Common 17-1381] The checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/microblaze_0_synth_1/microblaze_0.dcp' has been generated.

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