OpenCores
URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.cache/] [ip/] [2017.4/] [bd4a7ee8a4ca1bdd/] [bd4a7ee8a4ca1bdd.xci] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 vv_gulyaev
2
3
  xilinx.com
4
  ipcache
5
  bd4a7ee8a4ca1bdd
6
  0
7
  
8
    
9
      clk_gen
10
      
11
      
12
        100000000
13
        100000000
14
        MMCM
15
        false
16
        empty
17
        cddcdone
18
        cddcreq
19
        clkfb_in_n
20
        clkfb_in
21
        clkfb_in_p
22
        SINGLE
23
        clkfb_out_n
24
        clkfb_out
25
        clkfb_out_p
26
        clkfb_stopped
27
        50.0
28
        0.010
29
        100.0
30
        0.010
31
        BUFG
32
        112.316
33
        false
34
        89.971
35
        50.000
36
        100.000
37
        0.000
38
        1
39
        true
40
        BUFG
41
        0.0
42
        false
43
        0.0
44
        50.000
45
        100.000
46
        0.000
47
        1
48
        false
49
        BUFG
50
        0.0
51
        false
52
        0.0
53
        50.000
54
        100.000
55
        0.000
56
        1
57
        false
58
        BUFG
59
        0.0
60
        false
61
        0.0
62
        50.000
63
        100.000
64
        0.000
65
        1
66
        false
67
        BUFG
68
        0.0
69
        false
70
        0.0
71
        50.000
72
        100.000
73
        0.000
74
        1
75
        false
76
        BUFG
77
        0.0
78
        false
79
        0.0
80
        50.000
81
        100.000
82
        0.000
83
        1
84
        false
85
        BUFG
86
        0.0
87
        false
88
        0.0
89
        50.000
90
        100.000
91
        0.000
92
        1
93
        false
94
        600.000
95
        sys_diff_clock
96
        Custom
97
        clk_in_sel
98
        clk_out1
99
        false
100
        clk_out2
101
        false
102
        clk_out3
103
        false
104
        clk_out4
105
        false
106
        clk_out5
107
        false
108
        clk_out6
109
        false
110
        clk_out7
111
        false
112
        CLK_VALID
113
        auto
114
        clk_gen
115
        daddr
116
        dclk
117
        den
118
        Custom
119
        Custom
120
        din
121
        dout
122
        drdy
123
        dwe
124
        false
125
        false
126
        false
127
        false
128
        false
129
        false
130
        false
131
        false
132
        false
133
        FDBK_AUTO
134
        input_clk_stopped
135
        frequency
136
        Enable_AXI
137
        Units_MHz
138
        Units_UI
139
        UI
140
        No_Jitter
141
        locked
142
        OPTIMIZED
143
        5.000
144
        0.000
145
        false
146
        5.000
147
        10.0
148
        10.000
149
        0.500
150
        0.000
151
        false
152
        1
153
        0.500
154
        0.000
155
        false
156
        1
157
        0.500
158
        0.000
159
        false
160
        1
161
        0.500
162
        0.000
163
        false
164
        false
165
        1
166
        0.500
167
        0.000
168
        false
169
        1
170
        0.500
171
        0.000
172
        false
173
        1
174
        0.500
175
        0.000
176
        false
177
        false
178
        ZHOLD
179
        1
180
        None
181
        0.010
182
        0.010
183
        false
184
        1
185
        false
186
        false
187
        WAVEFORM
188
        false
189
        UNKNOWN
190
        OPTIMIZED
191
        4
192
        0.000
193
        10.000
194
        1
195
        0.500
196
        0.000
197
        1
198
        0.500
199
        0.000
200
        1
201
        0.500
202
        0.000
203
        1
204
        0.500
205
        0.000
206
        1
207
        0.500
208
        0.000
209
        1
210
        0.500
211
        0.000
212
        CLKFBOUT
213
        SYSTEM_SYNCHRONOUS
214
        1
215
        None
216
        0.010
217
        power_down
218
        1
219
        clk_in1
220
        MMCM
221
        mmcm_adv
222
        200.000
223
        0.010
224
        10.000
225
        Differential_clock_capable_pin
226
        psclk
227
        psdone
228
        psen
229
        psincdec
230
        100.0
231
        REL_PRIMARY
232
        Custom
233
        reset
234
        ACTIVE_HIGH
235
        100.000
236
        0.010
237
        10.000
238
        clk_in2
239
        Single_ended_clock_capable_pin
240
        CENTER_HIGH
241
        250
242
        0.004
243
        STATUS
244
        empty
245
        100.0
246
        100.0
247
        100.0
248
        100.0
249
        false
250
        false
251
        false
252
        false
253
        false
254
        false
255
        false
256
        true
257
        false
258
        false
259
        true
260
        false
261
        false
262
        false
263
        true
264
        false
265
        true
266
        false
267
        false
268
        false
269
        kintex7
270
        xilinx.com:kc705:part0:1.5
271
        xc7k325t
272
        ffg900
273
        VERILOG
274
        
275
        MIXED
276
        -2
277
        
278
        TRUE
279
        TRUE
280
        cc249fca
281
        bd4a7ee8a4ca1bdd
282
        IP_Unknown
283
        3
284
        TRUE
285
        .
286
        
287
        .
288
        2017.4
289
        GLOBAL
290
      
291
    
292
  
293

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.