Subversion Repositories aes-128-ecb-encoder

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

-- --------------------------------------------------------------------------------

-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017

-- Date        : Thu Jul 23 09:43:35 2020

-- Host        : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)

-- Command     : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix

--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_gen_sim_netlist.vhdl

-- Design      : clk_gen

-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or

--               synthesized. This netlist cannot be used for SDF annotated simulation.

-- Device      : xc7k325tffg900-2

-- --------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_gen_clk_wiz is

  port (

    clk_out1 : out STD_LOGIC;

    reset : in STD_LOGIC;

    locked : out STD_LOGIC;

    clk_in1_p : in STD_LOGIC;

    clk_in1_n : in STD_LOGIC

  );

end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_gen_clk_wiz;

architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_gen_clk_wiz is

  signal clk_in1_clk_gen : STD_LOGIC;

  signal clk_out1_clk_gen : STD_LOGIC;

  signal clkfbout_buf_clk_gen : STD_LOGIC;

  signal clkfbout_clk_gen : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;

  signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );

  attribute BOX_TYPE : string;

  attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";

  attribute BOX_TYPE of clkin1_ibufgds : label is "PRIMITIVE";

  attribute CAPACITANCE : string;

  attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE";

  attribute IBUF_DELAY_VALUE : string;

  attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0";

  attribute IFD_DELAY_VALUE : string;

  attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO";

  attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";

  attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";

begin

clkf_buf: unisim.vcomponents.BUFG

     port map (

      I => clkfbout_clk_gen,

      O => clkfbout_buf_clk_gen

    );

clkin1_ibufgds: unisim.vcomponents.IBUFDS

    generic map(

      IOSTANDARD => "DEFAULT"

    )

        port map (

      I => clk_in1_p,

      IB => clk_in1_n,

      O => clk_in1_clk_gen

    );

clkout1_buf: unisim.vcomponents.BUFG

     port map (

      I => clk_out1_clk_gen,

      O => clk_out1

    );

mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV

    generic map(

      BANDWIDTH => "OPTIMIZED",

      CLKFBOUT_MULT_F => 5.000000,

      CLKFBOUT_PHASE => 0.000000,

      CLKFBOUT_USE_FINE_PS => false,

      CLKIN1_PERIOD => 5.000000,

      CLKIN2_PERIOD => 0.000000,

      CLKOUT0_DIVIDE_F => 10.000000,

      CLKOUT0_DUTY_CYCLE => 0.500000,

      CLKOUT0_PHASE => 0.000000,

      CLKOUT0_USE_FINE_PS => false,

      CLKOUT1_DIVIDE => 1,

      CLKOUT1_DUTY_CYCLE => 0.500000,

      CLKOUT1_PHASE => 0.000000,

      CLKOUT1_USE_FINE_PS => false,

      CLKOUT2_DIVIDE => 1,

      CLKOUT2_DUTY_CYCLE => 0.500000,

      CLKOUT2_PHASE => 0.000000,

      CLKOUT2_USE_FINE_PS => false,

      CLKOUT3_DIVIDE => 1,

      CLKOUT3_DUTY_CYCLE => 0.500000,

      CLKOUT3_PHASE => 0.000000,

      CLKOUT3_USE_FINE_PS => false,

      CLKOUT4_CASCADE => false,

      CLKOUT4_DIVIDE => 1,

      CLKOUT4_DUTY_CYCLE => 0.500000,

      CLKOUT4_PHASE => 0.000000,

      CLKOUT4_USE_FINE_PS => false,

      CLKOUT5_DIVIDE => 1,

      CLKOUT5_DUTY_CYCLE => 0.500000,

      CLKOUT5_PHASE => 0.000000,

      CLKOUT5_USE_FINE_PS => false,

      CLKOUT6_DIVIDE => 1,

      CLKOUT6_DUTY_CYCLE => 0.500000,

      CLKOUT6_PHASE => 0.000000,

      CLKOUT6_USE_FINE_PS => false,

      COMPENSATION => "ZHOLD",

      DIVCLK_DIVIDE => 1,

      IS_CLKINSEL_INVERTED => '0',

      IS_PSEN_INVERTED => '0',

      IS_PSINCDEC_INVERTED => '0',

      IS_PWRDWN_INVERTED => '0',

      IS_RST_INVERTED => '0',

      REF_JITTER1 => 0.010000,

      REF_JITTER2 => 0.010000,

      SS_EN => "FALSE",

      SS_MODE => "CENTER_HIGH",

      SS_MOD_PERIOD => 10000,

      STARTUP_WAIT => false

    )

        port map (

      CLKFBIN => clkfbout_buf_clk_gen,

      CLKFBOUT => clkfbout_clk_gen,

      CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,

      CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,

      CLKIN1 => clk_in1_clk_gen,

      CLKIN2 => '0',

      CLKINSEL => '1',

      CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,

      CLKOUT0 => clk_out1_clk_gen,

      CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,

      CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,

      CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,

      CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,

      CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,

      CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,

      CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,

      CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,

      CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,

      CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,

      DADDR(6 downto 0) => B"0000000",

      DCLK => '0',

      DEN => '0',

      DI(15 downto 0) => B"0000000000000000",

      DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),

      DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,

      DWE => '0',

      LOCKED => locked,

      PSCLK => '0',

      PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,

      PSEN => '0',

      PSINCDEC => '0',

      PWRDWN => '0',

      RST => reset

    );

end STRUCTURE;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;

use UNISIM.VCOMPONENTS.ALL;

entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is

  port (

    clk_out1 : out STD_LOGIC;

    reset : in STD_LOGIC;

    locked : out STD_LOGIC;

    clk_in1_p : in STD_LOGIC;

    clk_in1_n : in STD_LOGIC

  );

  attribute NotValidForBitStream : boolean;

  attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;

end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;

architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is

begin

inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_gen_clk_wiz

     port map (

      clk_in1_n => clk_in1_n,

      clk_in1_p => clk_in1_p,

      clk_out1 => clk_out1,

      locked => locked,

      reset => reset

    );

end STRUCTURE;