Subversion Repositories aes-128-ecb-encoder

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// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:axi_uartlite:2.0

// IP Revision: 19

// The following must be inserted into your Verilog file for this

// core to be instantiated. Change the instance name and port connections

// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

axi_uartlite_module_sim your_instance_name (

  .s_axi_aclk(s_axi_aclk),        // input wire s_axi_aclk

  .s_axi_aresetn(s_axi_aresetn),  // input wire s_axi_aresetn

  .interrupt(interrupt),          // output wire interrupt

  .s_axi_awaddr(s_axi_awaddr),    // input wire [3 : 0] s_axi_awaddr

  .s_axi_awvalid(s_axi_awvalid),  // input wire s_axi_awvalid

  .s_axi_awready(s_axi_awready),  // output wire s_axi_awready

  .s_axi_wdata(s_axi_wdata),      // input wire [31 : 0] s_axi_wdata

  .s_axi_wstrb(s_axi_wstrb),      // input wire [3 : 0] s_axi_wstrb

  .s_axi_wvalid(s_axi_wvalid),    // input wire s_axi_wvalid

  .s_axi_wready(s_axi_wready),    // output wire s_axi_wready

  .s_axi_bresp(s_axi_bresp),      // output wire [1 : 0] s_axi_bresp

  .s_axi_bvalid(s_axi_bvalid),    // output wire s_axi_bvalid

  .s_axi_bready(s_axi_bready),    // input wire s_axi_bready

  .s_axi_araddr(s_axi_araddr),    // input wire [3 : 0] s_axi_araddr

  .s_axi_arvalid(s_axi_arvalid),  // input wire s_axi_arvalid

  .s_axi_arready(s_axi_arready),  // output wire s_axi_arready

  .s_axi_rdata(s_axi_rdata),      // output wire [31 : 0] s_axi_rdata

  .s_axi_rresp(s_axi_rresp),      // output wire [1 : 0] s_axi_rresp

  .s_axi_rvalid(s_axi_rvalid),    // output wire s_axi_rvalid

  .s_axi_rready(s_axi_rready),    // input wire s_axi_rready

  .rx(rx),                        // input wire rx

  .tx(tx)                        // output wire tx

);

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file axi_uartlite_module_sim.v when simulating

// the core, axi_uartlite_module_sim. When compiling the wrapper file, be sure to

// reference the Verilog simulation library.