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vv_gulyaev |
-- IPIF Common Library Package
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-------------------------------------------------------------------------------
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--
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-- *************************************************************************
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-- ** **
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-- ** DISCLAIMER OF LIABILITY **
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-- ** **
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-- ** This text/file contains proprietary, confidential **
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-- ** information of Xilinx, Inc., is distributed under **
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-- ** license from Xilinx, Inc., and may be used, copied **
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-- ** and/or disclosed only pursuant to the terms of a valid **
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-- ** license agreement with Xilinx, Inc. Xilinx hereby **
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-- ** grants you a license to use this text/file solely for **
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-- ** design, simulation, implementation and creation of **
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-- ** design files limited to Xilinx devices or technologies. **
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-- ** Use with non-Xilinx devices or technologies is expressly **
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-- ** prohibited and immediately terminates your license unless **
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-- ** covered by a separate agreement. **
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-- ** **
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-- ** Xilinx is providing this design, code, or information **
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-- ** "as-is" solely for use in developing programs and **
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-- ** solutions for Xilinx devices, with no obligation on the **
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-- ** part of Xilinx to provide support. By providing this design, **
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-- ** code, or information as one possible implementation of **
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-- ** this feature, application or standard, Xilinx is making no **
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-- ** representation that this implementation is free from any **
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-- ** claims of infringement. You are responsible for obtaining **
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-- ** any rights you may require for your implementation. **
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-- ** Xilinx expressly disclaims any warranty whatsoever with **
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-- ** respect to the adequacy of the implementation, including **
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-- ** but not limited to any warranties or representations that this **
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-- ** implementation is free from claims of infringement, implied **
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-- ** warranties of merchantability or fitness for a particular **
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-- ** purpose. **
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-- ** **
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-- ** Xilinx products are not intended for use in life support **
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-- ** appliances, devices, or systems. Use in such applications is **
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-- ** expressly prohibited. **
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-- ** **
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-- ** Any modifications that are made to the Source Code are **
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-- ** done at the user’s sole risk and will be unsupported. **
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-- ** The Xilinx Support Hotline does not have access to source **
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-- ** code and therefore cannot answer specific questions related **
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-- ** to source HDL. The Xilinx Hotline support of original source **
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-- ** code IP shall only address issues and questions related **
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-- ** to the standard Netlist version of the core (and thus **
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-- ** indirectly, the original core source). **
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-- ** **
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-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
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-- ** **
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-- ** This copyright and support notice must be retained as part **
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-- ** of this text at all times. **
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-- ** **
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-- *************************************************************************
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--
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-------------------------------------------------------------------------------
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-- Filename: ipif_pkg.vhd
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-- Version: Intital
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-- Description: This file contains the constants and functions used in the
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-- ipif common library components.
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--
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-------------------------------------------------------------------------------
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-- Structure:
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--
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-------------------------------------------------------------------------------
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-- Author: DET
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-- History:
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-- DET 02/21/02 -- Created from proc_common_pkg.vhd
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--
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-- DET 03/13/02 -- PLB IPIF development updates
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-- ^^^^^^
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-- - Commented out string types and string functions due to an XST
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-- problem with string arrays and functions. THe string array
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-- processing functions were replaced with comperable functions
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-- operating on integer arrays.
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-- ~~~~~~
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--
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--
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-- DET 4/30/2002 Initial
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-- ~~~~~~
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-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
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-- rebuild_int_array to support removal of unused elements from the
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-- ARD arrays.
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-- ^^^^^^ --
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--
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-- FLO 8/12/2002
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-- ~~~~~~
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-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
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-- and get_id_index_iboe.
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-- (Removed provisional functions bits_needed_for_vacancy,
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-- bits needed_for_occupancy, and bits_needed_for.)
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-- ^^^^^^
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--
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-- FLO 3/24/2003
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-- ~~~~~~
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-- - Added dependent property paramters for channelized DMA.
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-- - Added common property parameter array type.
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-- - Definded the KEYHOLD_BURST common-property parameter.
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-- ^^^^^^
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--
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-- FLO 10/22/2003
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-- ~~~~~~
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-- - Some adjustment to CHDMA parameterization.
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-- - Cleanup of obsolete code and comments. (The former "XST workaround"
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-- has become the officially deployed method.)
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-- ^^^^^^
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--
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-- LSS 03/24/2004
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-- ~~~~~~
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-- - Added 5 functions
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-- ^^^^^^
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--
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-- ALS 09/03/04
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-- ^^^^^^
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-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
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-- ~~~~~~
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--
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-- DET 1/17/2008 v4_0
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-- ~~~~~~
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-- - Changed proc_common library version to v4_0
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-- - Incorporated new disclaimer header
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-- ^^^^^^
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--
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-------------------------------------------------------------------------------
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-- Naming Conventions:
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-- active low signals: "*_n"
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-- clock signals: "clk", "clk_div#", "clk_#x"
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-- reset signals: "rst", "rst_n"
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-- generics: "C_*"
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-- user defined types: "*_TYPE"
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-- state machine next state: "*_ns"
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-- state machine current state: "*_cs"
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-- combinatorial signals: "*_com"
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-- pipelined or register delay signals: "*_d#"
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-- counter signals: "*cnt*"
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-- clock enable signals: "*_ce"
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-- internal version of output port "*_i"
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-- device pins: "*_pin"
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-- ports: - Names begin with Uppercase
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-- processes: "*_PROCESS"
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-- component instantiations: "<ENTITY_>I_<#|FUNC>
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-- need conversion function to convert reals/integers to std logic vectors
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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package ipif_pkg is
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-------------------------------------------------------------------------------
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-- Type Declarations
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-------------------------------------------------------------------------------
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type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
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subtype SLV64_TYPE is std_logic_vector(0 to 63);
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type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
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type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
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-------------------------------------------------------------------------------
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-- Function and Procedure Declarations
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-------------------------------------------------------------------------------
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function "=" (s1: in string; s2: in string) return boolean;
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function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
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function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
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function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
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index : integer) return integer;
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function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
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function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
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function S32 (in_string : string) return string;
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--------------------------------------------------------------------------------
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-- ARD support functions.
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-- These function can be useful when operating with the ARD parameterization.
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--------------------------------------------------------------------------------
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function get_id_index (id_array :INTEGER_ARRAY_TYPE;
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id : integer)
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return integer;
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function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
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id : integer)
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return integer;
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function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
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id : integer) return boolean;
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function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
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dwidth_array: INTEGER_ARRAY_TYPE;
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id : integer;
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default_i : integer)
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return integer;
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function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
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function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
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id : integer)
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return integer ;
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function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
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num_valid_pairs : integer)
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return SLV32_ARRAY_TYPE;
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function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
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num_valid_pairs : integer)
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return SLV64_ARRAY_TYPE;
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function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
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num_valid_entry : integer)
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return INTEGER_ARRAY_TYPE;
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-- 5 Functions Added 3/24/04
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function populate_intr_mode_array (num_user_intr : integer;
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intr_capture_mode : integer)
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return INTEGER_ARRAY_TYPE ;
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function add_intr_ard_id_array(include_intr : boolean;
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ard_id_array : INTEGER_ARRAY_TYPE)
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return INTEGER_ARRAY_TYPE;
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function add_intr_ard_addr_range_array(include_intr : boolean;
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ZERO_ADDR_PAD : std_logic_vector;
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intr_baseaddr : std_logic_vector;
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intr_highaddr : std_logic_vector;
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ard_id_array : INTEGER_ARRAY_TYPE;
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ard_addr_range_array : SLV64_ARRAY_TYPE)
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return SLV64_ARRAY_TYPE;
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function add_intr_ard_num_ce_array(include_intr : boolean;
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ard_id_array : INTEGER_ARRAY_TYPE;
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ard_num_ce_array : INTEGER_ARRAY_TYPE)
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return INTEGER_ARRAY_TYPE;
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function add_intr_ard_dwidth_array(include_intr : boolean;
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intr_dwidth : integer;
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ard_id_array : INTEGER_ARRAY_TYPE;
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ard_dwidth_array : INTEGER_ARRAY_TYPE)
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return INTEGER_ARRAY_TYPE;
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function log2(x : natural) return integer;
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function clog2(x : positive) return natural;
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-------------------------------------------------------------------------------
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-- Constant Declarations
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Channel Protocols
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-- The constant declarations below give symbolic-name aliases for values that
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-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
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-------------------------------------------------------------------------------
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constant XCL : integer := 0;
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constant DAG : integer := 1;
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--------------------------------------------------------------------------------
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-- Address range types.
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-- The constant declarations, below, give symbolic-name aliases for values
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-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
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-- gives aliases that are used to include IPIF services.
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--------------------------------------------------------------------------------
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-- IPIF module aliases
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Constant IPIF_INTR : integer := 1;
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Constant IPIF_RST : integer := 2;
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Constant IPIF_SESR_SEAR : integer := 3;
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Constant IPIF_DMA_SG : integer := 4;
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Constant IPIF_WRFIFO_REG : integer := 5;
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Constant IPIF_WRFIFO_DATA : integer := 6;
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Constant IPIF_RDFIFO_REG : integer := 7;
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Constant IPIF_RDFIFO_DATA : integer := 8;
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Constant IPIF_CHDMA_CHANNELS : integer := 9;
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Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
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Constant CHDMA_STATUS_FIFO : integer := 90;
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-- Some predefined user module aliases
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Constant USER_00 : integer := 100;
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Constant USER_01 : integer := 101;
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Constant USER_02 : integer := 102;
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Constant USER_03 : integer := 103;
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Constant USER_04 : integer := 104;
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Constant USER_05 : integer := 105;
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Constant USER_06 : integer := 106;
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Constant USER_07 : integer := 107;
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Constant USER_08 : integer := 108;
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Constant USER_09 : integer := 109;
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Constant USER_10 : integer := 110;
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Constant USER_11 : integer := 111;
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Constant USER_12 : integer := 112;
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Constant USER_13 : integer := 113;
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Constant USER_14 : integer := 114;
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Constant USER_15 : integer := 115;
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Constant USER_16 : integer := 116;
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---( Start of Dependent Properties declarations
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--------------------------------------------------------------------------------
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-- Declarations for Dependent Properties (properties that depend on the type of
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-- the address range, or in other words, address-range-specific parameters).
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-- There is one property, i.e. one parameter, encoded as an integer at
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-- each index of the properties array. There is one properties array for
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-- each address range.
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--
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-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
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-- a properties array and it is usually giving its (static) value using a
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-- VHDL aggregate construct. (--ToDo, give an example of this.)
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--
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-- The the "assigned" default value of a dependent property is zero. This value
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-- is usually specified the aggregate by leaving its (index) name out so that
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-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
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-- as noted in the definitions, below, have an "effective" default value that is
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-- different from the assigned default value of zero. In such cases, the
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-- function, eff_dp, given below, can be used to get the effective value of
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-- the dependent property.
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--------------------------------------------------------------------------------
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constant DEPENDENT_PROPS_SIZE : integer := 32;
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subtype DEPENDENT_PROPS_TYPE
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is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
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type DEPENDENT_PROPS_ARRAY_TYPE
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is array (natural range <>) of DEPENDENT_PROPS_TYPE;
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--------------------------------------------------------------------------------
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-- Below are the indices of dependent properties for the different types of
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-- address ranges.
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--
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-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
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-- for a set of address ranges. Then, e.g.,
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--
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-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
|
349 |
|
|
--
|
350 |
|
|
-- gives the fifo capacity in bits, provided that the i'th address range
|
351 |
|
|
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
|
352 |
|
|
--
|
353 |
|
|
-- These indices should be referenced only by the names below and never
|
354 |
|
|
-- by numerical literals. (The right to change numerical index assignments
|
355 |
|
|
-- is reserved; applications using the names will not be affected by such
|
356 |
|
|
-- reassignments.)
|
357 |
|
|
--------------------------------------------------------------------------------
|
358 |
|
|
--
|
359 |
|
|
--ToDo, if the interrupt controller parameterization is ever moved to
|
360 |
|
|
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
|
361 |
|
|
-- could be uncommented and used.
|
362 |
|
|
---- IPIF_INTR IDX
|
363 |
|
|
---------------------------------------------------------------------------- ---
|
364 |
|
|
constant EXCLUDE_DEV_ISC : integer := 0;
|
365 |
|
|
-- 1 specifies that only the global interrupt
|
366 |
|
|
-- enable is present in the device interrupt source
|
367 |
|
|
-- controller and that the only source of interrupts
|
368 |
|
|
-- in the device is the IP interrupt source controller.
|
369 |
|
|
-- 0 specifies that the full device interrupt
|
370 |
|
|
-- source controller structure will be included.
|
371 |
|
|
constant INCLUDE_DEV_PENCODER : integer := 1;
|
372 |
|
|
-- 1 will include the Device IID in the device interrupt
|
373 |
|
|
-- source controller, 0 will exclude it.
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
--
|
377 |
|
|
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
|
378 |
|
|
---------------------------------------------------------------------------- ---
|
379 |
|
|
constant FIFO_CAPACITY_BITS : integer := 0;
|
380 |
|
|
constant WR_WIDTH_BITS : integer := 1;
|
381 |
|
|
constant RD_WIDTH_BITS : integer := 2;
|
382 |
|
|
constant EXCLUDE_PACKET_MODE : integer := 3;
|
383 |
|
|
-- 1 Don't include packet mode features
|
384 |
|
|
-- 0 Include packet mode features
|
385 |
|
|
constant EXCLUDE_VACANCY : integer := 4;
|
386 |
|
|
-- 1 Don't include vacancy calculation
|
387 |
|
|
-- 0 Include vacancy calculation
|
388 |
|
|
-- See also the functions
|
389 |
|
|
-- bits_needed_for_vac and
|
390 |
|
|
-- bits_needed_for_occ that are declared below.
|
391 |
|
|
constant INCLUDE_DRE : integer := 5;
|
392 |
|
|
constant INCLUDE_AUTOPUSH_POP : integer := 6;
|
393 |
|
|
constant AUTOPUSH_POP_CE : integer := 7;
|
394 |
|
|
constant INCLUDE_CSUM : integer := 8;
|
395 |
|
|
--------------------------------------------------------------------------------
|
396 |
|
|
|
397 |
|
|
--
|
398 |
|
|
-- DMA_SG IDX
|
399 |
|
|
---------------------------------------------------------------------------- ---
|
400 |
|
|
--------------------------------------------------------------------------------
|
401 |
|
|
|
402 |
|
|
-- IPIF_CHDMA_CHANNELS IDX
|
403 |
|
|
---------------------------------------------------------------------------- ---
|
404 |
|
|
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
|
405 |
|
|
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
|
406 |
|
|
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
|
407 |
|
|
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
|
408 |
|
|
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
|
409 |
|
|
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
|
410 |
|
|
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
|
411 |
|
|
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
|
412 |
|
|
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
|
413 |
|
|
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
|
414 |
|
|
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
|
415 |
|
|
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
|
416 |
|
|
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
|
417 |
|
|
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
|
418 |
|
|
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
|
419 |
|
|
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
|
420 |
|
|
-- Gives the number of sub-channels for physical channel i.
|
421 |
|
|
--
|
422 |
|
|
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
|
423 |
|
|
-- below), have consecutive values starting with 0 for
|
424 |
|
|
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
|
425 |
|
|
-- names for use in the dependent-properties aggregates that parameterize
|
426 |
|
|
-- an IPIF_CHDMA_CHANNELS address range.)
|
427 |
|
|
--
|
428 |
|
|
-- [Users can ignore this note for developers
|
429 |
|
|
-- If the number of physical channels changes, both the
|
430 |
|
|
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
|
431 |
|
|
-- below, must be adjusted.
|
432 |
|
|
-- (Use of an array constant or a function of the form
|
433 |
|
|
-- NUM_SUBS_FOR_PHYS(i) to define the indices
|
434 |
|
|
-- runs afoul of LRM restrictions on non-locally static aggregate
|
435 |
|
|
-- choices. (Further, the LRM imposes perhaps unnecessarily
|
436 |
|
|
-- strict limits on what qualifies as a locally static primary.)
|
437 |
|
|
-- Note: This information is supplied for the benefit of anyone seeking
|
438 |
|
|
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
|
439 |
|
|
-- indices are defined.)
|
440 |
|
|
-- End of note for developers ]
|
441 |
|
|
--
|
442 |
|
|
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
|
443 |
|
|
-- dependent-properties array must be even since TX and RX channels
|
444 |
|
|
-- come in pairs with the TX followed immediately by
|
445 |
|
|
-- the corresponding RX.
|
446 |
|
|
--
|
447 |
|
|
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
|
448 |
|
|
-- The number of simple DMA channels.
|
449 |
|
|
constant NUM_SIMPLE_SG_CHANS : integer :=17;
|
450 |
|
|
-- The number of simple SG channels.
|
451 |
|
|
constant INTR_COALESCE : integer :=18;
|
452 |
|
|
-- 0 Interrupt coalescing is disabled
|
453 |
|
|
-- 1 Interrupt coalescing is enabled
|
454 |
|
|
constant CLK_PERIOD_PS : integer :=19;
|
455 |
|
|
-- The period of the OPB Bus clock in ps.
|
456 |
|
|
-- The default value of 0 is a special value that
|
457 |
|
|
-- is synonymous with 10000 ps (10 ns).
|
458 |
|
|
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
|
459 |
|
|
constant PACKET_WAIT_UNIT_NS : integer :=20;
|
460 |
|
|
-- Gives the unit for used for timing of pack-wait bounds.
|
461 |
|
|
-- The default value of 0 is a special value that
|
462 |
|
|
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
|
463 |
|
|
-- value is typically only used for testing.
|
464 |
|
|
-- Relevant only if (INTR_COALESCE = 1).
|
465 |
|
|
constant BURST_SIZE : integer :=21;
|
466 |
|
|
-- 1, 2, 4, 8 or 16
|
467 |
|
|
-- The default value of 0 is a special value that
|
468 |
|
|
-- is synonymous with a burst size of 16.
|
469 |
|
|
-- Setting the BURST_SIZE to 1 effectively disables
|
470 |
|
|
-- bursts.
|
471 |
|
|
constant REMAINDER_AS_SINGLES : integer :=22;
|
472 |
|
|
-- 0 Remainder handled as a short burst
|
473 |
|
|
-- 1 Remainder handled as a series of singles
|
474 |
|
|
|
475 |
|
|
--------------------------------------------------------------------------------
|
476 |
|
|
-- The constant below is not the index of a dependent-properties
|
477 |
|
|
-- parameter (and, as such, would never appear as a choice in a
|
478 |
|
|
-- dependent-properties aggregate). Rather, it is fixed to the maximum
|
479 |
|
|
-- number of physical channels that an Address Range of type
|
480 |
|
|
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
|
481 |
|
|
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
|
482 |
|
|
--------------------------------------------------------------------------------
|
483 |
|
|
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
|
484 |
|
|
|
485 |
|
|
|
486 |
|
|
--------------------------------------------------------------------------
|
487 |
|
|
-- EXAMPLE: Here is an example dependent-properties aggregate for an
|
488 |
|
|
-- address range of type IPIF_CHDMA_CHANNELS.
|
489 |
|
|
-- To have a compact list of all of the CHDMA parameters, all are
|
490 |
|
|
-- shown, however three are commented out and the unneeded
|
491 |
|
|
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
|
492 |
|
|
-- gives these parameters their default values, such that, for the example
|
493 |
|
|
--
|
494 |
|
|
-- - All physical channels above 2 have zero subchannels (effectively,
|
495 |
|
|
-- these physical channels are not used)
|
496 |
|
|
-- - There are no simple SG channels
|
497 |
|
|
-- - The packet-wait time unit is 1 ms
|
498 |
|
|
-- - Burst size is 16
|
499 |
|
|
--------------------------------------------------------------------------
|
500 |
|
|
-- (
|
501 |
|
|
-- NUM_SUBS_FOR_PHYS_0 => 8,
|
502 |
|
|
-- NUM_SUBS_FOR_PHYS_1 => 4,
|
503 |
|
|
-- NUM_SUBS_FOR_PHYS_2 => 14,
|
504 |
|
|
-- NUM_SIMPLE_DMA_CHANS => 1,
|
505 |
|
|
-- --NUM_SIMPLE_SG_CHANS => 5,
|
506 |
|
|
-- INTR_COALESCE => 1,
|
507 |
|
|
-- CLK_PERIOD_PS => 20000,
|
508 |
|
|
-- --PACKET_WAIT_UNIT_NS => 50000,
|
509 |
|
|
-- --BURST_SIZE => 1,
|
510 |
|
|
-- REMAINDER_AS_SINGLES => 1,
|
511 |
|
|
-- OTHERS => 0
|
512 |
|
|
-- )
|
513 |
|
|
--
|
514 |
|
|
--------------------------------------------------------------------------------
|
515 |
|
|
|
516 |
|
|
--------------------------------------------------------------------------------
|
517 |
|
|
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
|
518 |
|
|
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
|
519 |
|
|
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
|
520 |
|
|
-- without making reference to dependent_props.
|
521 |
|
|
--------------------------------------------------------------------------------
|
522 |
|
|
function bits_needed_for_vac(
|
523 |
|
|
fifo_present: boolean;
|
524 |
|
|
dependent_props : DEPENDENT_PROPS_TYPE
|
525 |
|
|
) return integer;
|
526 |
|
|
|
527 |
|
|
--------------------------------------------------------------------------------
|
528 |
|
|
-- Calculates the number of bits needed to convey the occupancy (fullness) of
|
529 |
|
|
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
|
530 |
|
|
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
|
531 |
|
|
-- without making reference to dependent_props.
|
532 |
|
|
--------------------------------------------------------------------------------
|
533 |
|
|
function bits_needed_for_occ(
|
534 |
|
|
fifo_present: boolean;
|
535 |
|
|
dependent_props : DEPENDENT_PROPS_TYPE
|
536 |
|
|
) return integer;
|
537 |
|
|
|
538 |
|
|
--------------------------------------------------------------------------------
|
539 |
|
|
-- Function eff_dp.
|
540 |
|
|
--
|
541 |
|
|
-- For some of the dependent properties, the default value of zero is meant
|
542 |
|
|
-- to imply an effective default value of other than zero (see e.g.
|
543 |
|
|
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
|
544 |
|
|
-- following function is used to get the (possibly default-adjusted)
|
545 |
|
|
-- value for a dependent property.
|
546 |
|
|
--
|
547 |
|
|
-- Example call:
|
548 |
|
|
--
|
549 |
|
|
-- eff_value_of_param :=
|
550 |
|
|
-- eff_dp(
|
551 |
|
|
-- C_IPIF_CHDMA_CHANNELS,
|
552 |
|
|
-- PACKET_WAIT_UNIT_NS,
|
553 |
|
|
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
|
554 |
|
|
-- );
|
555 |
|
|
--
|
556 |
|
|
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
|
557 |
|
|
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
|
558 |
|
|
-- type C_IPIF_CHDMA_CHANNELS.
|
559 |
|
|
--------------------------------------------------------------------------------
|
560 |
|
|
function eff_dp(id : integer; -- The type of address range.
|
561 |
|
|
dep_prop : integer; -- The index of the dependent prop.
|
562 |
|
|
value : integer -- The value at that index.
|
563 |
|
|
) return integer; -- The effective value, possibly adjusted
|
564 |
|
|
-- if value has the default value of 0.
|
565 |
|
|
|
566 |
|
|
---) End of Dependent Properties declarations
|
567 |
|
|
|
568 |
|
|
|
569 |
|
|
--------------------------------------------------------------------------------
|
570 |
|
|
-- Declarations for Common Properties (properties that apply regardless of the
|
571 |
|
|
-- type of the address range). Structurally, these work the same as
|
572 |
|
|
-- the dependent properties.
|
573 |
|
|
--------------------------------------------------------------------------------
|
574 |
|
|
|
575 |
|
|
constant COMMON_PROPS_SIZE : integer := 2;
|
576 |
|
|
|
577 |
|
|
subtype COMMON_PROPS_TYPE
|
578 |
|
|
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
|
579 |
|
|
|
580 |
|
|
type COMMON_PROPS_ARRAY_TYPE
|
581 |
|
|
is array (natural range <>) of COMMON_PROPS_TYPE;
|
582 |
|
|
|
583 |
|
|
--------------------------------------------------------------------------------
|
584 |
|
|
-- Below are the indices of the common properties.
|
585 |
|
|
--
|
586 |
|
|
-- These indices should be referenced only by the names below and never
|
587 |
|
|
-- by numerical literals.
|
588 |
|
|
-- IDX
|
589 |
|
|
---------------------------------------------------------------------------- ---
|
590 |
|
|
constant KEYHOLE_BURST : integer := 0;
|
591 |
|
|
-- 1 All addresses of a burst are forced to the initial
|
592 |
|
|
-- address of the burst.
|
593 |
|
|
-- 0 Burst addresses follow the bus protocol.
|
594 |
|
|
|
595 |
|
|
|
596 |
|
|
|
597 |
|
|
|
598 |
|
|
-- IP interrupt mode array constants
|
599 |
|
|
Constant INTR_PASS_THRU : integer := 1;
|
600 |
|
|
Constant INTR_PASS_THRU_INV : integer := 2;
|
601 |
|
|
Constant INTR_REG_EVENT : integer := 3;
|
602 |
|
|
Constant INTR_REG_EVENT_INV : integer := 4;
|
603 |
|
|
Constant INTR_POS_EDGE_DETECT : integer := 5;
|
604 |
|
|
Constant INTR_NEG_EDGE_DETECT : integer := 6;
|
605 |
|
|
|
606 |
|
|
|
607 |
|
|
|
608 |
|
|
|
609 |
|
|
|
610 |
|
|
end ipif_pkg;
|
611 |
|
|
|
612 |
|
|
|
613 |
|
|
|
614 |
|
|
|
615 |
|
|
package body ipif_pkg is
|
616 |
|
|
|
617 |
|
|
-------------------------------------------------------------------------------
|
618 |
|
|
-- Function log2 -- returns number of bits needed to encode x choices
|
619 |
|
|
-- x = 0 returns 0
|
620 |
|
|
-- x = 1 returns 0
|
621 |
|
|
-- x = 2 returns 1
|
622 |
|
|
-- x = 4 returns 2, etc.
|
623 |
|
|
-------------------------------------------------------------------------------
|
624 |
|
|
--
|
625 |
|
|
function log2(x : natural) return integer is
|
626 |
|
|
variable i : integer := 0;
|
627 |
|
|
variable val: integer := 1;
|
628 |
|
|
begin
|
629 |
|
|
if x = 0 then return 0;
|
630 |
|
|
else
|
631 |
|
|
for j in 0 to 29 loop -- for loop for XST
|
632 |
|
|
if val >= x then null;
|
633 |
|
|
else
|
634 |
|
|
i := i+1;
|
635 |
|
|
val := val*2;
|
636 |
|
|
end if;
|
637 |
|
|
end loop;
|
638 |
|
|
-- Fix per CR520627 XST was ignoring this anyway and printing a
|
639 |
|
|
-- Warning in SRP file. This will get rid of the warning and not
|
640 |
|
|
-- impact simulation.
|
641 |
|
|
-- synthesis translate_off
|
642 |
|
|
assert val >= x
|
643 |
|
|
report "Function log2 received argument larger" &
|
644 |
|
|
" than its capability of 2^30. "
|
645 |
|
|
severity failure;
|
646 |
|
|
-- synthesis translate_on
|
647 |
|
|
return i;
|
648 |
|
|
end if;
|
649 |
|
|
end function log2;
|
650 |
|
|
|
651 |
|
|
|
652 |
|
|
|
653 |
|
|
--------------------------------------------------------------------------------
|
654 |
|
|
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
|
655 |
|
|
-- i.e., the least integer greater than or equal to log2(x).
|
656 |
|
|
--------------------------------------------------------------------------------
|
657 |
|
|
function clog2(x : positive) return natural is
|
658 |
|
|
variable r : natural := 0;
|
659 |
|
|
variable rp : natural := 1; -- rp tracks the value 2**r
|
660 |
|
|
begin
|
661 |
|
|
while rp < x loop -- Termination condition T: x <= 2**r
|
662 |
|
|
-- Loop invariant L: 2**(r-1) < x
|
663 |
|
|
r := r + 1;
|
664 |
|
|
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
|
665 |
|
|
-- the integer range, the doubled value would exceed x, so safe to exit.
|
666 |
|
|
rp := rp + rp;
|
667 |
|
|
end loop;
|
668 |
|
|
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
|
669 |
|
|
return r; --
|
670 |
|
|
end clog2;
|
671 |
|
|
|
672 |
|
|
|
673 |
|
|
-------------------------------------------------------------------------------
|
674 |
|
|
-- Function Definitions
|
675 |
|
|
-------------------------------------------------------------------------------
|
676 |
|
|
|
677 |
|
|
|
678 |
|
|
-----------------------------------------------------------------------------
|
679 |
|
|
-- Function "="
|
680 |
|
|
--
|
681 |
|
|
-- This function can be used to overload the "=" operator when comparing
|
682 |
|
|
-- strings.
|
683 |
|
|
-----------------------------------------------------------------------------
|
684 |
|
|
function "=" (s1: in string; s2: in string) return boolean is
|
685 |
|
|
constant tc: character := ' '; -- string termination character
|
686 |
|
|
variable i: integer := 1;
|
687 |
|
|
variable v1 : string(1 to s1'length) := s1;
|
688 |
|
|
variable v2 : string(1 to s2'length) := s2;
|
689 |
|
|
begin
|
690 |
|
|
while (i <= v1'length) and (v1(i) /= tc) and
|
691 |
|
|
(i <= v2'length) and (v2(i) /= tc) and
|
692 |
|
|
(v1(i) = v2(i))
|
693 |
|
|
loop
|
694 |
|
|
i := i+1;
|
695 |
|
|
end loop;
|
696 |
|
|
return ((i > v1'length) or (v1(i) = tc)) and
|
697 |
|
|
((i > v2'length) or (v2(i) = tc));
|
698 |
|
|
end;
|
699 |
|
|
|
700 |
|
|
|
701 |
|
|
|
702 |
|
|
|
703 |
|
|
----------------------------------------------------------------------------
|
704 |
|
|
-- Function equaluseCase
|
705 |
|
|
--
|
706 |
|
|
-- This function returns true if case sensitive string comparison determines
|
707 |
|
|
-- that str1 and str2 are the same.
|
708 |
|
|
-----------------------------------------------------------------------------
|
709 |
|
|
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
|
710 |
|
|
CONSTANT len1 : INTEGER := str1'length;
|
711 |
|
|
CONSTANT len2 : INTEGER := str2'length;
|
712 |
|
|
VARIABLE equal : BOOLEAN := TRUE;
|
713 |
|
|
BEGIN
|
714 |
|
|
IF NOT (len1=len2) THEN
|
715 |
|
|
equal := FALSE;
|
716 |
|
|
ELSE
|
717 |
|
|
FOR i IN str1'range LOOP
|
718 |
|
|
IF NOT (str1(i) = str2(i)) THEN
|
719 |
|
|
equal := FALSE;
|
720 |
|
|
END IF;
|
721 |
|
|
END LOOP;
|
722 |
|
|
END IF;
|
723 |
|
|
|
724 |
|
|
RETURN equal;
|
725 |
|
|
END equaluseCase;
|
726 |
|
|
|
727 |
|
|
|
728 |
|
|
-----------------------------------------------------------------------------
|
729 |
|
|
-- Function calc_num_ce
|
730 |
|
|
--
|
731 |
|
|
-- This function is used to process the array specifying the number of Chip
|
732 |
|
|
-- Enables required for a Base Address specification. The array is input to
|
733 |
|
|
-- the function and an integer is returned reflecting the total number of
|
734 |
|
|
-- Chip Enables required for the CE, RdCE, and WrCE Buses
|
735 |
|
|
-----------------------------------------------------------------------------
|
736 |
|
|
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
|
737 |
|
|
|
738 |
|
|
Variable ce_num_sum : integer := 0;
|
739 |
|
|
|
740 |
|
|
begin
|
741 |
|
|
|
742 |
|
|
for i in 0 to (ce_num_array'length)-1 loop
|
743 |
|
|
ce_num_sum := ce_num_sum + ce_num_array(i);
|
744 |
|
|
End loop;
|
745 |
|
|
|
746 |
|
|
return(ce_num_sum);
|
747 |
|
|
|
748 |
|
|
end function calc_num_ce;
|
749 |
|
|
|
750 |
|
|
|
751 |
|
|
-----------------------------------------------------------------------------
|
752 |
|
|
-- Function calc_start_ce_index
|
753 |
|
|
--
|
754 |
|
|
-- This function is used to process the array specifying the number of Chip
|
755 |
|
|
-- Enables required for a Base Address specification. The CE Size array is
|
756 |
|
|
-- input to the function and an integer index representing the index of the
|
757 |
|
|
-- target module in the ce_num_array. An integer is returned reflecting the
|
758 |
|
|
-- starting index of the assigned Chip Enables within the CE, RdCE, and
|
759 |
|
|
-- WrCE Buses.
|
760 |
|
|
-----------------------------------------------------------------------------
|
761 |
|
|
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
|
762 |
|
|
index : integer) return integer is
|
763 |
|
|
|
764 |
|
|
Variable ce_num_sum : integer := 0;
|
765 |
|
|
|
766 |
|
|
begin
|
767 |
|
|
If (index = 0) Then
|
768 |
|
|
ce_num_sum := 0;
|
769 |
|
|
else
|
770 |
|
|
for i in 0 to index-1 loop
|
771 |
|
|
ce_num_sum := ce_num_sum + ce_num_array(i);
|
772 |
|
|
End loop;
|
773 |
|
|
End if;
|
774 |
|
|
|
775 |
|
|
return(ce_num_sum);
|
776 |
|
|
|
777 |
|
|
end function calc_start_ce_index;
|
778 |
|
|
|
779 |
|
|
|
780 |
|
|
-----------------------------------------------------------------------------
|
781 |
|
|
-- Function get_min_dwidth
|
782 |
|
|
--
|
783 |
|
|
-- This function is used to process the array specifying the data bus width
|
784 |
|
|
-- for each of the target modules. The dwidth_array is input to the function
|
785 |
|
|
-- and an integer is returned that is the smallest value found of all the
|
786 |
|
|
-- entries in the array.
|
787 |
|
|
-----------------------------------------------------------------------------
|
788 |
|
|
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
|
789 |
|
|
|
790 |
|
|
Variable temp_min : Integer := 1024;
|
791 |
|
|
|
792 |
|
|
begin
|
793 |
|
|
|
794 |
|
|
for i in 0 to dwidth_array'length-1 loop
|
795 |
|
|
|
796 |
|
|
If (dwidth_array(i) < temp_min) Then
|
797 |
|
|
temp_min := dwidth_array(i);
|
798 |
|
|
else
|
799 |
|
|
null;
|
800 |
|
|
End if;
|
801 |
|
|
|
802 |
|
|
End loop;
|
803 |
|
|
|
804 |
|
|
return(temp_min);
|
805 |
|
|
|
806 |
|
|
end function get_min_dwidth;
|
807 |
|
|
|
808 |
|
|
|
809 |
|
|
|
810 |
|
|
-----------------------------------------------------------------------------
|
811 |
|
|
-- Function get_max_dwidth
|
812 |
|
|
--
|
813 |
|
|
-- This function is used to process the array specifying the data bus width
|
814 |
|
|
-- for each of the target modules. The dwidth_array is input to the function
|
815 |
|
|
-- and an integer is returned that is the largest value found of all the
|
816 |
|
|
-- entries in the array.
|
817 |
|
|
-----------------------------------------------------------------------------
|
818 |
|
|
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
|
819 |
|
|
|
820 |
|
|
Variable temp_max : Integer := 0;
|
821 |
|
|
|
822 |
|
|
begin
|
823 |
|
|
|
824 |
|
|
for i in 0 to dwidth_array'length-1 loop
|
825 |
|
|
|
826 |
|
|
If (dwidth_array(i) > temp_max) Then
|
827 |
|
|
temp_max := dwidth_array(i);
|
828 |
|
|
else
|
829 |
|
|
null;
|
830 |
|
|
End if;
|
831 |
|
|
|
832 |
|
|
End loop;
|
833 |
|
|
|
834 |
|
|
return(temp_max);
|
835 |
|
|
|
836 |
|
|
end function get_max_dwidth;
|
837 |
|
|
|
838 |
|
|
|
839 |
|
|
|
840 |
|
|
-----------------------------------------------------------------------------
|
841 |
|
|
-- Function S32
|
842 |
|
|
--
|
843 |
|
|
-- This function is used to expand an input string to 32 characters by
|
844 |
|
|
-- padding with spaces. If the input string is larger than 32 characters,
|
845 |
|
|
-- it will truncate to 32 characters.
|
846 |
|
|
-----------------------------------------------------------------------------
|
847 |
|
|
function S32 (in_string : string) return string is
|
848 |
|
|
|
849 |
|
|
constant OUTPUT_STRING_LENGTH : integer := 32;
|
850 |
|
|
Constant space : character := ' ';
|
851 |
|
|
|
852 |
|
|
variable new_string : string(1 to 32);
|
853 |
|
|
Variable start_index : Integer := in_string'length+1;
|
854 |
|
|
|
855 |
|
|
begin
|
856 |
|
|
|
857 |
|
|
If (in_string'length < OUTPUT_STRING_LENGTH) Then
|
858 |
|
|
|
859 |
|
|
for i in 1 to in_string'length loop
|
860 |
|
|
new_string(i) := in_string(i);
|
861 |
|
|
End loop;
|
862 |
|
|
|
863 |
|
|
for j in start_index to OUTPUT_STRING_LENGTH loop
|
864 |
|
|
new_string(j) := space;
|
865 |
|
|
End loop;
|
866 |
|
|
|
867 |
|
|
|
868 |
|
|
else -- use first 32 chars of in_string (truncate the rest)
|
869 |
|
|
|
870 |
|
|
for k in 1 to OUTPUT_STRING_LENGTH loop
|
871 |
|
|
new_string(k) := in_string(k);
|
872 |
|
|
End loop;
|
873 |
|
|
|
874 |
|
|
End if;
|
875 |
|
|
|
876 |
|
|
return(new_string);
|
877 |
|
|
|
878 |
|
|
end function S32;
|
879 |
|
|
|
880 |
|
|
|
881 |
|
|
-----------------------------------------------------------------------------
|
882 |
|
|
-- Function get_id_index
|
883 |
|
|
--
|
884 |
|
|
-- This function is used to process the array specifying the target function
|
885 |
|
|
-- assigned to a Base Address pair address range. The id_array and a
|
886 |
|
|
-- id number is input to the function. A integer is returned reflecting the
|
887 |
|
|
-- array index of the id matching the id input number. This function
|
888 |
|
|
-- should only be called if the id number is known to exist in the
|
889 |
|
|
-- name_array input. This can be detirmined by using the find_ard_id
|
890 |
|
|
-- function.
|
891 |
|
|
-----------------------------------------------------------------------------
|
892 |
|
|
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
|
893 |
|
|
id : integer) return integer is
|
894 |
|
|
|
895 |
|
|
Variable match : Boolean := false;
|
896 |
|
|
Variable match_index : Integer := 10000; -- a really big number!
|
897 |
|
|
|
898 |
|
|
|
899 |
|
|
begin
|
900 |
|
|
|
901 |
|
|
for array_index in 0 to id_array'length-1 loop
|
902 |
|
|
|
903 |
|
|
|
904 |
|
|
If (match = true) Then -- match already found so do nothing
|
905 |
|
|
|
906 |
|
|
null;
|
907 |
|
|
|
908 |
|
|
else -- compare the numbers one by one
|
909 |
|
|
|
910 |
|
|
match := (id_array(array_index) = id);
|
911 |
|
|
|
912 |
|
|
If (match) Then
|
913 |
|
|
match_index := array_index;
|
914 |
|
|
else
|
915 |
|
|
null;
|
916 |
|
|
End if;
|
917 |
|
|
|
918 |
|
|
End if;
|
919 |
|
|
|
920 |
|
|
End loop;
|
921 |
|
|
|
922 |
|
|
return(match_index);
|
923 |
|
|
|
924 |
|
|
end function get_id_index;
|
925 |
|
|
|
926 |
|
|
|
927 |
|
|
--------------------------------------------------------------------------------
|
928 |
|
|
-- get_id_index but return a value in bounds on error (iboe).
|
929 |
|
|
--
|
930 |
|
|
-- This function is the same as get_id_index, except that when id does
|
931 |
|
|
-- not exist in id_array, the value returned is any index that is
|
932 |
|
|
-- within the index range of id_array.
|
933 |
|
|
--
|
934 |
|
|
-- This function would normally only be used where function find_ard_id
|
935 |
|
|
-- is used to establish the existence of id but, even when non-existent,
|
936 |
|
|
-- an element of one of the ARD arrays will be computed from the
|
937 |
|
|
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
|
938 |
|
|
-- and the example call, below
|
939 |
|
|
--
|
940 |
|
|
-- bits_needed_for_vac(
|
941 |
|
|
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
|
942 |
|
|
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
|
943 |
|
|
-- IPIF_RDFIFO_DATA))
|
944 |
|
|
-- )
|
945 |
|
|
--------------------------------------------------------------------------------
|
946 |
|
|
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
|
947 |
|
|
id : integer) return integer is
|
948 |
|
|
|
949 |
|
|
Variable match : Boolean := false;
|
950 |
|
|
Variable match_index : Integer := id_array'left; -- any valid array index
|
951 |
|
|
|
952 |
|
|
begin
|
953 |
|
|
for array_index in 0 to id_array'length-1 loop
|
954 |
|
|
If (match = true) Then -- match already found so do nothing
|
955 |
|
|
null;
|
956 |
|
|
else -- compare the numbers one by one
|
957 |
|
|
match := (id_array(array_index) = id);
|
958 |
|
|
If (match) Then match_index := array_index;
|
959 |
|
|
else null;
|
960 |
|
|
End if;
|
961 |
|
|
End if;
|
962 |
|
|
End loop;
|
963 |
|
|
return(match_index);
|
964 |
|
|
end function get_id_index_iboe;
|
965 |
|
|
|
966 |
|
|
|
967 |
|
|
-----------------------------------------------------------------------------
|
968 |
|
|
-- Function find_ard_id
|
969 |
|
|
--
|
970 |
|
|
-- This function is used to process the array specifying the target function
|
971 |
|
|
-- assigned to a Base Address pair address range. The id_array and a
|
972 |
|
|
-- integer id is input to the function. A boolean is returned reflecting the
|
973 |
|
|
-- presence (or not) of a number in the array matching the id input number.
|
974 |
|
|
-----------------------------------------------------------------------------
|
975 |
|
|
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
|
976 |
|
|
id : integer) return boolean is
|
977 |
|
|
|
978 |
|
|
Variable match : Boolean := false;
|
979 |
|
|
|
980 |
|
|
begin
|
981 |
|
|
|
982 |
|
|
for array_index in 0 to id_array'length-1 loop
|
983 |
|
|
|
984 |
|
|
|
985 |
|
|
If (match = true) Then -- match already found so do nothing
|
986 |
|
|
|
987 |
|
|
null;
|
988 |
|
|
|
989 |
|
|
else -- compare the numbers one by one
|
990 |
|
|
|
991 |
|
|
match := (id_array(array_index) = id);
|
992 |
|
|
|
993 |
|
|
End if;
|
994 |
|
|
|
995 |
|
|
End loop;
|
996 |
|
|
|
997 |
|
|
return(match);
|
998 |
|
|
|
999 |
|
|
end function find_ard_id;
|
1000 |
|
|
|
1001 |
|
|
|
1002 |
|
|
-----------------------------------------------------------------------------
|
1003 |
|
|
-- Function find_id_dwidth
|
1004 |
|
|
--
|
1005 |
|
|
-- This function is used to find the data width of a target module. If the
|
1006 |
|
|
-- target module exists, the data width is extracted from the input dwidth
|
1007 |
|
|
-- array. If the module is not in the ID array, the default input is
|
1008 |
|
|
-- returned. This function is needed to assign data port size constraints on
|
1009 |
|
|
-- unconstrained port widths.
|
1010 |
|
|
-----------------------------------------------------------------------------
|
1011 |
|
|
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
|
1012 |
|
|
dwidth_array: INTEGER_ARRAY_TYPE;
|
1013 |
|
|
id : integer;
|
1014 |
|
|
default_i : integer) return integer is
|
1015 |
|
|
|
1016 |
|
|
|
1017 |
|
|
Variable id_present : Boolean := false;
|
1018 |
|
|
Variable array_index : Integer := 0;
|
1019 |
|
|
Variable dwidth : Integer := default_i;
|
1020 |
|
|
|
1021 |
|
|
begin
|
1022 |
|
|
|
1023 |
|
|
id_present := find_ard_id(id_array, id);
|
1024 |
|
|
|
1025 |
|
|
If (id_present) Then
|
1026 |
|
|
array_index := get_id_index (id_array, id);
|
1027 |
|
|
dwidth := dwidth_array(array_index);
|
1028 |
|
|
else
|
1029 |
|
|
null; -- use default input
|
1030 |
|
|
End if;
|
1031 |
|
|
|
1032 |
|
|
|
1033 |
|
|
Return (dwidth);
|
1034 |
|
|
|
1035 |
|
|
end function find_id_dwidth;
|
1036 |
|
|
|
1037 |
|
|
|
1038 |
|
|
|
1039 |
|
|
|
1040 |
|
|
|
1041 |
|
|
-----------------------------------------------------------------------------
|
1042 |
|
|
-- Function cnt_ipif_id_blks
|
1043 |
|
|
--
|
1044 |
|
|
-- This function is used to detirmine the number of IPIF components specified
|
1045 |
|
|
-- in the ARD ID Array. An integer is returned representing the number
|
1046 |
|
|
-- of elements counted. User IDs are ignored in the counting process.
|
1047 |
|
|
-----------------------------------------------------------------------------
|
1048 |
|
|
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
|
1049 |
|
|
return integer is
|
1050 |
|
|
|
1051 |
|
|
Variable blk_count : integer := 0;
|
1052 |
|
|
Variable temp_id : integer;
|
1053 |
|
|
|
1054 |
|
|
begin
|
1055 |
|
|
|
1056 |
|
|
for array_index in 0 to id_array'length-1 loop
|
1057 |
|
|
|
1058 |
|
|
temp_id := id_array(array_index);
|
1059 |
|
|
|
1060 |
|
|
If (temp_id = IPIF_WRFIFO_DATA or
|
1061 |
|
|
temp_id = IPIF_RDFIFO_DATA or
|
1062 |
|
|
temp_id = IPIF_RST or
|
1063 |
|
|
temp_id = IPIF_INTR or
|
1064 |
|
|
temp_id = IPIF_DMA_SG or
|
1065 |
|
|
temp_id = IPIF_SESR_SEAR
|
1066 |
|
|
) Then -- IPIF block found
|
1067 |
|
|
|
1068 |
|
|
blk_count := blk_count+1;
|
1069 |
|
|
|
1070 |
|
|
else -- go to next loop iteration
|
1071 |
|
|
|
1072 |
|
|
null;
|
1073 |
|
|
|
1074 |
|
|
End if;
|
1075 |
|
|
|
1076 |
|
|
End loop;
|
1077 |
|
|
|
1078 |
|
|
return(blk_count);
|
1079 |
|
|
|
1080 |
|
|
end function cnt_ipif_id_blks;
|
1081 |
|
|
|
1082 |
|
|
|
1083 |
|
|
|
1084 |
|
|
-----------------------------------------------------------------------------
|
1085 |
|
|
-- Function get_ipif_id_dbus_index
|
1086 |
|
|
--
|
1087 |
|
|
-- This function is used to detirmine the IPIF relative index of a given
|
1088 |
|
|
-- ID value. User IDs are ignored in the index detirmination.
|
1089 |
|
|
-----------------------------------------------------------------------------
|
1090 |
|
|
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
|
1091 |
|
|
id : integer)
|
1092 |
|
|
return integer is
|
1093 |
|
|
|
1094 |
|
|
Variable blk_index : integer := 0;
|
1095 |
|
|
Variable temp_id : integer;
|
1096 |
|
|
Variable id_found : Boolean := false;
|
1097 |
|
|
|
1098 |
|
|
begin
|
1099 |
|
|
|
1100 |
|
|
for array_index in 0 to id_array'length-1 loop
|
1101 |
|
|
|
1102 |
|
|
temp_id := id_array(array_index);
|
1103 |
|
|
|
1104 |
|
|
If (id_found) then
|
1105 |
|
|
|
1106 |
|
|
null;
|
1107 |
|
|
|
1108 |
|
|
elsif (temp_id = id) then
|
1109 |
|
|
|
1110 |
|
|
id_found := true;
|
1111 |
|
|
|
1112 |
|
|
elsif (temp_id = IPIF_WRFIFO_DATA or
|
1113 |
|
|
temp_id = IPIF_RDFIFO_DATA or
|
1114 |
|
|
temp_id = IPIF_RST or
|
1115 |
|
|
temp_id = IPIF_INTR or
|
1116 |
|
|
temp_id = IPIF_DMA_SG or
|
1117 |
|
|
temp_id = IPIF_SESR_SEAR
|
1118 |
|
|
) Then -- IPIF block found
|
1119 |
|
|
|
1120 |
|
|
blk_index := blk_index+1;
|
1121 |
|
|
|
1122 |
|
|
else -- user block so do nothing
|
1123 |
|
|
|
1124 |
|
|
null;
|
1125 |
|
|
|
1126 |
|
|
End if;
|
1127 |
|
|
|
1128 |
|
|
End loop;
|
1129 |
|
|
|
1130 |
|
|
return(blk_index);
|
1131 |
|
|
|
1132 |
|
|
|
1133 |
|
|
end function get_ipif_id_dbus_index;
|
1134 |
|
|
|
1135 |
|
|
|
1136 |
|
|
|
1137 |
|
|
------------------------------------------------------------------------------
|
1138 |
|
|
-- Function: rebuild_slv32_array
|
1139 |
|
|
--
|
1140 |
|
|
-- Description:
|
1141 |
|
|
-- This function takes an input slv32 array and rebuilds an output slv32
|
1142 |
|
|
-- array composed of the first "num_valid_entry" elements from the input
|
1143 |
|
|
-- array.
|
1144 |
|
|
------------------------------------------------------------------------------
|
1145 |
|
|
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
|
1146 |
|
|
num_valid_pairs : integer)
|
1147 |
|
|
return SLV32_ARRAY_TYPE is
|
1148 |
|
|
|
1149 |
|
|
--Constants
|
1150 |
|
|
constant num_elements : Integer := num_valid_pairs * 2;
|
1151 |
|
|
|
1152 |
|
|
-- Variables
|
1153 |
|
|
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
|
1154 |
|
|
|
1155 |
|
|
begin
|
1156 |
|
|
|
1157 |
|
|
for array_index in 0 to num_elements-1 loop
|
1158 |
|
|
|
1159 |
|
|
temp_baseaddr32_array(array_index) := slv32_array(array_index);
|
1160 |
|
|
|
1161 |
|
|
end loop;
|
1162 |
|
|
|
1163 |
|
|
|
1164 |
|
|
return(temp_baseaddr32_array);
|
1165 |
|
|
|
1166 |
|
|
end function rebuild_slv32_array;
|
1167 |
|
|
|
1168 |
|
|
|
1169 |
|
|
|
1170 |
|
|
|
1171 |
|
|
------------------------------------------------------------------------------
|
1172 |
|
|
-- Function: rebuild_slv64_array
|
1173 |
|
|
--
|
1174 |
|
|
-- Description:
|
1175 |
|
|
-- This function takes an input slv64 array and rebuilds an output slv64
|
1176 |
|
|
-- array composed of the first "num_valid_entry" elements from the input
|
1177 |
|
|
-- array.
|
1178 |
|
|
------------------------------------------------------------------------------
|
1179 |
|
|
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
|
1180 |
|
|
num_valid_pairs : integer)
|
1181 |
|
|
return SLV64_ARRAY_TYPE is
|
1182 |
|
|
|
1183 |
|
|
--Constants
|
1184 |
|
|
constant num_elements : Integer := num_valid_pairs * 2;
|
1185 |
|
|
|
1186 |
|
|
-- Variables
|
1187 |
|
|
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
|
1188 |
|
|
|
1189 |
|
|
begin
|
1190 |
|
|
|
1191 |
|
|
for array_index in 0 to num_elements-1 loop
|
1192 |
|
|
|
1193 |
|
|
temp_baseaddr64_array(array_index) := slv64_array(array_index);
|
1194 |
|
|
|
1195 |
|
|
end loop;
|
1196 |
|
|
|
1197 |
|
|
|
1198 |
|
|
return(temp_baseaddr64_array);
|
1199 |
|
|
|
1200 |
|
|
end function rebuild_slv64_array;
|
1201 |
|
|
|
1202 |
|
|
|
1203 |
|
|
|
1204 |
|
|
------------------------------------------------------------------------------
|
1205 |
|
|
-- Function: rebuild_int_array
|
1206 |
|
|
--
|
1207 |
|
|
-- Description:
|
1208 |
|
|
-- This function takes an input integer array and rebuilds an output integer
|
1209 |
|
|
-- array composed of the first "num_valid_entry" elements from the input
|
1210 |
|
|
-- array.
|
1211 |
|
|
------------------------------------------------------------------------------
|
1212 |
|
|
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
|
1213 |
|
|
num_valid_entry : integer)
|
1214 |
|
|
return INTEGER_ARRAY_TYPE is
|
1215 |
|
|
|
1216 |
|
|
-- Variables
|
1217 |
|
|
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
|
1218 |
|
|
|
1219 |
|
|
begin
|
1220 |
|
|
|
1221 |
|
|
for array_index in 0 to num_valid_entry-1 loop
|
1222 |
|
|
|
1223 |
|
|
temp_int_array(array_index) := int_array(array_index);
|
1224 |
|
|
|
1225 |
|
|
end loop;
|
1226 |
|
|
|
1227 |
|
|
|
1228 |
|
|
return(temp_int_array);
|
1229 |
|
|
|
1230 |
|
|
end function rebuild_int_array;
|
1231 |
|
|
|
1232 |
|
|
|
1233 |
|
|
|
1234 |
|
|
function bits_needed_for_vac(
|
1235 |
|
|
fifo_present: boolean;
|
1236 |
|
|
dependent_props : DEPENDENT_PROPS_TYPE
|
1237 |
|
|
) return integer is
|
1238 |
|
|
begin
|
1239 |
|
|
if not fifo_present then
|
1240 |
|
|
return 1; -- Zero would be better but leads to "0 to -1" null
|
1241 |
|
|
-- ranges that are not handled by XST Flint or earlier
|
1242 |
|
|
-- because of the negative index.
|
1243 |
|
|
else
|
1244 |
|
|
return
|
1245 |
|
|
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
|
1246 |
|
|
dependent_props(RD_WIDTH_BITS)
|
1247 |
|
|
);
|
1248 |
|
|
end if;
|
1249 |
|
|
end function bits_needed_for_vac;
|
1250 |
|
|
|
1251 |
|
|
|
1252 |
|
|
function bits_needed_for_occ(
|
1253 |
|
|
fifo_present: boolean;
|
1254 |
|
|
dependent_props : DEPENDENT_PROPS_TYPE
|
1255 |
|
|
) return integer is
|
1256 |
|
|
begin
|
1257 |
|
|
if not fifo_present then
|
1258 |
|
|
return 1; -- Zero would be better but leads to "0 to -1" null
|
1259 |
|
|
-- ranges that are not handled by XST Flint or earlier
|
1260 |
|
|
-- because of the negative index.
|
1261 |
|
|
else
|
1262 |
|
|
return
|
1263 |
|
|
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
|
1264 |
|
|
dependent_props(WR_WIDTH_BITS)
|
1265 |
|
|
);
|
1266 |
|
|
end if;
|
1267 |
|
|
end function bits_needed_for_occ;
|
1268 |
|
|
|
1269 |
|
|
|
1270 |
|
|
function eff_dp(id : integer;
|
1271 |
|
|
dep_prop : integer;
|
1272 |
|
|
value : integer) return integer is
|
1273 |
|
|
variable dp : integer := dep_prop;
|
1274 |
|
|
type bo2na_type is array (boolean) of natural;
|
1275 |
|
|
constant bo2na : bo2na_type := (0, 1);
|
1276 |
|
|
begin
|
1277 |
|
|
if value /= 0 then return value; end if; -- Not default
|
1278 |
|
|
case id is
|
1279 |
|
|
when IPIF_CHDMA_CHANNELS =>
|
1280 |
|
|
-------------------
|
1281 |
|
|
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
|
1282 |
|
|
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
|
1283 |
|
|
+ bo2na(dp = BURST_SIZE ) * 16
|
1284 |
|
|
);
|
1285 |
|
|
when others => return 0;
|
1286 |
|
|
end case;
|
1287 |
|
|
end eff_dp;
|
1288 |
|
|
|
1289 |
|
|
|
1290 |
|
|
function populate_intr_mode_array (num_user_intr : integer;
|
1291 |
|
|
intr_capture_mode : integer)
|
1292 |
|
|
return INTEGER_ARRAY_TYPE is
|
1293 |
|
|
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
|
1294 |
|
|
begin
|
1295 |
|
|
for i in 0 to num_user_intr-1 loop
|
1296 |
|
|
intr_mode_array(i) := intr_capture_mode;
|
1297 |
|
|
end loop;
|
1298 |
|
|
|
1299 |
|
|
return intr_mode_array;
|
1300 |
|
|
end function populate_intr_mode_array;
|
1301 |
|
|
|
1302 |
|
|
|
1303 |
|
|
function add_intr_ard_id_array(include_intr : boolean;
|
1304 |
|
|
ard_id_array : INTEGER_ARRAY_TYPE)
|
1305 |
|
|
return INTEGER_ARRAY_TYPE is
|
1306 |
|
|
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
|
1307 |
|
|
begin
|
1308 |
|
|
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
|
1309 |
|
|
if include_intr then
|
1310 |
|
|
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
|
1311 |
|
|
return intr_ard_id_array;
|
1312 |
|
|
else
|
1313 |
|
|
return ard_id_array;
|
1314 |
|
|
end if;
|
1315 |
|
|
end function add_intr_ard_id_array;
|
1316 |
|
|
|
1317 |
|
|
|
1318 |
|
|
function add_intr_ard_addr_range_array(include_intr : boolean;
|
1319 |
|
|
ZERO_ADDR_PAD : std_logic_vector;
|
1320 |
|
|
intr_baseaddr : std_logic_vector;
|
1321 |
|
|
intr_highaddr : std_logic_vector;
|
1322 |
|
|
ard_id_array : INTEGER_ARRAY_TYPE;
|
1323 |
|
|
ard_addr_range_array : SLV64_ARRAY_TYPE)
|
1324 |
|
|
return SLV64_ARRAY_TYPE is
|
1325 |
|
|
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
|
1326 |
|
|
begin
|
1327 |
|
|
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
|
1328 |
|
|
if include_intr then
|
1329 |
|
|
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
|
1330 |
|
|
:= ZERO_ADDR_PAD & intr_baseaddr;
|
1331 |
|
|
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
|
1332 |
|
|
:= ZERO_ADDR_PAD & intr_highaddr;
|
1333 |
|
|
return intr_ard_addr_range_array;
|
1334 |
|
|
else
|
1335 |
|
|
return ard_addr_range_array;
|
1336 |
|
|
end if;
|
1337 |
|
|
end function add_intr_ard_addr_range_array;
|
1338 |
|
|
|
1339 |
|
|
function add_intr_ard_dwidth_array(include_intr : boolean;
|
1340 |
|
|
intr_dwidth : integer;
|
1341 |
|
|
ard_id_array : INTEGER_ARRAY_TYPE;
|
1342 |
|
|
ard_dwidth_array : INTEGER_ARRAY_TYPE)
|
1343 |
|
|
return INTEGER_ARRAY_TYPE is
|
1344 |
|
|
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
|
1345 |
|
|
begin
|
1346 |
|
|
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
|
1347 |
|
|
if include_intr then
|
1348 |
|
|
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
|
1349 |
|
|
return intr_ard_dwidth_array;
|
1350 |
|
|
else
|
1351 |
|
|
return ard_dwidth_array;
|
1352 |
|
|
end if;
|
1353 |
|
|
end function add_intr_ard_dwidth_array;
|
1354 |
|
|
|
1355 |
|
|
function add_intr_ard_num_ce_array(include_intr : boolean;
|
1356 |
|
|
ard_id_array : INTEGER_ARRAY_TYPE;
|
1357 |
|
|
ard_num_ce_array : INTEGER_ARRAY_TYPE)
|
1358 |
|
|
return INTEGER_ARRAY_TYPE is
|
1359 |
|
|
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
|
1360 |
|
|
begin
|
1361 |
|
|
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
|
1362 |
|
|
if include_intr then
|
1363 |
|
|
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
|
1364 |
|
|
return intr_ard_num_ce_array;
|
1365 |
|
|
else
|
1366 |
|
|
return ard_num_ce_array;
|
1367 |
|
|
end if;
|
1368 |
|
|
end function add_intr_ard_num_ce_array;
|
1369 |
|
|
|
1370 |
|
|
|
1371 |
|
|
end package body ipif_pkg;
|
1372 |
|
|
|
1373 |
|
|
|
1374 |
|
|
-- pselect_f.vhd - entity/architecture pair
|
1375 |
|
|
-------------------------------------------------------------------------------
|
1376 |
|
|
--
|
1377 |
|
|
-- *************************************************************************
|
1378 |
|
|
-- ** **
|
1379 |
|
|
-- ** DISCLAIMER OF LIABILITY **
|
1380 |
|
|
-- ** **
|
1381 |
|
|
-- ** This text/file contains proprietary, confidential **
|
1382 |
|
|
-- ** information of Xilinx, Inc., is distributed under **
|
1383 |
|
|
-- ** license from Xilinx, Inc., and may be used, copied **
|
1384 |
|
|
-- ** and/or disclosed only pursuant to the terms of a valid **
|
1385 |
|
|
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
|
1386 |
|
|
-- ** grants you a license to use this text/file solely for **
|
1387 |
|
|
-- ** design, simulation, implementation and creation of **
|
1388 |
|
|
-- ** design files limited to Xilinx devices or technologies. **
|
1389 |
|
|
-- ** Use with non-Xilinx devices or technologies is expressly **
|
1390 |
|
|
-- ** prohibited and immediately terminates your license unless **
|
1391 |
|
|
-- ** covered by a separate agreement. **
|
1392 |
|
|
-- ** **
|
1393 |
|
|
-- ** Xilinx is providing this design, code, or information **
|
1394 |
|
|
-- ** "as-is" solely for use in developing programs and **
|
1395 |
|
|
-- ** solutions for Xilinx devices, with no obligation on the **
|
1396 |
|
|
-- ** part of Xilinx to provide support. By providing this design, **
|
1397 |
|
|
-- ** code, or information as one possible implementation of **
|
1398 |
|
|
-- ** this feature, application or standard, Xilinx is making no **
|
1399 |
|
|
-- ** representation that this implementation is free from any **
|
1400 |
|
|
-- ** claims of infringement. You are responsible for obtaining **
|
1401 |
|
|
-- ** any rights you may require for your implementation. **
|
1402 |
|
|
-- ** Xilinx expressly disclaims any warranty whatsoever with **
|
1403 |
|
|
-- ** respect to the adequacy of the implementation, including **
|
1404 |
|
|
-- ** but not limited to any warranties or representations that this **
|
1405 |
|
|
-- ** implementation is free from claims of infringement, implied **
|
1406 |
|
|
-- ** warranties of merchantability or fitness for a particular **
|
1407 |
|
|
-- ** purpose. **
|
1408 |
|
|
-- ** **
|
1409 |
|
|
-- ** Xilinx products are not intended for use in life support **
|
1410 |
|
|
-- ** appliances, devices, or systems. Use in such applications is **
|
1411 |
|
|
-- ** expressly prohibited. **
|
1412 |
|
|
-- ** **
|
1413 |
|
|
-- ** Any modifications that are made to the Source Code are **
|
1414 |
|
|
-- ** done at the user’s sole risk and will be unsupported. **
|
1415 |
|
|
-- ** The Xilinx Support Hotline does not have access to source **
|
1416 |
|
|
-- ** code and therefore cannot answer specific questions related **
|
1417 |
|
|
-- ** to source HDL. The Xilinx Hotline support of original source **
|
1418 |
|
|
-- ** code IP shall only address issues and questions related **
|
1419 |
|
|
-- ** to the standard Netlist version of the core (and thus **
|
1420 |
|
|
-- ** indirectly, the original core source). **
|
1421 |
|
|
-- ** **
|
1422 |
|
|
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
|
1423 |
|
|
-- ** **
|
1424 |
|
|
-- ** This copyright and support notice must be retained as part **
|
1425 |
|
|
-- ** of this text at all times. **
|
1426 |
|
|
-- ** **
|
1427 |
|
|
-- *************************************************************************
|
1428 |
|
|
--
|
1429 |
|
|
-------------------------------------------------------------------------------
|
1430 |
|
|
-- Filename: pselect_f.vhd
|
1431 |
|
|
--
|
1432 |
|
|
-- Description:
|
1433 |
|
|
-- (Note: At least as early as I.31, XST implements a carry-
|
1434 |
|
|
-- chain structure for most decoders when these are coded in
|
1435 |
|
|
-- inferrable VHLD. An example of such code can be seen
|
1436 |
|
|
-- below in the "INFERRED_GEN" Generate Statement.
|
1437 |
|
|
--
|
1438 |
|
|
-- -> New code should not need to instantiate pselect-type
|
1439 |
|
|
-- components.
|
1440 |
|
|
--
|
1441 |
|
|
-- -> Existing code can be ported to Virtex5 and later by
|
1442 |
|
|
-- replacing pselect instances by pselect_f instances.
|
1443 |
|
|
-- As long as the C_FAMILY parameter is not included
|
1444 |
|
|
-- in the Generic Map, an inferred implementation
|
1445 |
|
|
-- will result.
|
1446 |
|
|
--
|
1447 |
|
|
-- -> If the designer wishes to force an explicit carry-
|
1448 |
|
|
-- chain implementation, pselect_f can be used with
|
1449 |
|
|
-- the C_FAMILY parameter set to the target
|
1450 |
|
|
-- Xilinx FPGA family.
|
1451 |
|
|
-- )
|
1452 |
|
|
--
|
1453 |
|
|
-- Parameterizeable peripheral select (address decode).
|
1454 |
|
|
-- AValid qualifier comes in on Carry In at bottom
|
1455 |
|
|
-- of carry chain.
|
1456 |
|
|
--
|
1457 |
|
|
--
|
1458 |
|
|
-- VHDL-Standard: VHDL'93
|
1459 |
|
|
-------------------------------------------------------------------------------
|
1460 |
|
|
-- Structure: pselect_f.vhd
|
1461 |
|
|
-- family_support.vhd
|
1462 |
|
|
--
|
1463 |
|
|
-------------------------------------------------------------------------------
|
1464 |
|
|
-- History:
|
1465 |
|
|
-- Vaibhav & FLO 05/26/06 First Version
|
1466 |
|
|
--
|
1467 |
|
|
-- DET 1/17/2008 v4_0
|
1468 |
|
|
-- ~~~~~~
|
1469 |
|
|
-- - Changed proc_common library version to v4_0
|
1470 |
|
|
-- - Incorporated new disclaimer header
|
1471 |
|
|
-- ^^^^^^
|
1472 |
|
|
--
|
1473 |
|
|
-------------------------------------------------------------------------------
|
1474 |
|
|
-------------------------------------------------------------------------------
|
1475 |
|
|
-- Naming Conventions:
|
1476 |
|
|
-- active low signals: "*_n"
|
1477 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
1478 |
|
|
-- reset signals: "rst", "rst_n"
|
1479 |
|
|
-- generics: "C_*"
|
1480 |
|
|
-- user defined types: "*_TYPE"
|
1481 |
|
|
-- state machine next state: "*_ns"
|
1482 |
|
|
-- state machine current state: "*_cs"
|
1483 |
|
|
-- combinatorial signals: "*_com"
|
1484 |
|
|
-- pipelined or register delay signals: "*_d#"
|
1485 |
|
|
-- counter signals: "*cnt*"
|
1486 |
|
|
-- clock enable signals: "*_ce"
|
1487 |
|
|
-- internal version of output port "*_i"
|
1488 |
|
|
-- device pins: "*_pin"
|
1489 |
|
|
-- ports: - Names begin with Uppercase
|
1490 |
|
|
-- processes: "*_PROCESS"
|
1491 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
1492 |
|
|
-------------------------------------------------------------------------------
|
1493 |
|
|
library IEEE;
|
1494 |
|
|
use IEEE.std_logic_1164.all;
|
1495 |
|
|
|
1496 |
|
|
|
1497 |
|
|
-----------------------------------------------------------------------------
|
1498 |
|
|
-- Entity section
|
1499 |
|
|
-----------------------------------------------------------------------------
|
1500 |
|
|
-------------------------------------------------------------------------------
|
1501 |
|
|
-- Definition of Generics:
|
1502 |
|
|
-- C_AB -- number of address bits to decode
|
1503 |
|
|
-- C_AW -- width of address bus
|
1504 |
|
|
-- C_BAR -- base address of peripheral (peripheral select
|
1505 |
|
|
-- is asserted when the C_AB most significant
|
1506 |
|
|
-- address bits match the C_AB most significant
|
1507 |
|
|
-- C_BAR bits
|
1508 |
|
|
-- Definition of Ports:
|
1509 |
|
|
-- A -- address input
|
1510 |
|
|
-- AValid -- address qualifier
|
1511 |
|
|
-- CS -- peripheral select
|
1512 |
|
|
-------------------------------------------------------------------------------
|
1513 |
|
|
|
1514 |
|
|
entity pselect_f is
|
1515 |
|
|
|
1516 |
|
|
generic (
|
1517 |
|
|
C_AB : integer := 9;
|
1518 |
|
|
C_AW : integer := 32;
|
1519 |
|
|
C_BAR : std_logic_vector;
|
1520 |
|
|
C_FAMILY : string := "nofamily"
|
1521 |
|
|
);
|
1522 |
|
|
port (
|
1523 |
|
|
A : in std_logic_vector(0 to C_AW-1);
|
1524 |
|
|
AValid : in std_logic;
|
1525 |
|
|
CS : out std_logic
|
1526 |
|
|
);
|
1527 |
|
|
|
1528 |
|
|
end entity pselect_f;
|
1529 |
|
|
|
1530 |
|
|
-----------------------------------------------------------------------------
|
1531 |
|
|
-- Architecture section
|
1532 |
|
|
-----------------------------------------------------------------------------
|
1533 |
|
|
|
1534 |
|
|
architecture imp of pselect_f is
|
1535 |
|
|
|
1536 |
|
|
|
1537 |
|
|
|
1538 |
|
|
-----------------------------------------------------------------------------
|
1539 |
|
|
-- C_BAR may not be indexed from 0 and may not be ascending;
|
1540 |
|
|
-- BAR recasts C_BAR to have these properties.
|
1541 |
|
|
-----------------------------------------------------------------------------
|
1542 |
|
|
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
|
1543 |
|
|
|
1544 |
|
|
-- type bo2sl_type is array (boolean) of std_logic;
|
1545 |
|
|
-- constant bo2sl : bo2sl_type := (false => '0', true => '1');
|
1546 |
|
|
|
1547 |
|
|
function min(i, j: integer) return integer is
|
1548 |
|
|
begin
|
1549 |
|
|
if i<j then return i; else return j; end if;
|
1550 |
|
|
end;
|
1551 |
|
|
|
1552 |
|
|
begin
|
1553 |
|
|
|
1554 |
|
|
------------------------------------------------------------------------------
|
1555 |
|
|
-- Check that the generics are valid.
|
1556 |
|
|
------------------------------------------------------------------------------
|
1557 |
|
|
-- synthesis translate_off
|
1558 |
|
|
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
|
1559 |
|
|
report "pselect_f generic error: " &
|
1560 |
|
|
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
|
1561 |
|
|
" does not hold."
|
1562 |
|
|
severity failure;
|
1563 |
|
|
-- synthesis translate_on
|
1564 |
|
|
|
1565 |
|
|
|
1566 |
|
|
------------------------------------------------------------------------------
|
1567 |
|
|
-- Build a behavioral decoder
|
1568 |
|
|
------------------------------------------------------------------------------
|
1569 |
|
|
|
1570 |
|
|
XST_WA:if C_AB > 0 generate
|
1571 |
|
|
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
|
1572 |
|
|
'0' ;
|
1573 |
|
|
end generate XST_WA;
|
1574 |
|
|
|
1575 |
|
|
PASS_ON_GEN:if C_AB = 0 generate
|
1576 |
|
|
CS <= AValid ;
|
1577 |
|
|
end generate PASS_ON_GEN;
|
1578 |
|
|
|
1579 |
|
|
|
1580 |
|
|
|
1581 |
|
|
|
1582 |
|
|
end imp;
|
1583 |
|
|
|
1584 |
|
|
|
1585 |
|
|
|
1586 |
|
|
-------------------------------------------------------------------
|
1587 |
|
|
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
|
1588 |
|
|
--
|
1589 |
|
|
-- This file contains confidential and proprietary information
|
1590 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
1591 |
|
|
-- international copyright and other intellectual property
|
1592 |
|
|
-- laws.
|
1593 |
|
|
--
|
1594 |
|
|
-- DISCLAIMER
|
1595 |
|
|
-- This disclaimer is not a license and does not grant any
|
1596 |
|
|
-- rights to the materials distributed herewith. Except as
|
1597 |
|
|
-- otherwise provided in a valid license issued to you by
|
1598 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
1599 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
1600 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
1601 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
1602 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
1603 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
1604 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
1605 |
|
|
-- including negligence, or under any other theory of
|
1606 |
|
|
-- liability) for any loss or damage of any kind or nature
|
1607 |
|
|
-- related to, arising under or in connection with these
|
1608 |
|
|
-- materials, including for any direct, or any indirect,
|
1609 |
|
|
-- special, incidental, or consequential loss or damage
|
1610 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
1611 |
|
|
-- loss or damage suffered as a result of any action brought
|
1612 |
|
|
-- by a third party) even if such damage or loss was
|
1613 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
1614 |
|
|
-- possibility of the same.
|
1615 |
|
|
--
|
1616 |
|
|
-- CRITICAL APPLICATIONS
|
1617 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
1618 |
|
|
-- safe, or for use in any application requiring fail-safe
|
1619 |
|
|
-- performance, such as life-support or safety devices or
|
1620 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
1621 |
|
|
-- applications related to the deployment of airbags, or any
|
1622 |
|
|
-- other applications that could lead to death, personal
|
1623 |
|
|
-- injury, or severe property or environmental damage
|
1624 |
|
|
-- (individually and collectively, "Critical
|
1625 |
|
|
-- Applications"). Customer assumes the sole risk and
|
1626 |
|
|
-- liability of any use of Xilinx products in Critical
|
1627 |
|
|
-- Applications, subject only to applicable laws and
|
1628 |
|
|
-- regulations governing limitations on product liability.
|
1629 |
|
|
--
|
1630 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
1631 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
1632 |
|
|
-------------------------------------------------------------------
|
1633 |
|
|
-- ************************************************************************
|
1634 |
|
|
--
|
1635 |
|
|
-------------------------------------------------------------------------------
|
1636 |
|
|
-- Filename: address_decoder.vhd
|
1637 |
|
|
-- Version: v2.0
|
1638 |
|
|
-- Description: Address decoder utilizing unconstrained arrays for Base
|
1639 |
|
|
-- Address specification and ce number.
|
1640 |
|
|
-------------------------------------------------------------------------------
|
1641 |
|
|
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
|
1642 |
|
|
--
|
1643 |
|
|
-- --axi_lite_ipif.vhd
|
1644 |
|
|
-- --slave_attachment.vhd
|
1645 |
|
|
-- --address_decoder.vhd
|
1646 |
|
|
-------------------------------------------------------------------------------
|
1647 |
|
|
-- Author: BSB
|
1648 |
|
|
--
|
1649 |
|
|
-- History:
|
1650 |
|
|
--
|
1651 |
|
|
-- BSB 05/20/10 -- First version
|
1652 |
|
|
-- ~~~~~~
|
1653 |
|
|
-- - Created the first version v1.00.a
|
1654 |
|
|
-- ^^^^^^
|
1655 |
|
|
-- ~~~~~~
|
1656 |
|
|
-- SK 08/09/2010 --
|
1657 |
|
|
-- - updated the core with optimziation. Closed CR 574507
|
1658 |
|
|
-- - combined the CE generation logic to further optimize the code.
|
1659 |
|
|
-- ^^^^^^
|
1660 |
|
|
-- ~~~~~~
|
1661 |
|
|
-- SK 12/16/12 -- v2.0
|
1662 |
|
|
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
|
1663 |
|
|
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
|
1664 |
|
|
-- 3. updated the proc common version to proc_common_base_v5_0
|
1665 |
|
|
-- 4. No Logic Updates
|
1666 |
|
|
-- ^^^^^^
|
1667 |
|
|
-------------------------------------------------------------------------------
|
1668 |
|
|
-- Naming Conventions:
|
1669 |
|
|
-- active low signals: "*_n"
|
1670 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
1671 |
|
|
-- reset signals: "rst", "rst_n"
|
1672 |
|
|
-- generics: "C_*"
|
1673 |
|
|
-- user defined types: "*_TYPE"
|
1674 |
|
|
-- state machine next state: "*_ns"
|
1675 |
|
|
-- state machine current state: "*_cs"
|
1676 |
|
|
-- combinatorial signals: "*_cmb"
|
1677 |
|
|
-- pipelined or register delay signals: "*_d#"
|
1678 |
|
|
-- counter signals: "*cnt*"
|
1679 |
|
|
-- clock enable signals: "*_ce"
|
1680 |
|
|
-- internal version of output port "*_i"
|
1681 |
|
|
-- device pins: "*_pin"
|
1682 |
|
|
-- ports: - Names begin with Uppercase
|
1683 |
|
|
-- processes: "*_PROCESS"
|
1684 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
1685 |
|
|
-------------------------------------------------------------------------------
|
1686 |
|
|
|
1687 |
|
|
library IEEE;
|
1688 |
|
|
use IEEE.std_logic_1164.all;
|
1689 |
|
|
use ieee.numeric_std.all;
|
1690 |
|
|
|
1691 |
|
|
--library proc_common_base_v5_0;
|
1692 |
|
|
--use proc_common_base_v5_0.proc_common_pkg.clog2;
|
1693 |
|
|
--use proc_common_base_v5_0.pselect_f;
|
1694 |
|
|
--use proc_common_base_v5_0.ipif_pkg.all;
|
1695 |
|
|
|
1696 |
|
|
library axi_lite_ipif_v3_0_4;
|
1697 |
|
|
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
|
1698 |
|
|
|
1699 |
|
|
-------------------------------------------------------------------------------
|
1700 |
|
|
-- Definition of Generics
|
1701 |
|
|
-------------------------------------------------------------------------------
|
1702 |
|
|
-- C_BUS_AWIDTH -- Address bus width
|
1703 |
|
|
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
|
1704 |
|
|
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
|
1705 |
|
|
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
|
1706 |
|
|
-- C_FAMILY -- Target FPGA family
|
1707 |
|
|
-------------------------------------------------------------------------------
|
1708 |
|
|
-- Definition of Ports
|
1709 |
|
|
-------------------------------------------------------------------------------
|
1710 |
|
|
-- Bus_clk -- Clock
|
1711 |
|
|
-- Bus_rst -- Reset
|
1712 |
|
|
-- Address_In_Erly -- Adddress in
|
1713 |
|
|
-- Address_Valid_Erly -- Address is valid
|
1714 |
|
|
-- Bus_RNW -- Read or write registered
|
1715 |
|
|
-- Bus_RNW_Erly -- Read or Write
|
1716 |
|
|
-- CS_CE_ld_enable -- chip select and chip enable registered
|
1717 |
|
|
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
|
1718 |
|
|
-- RW_CE_ld_enable -- Read or Write Chip Enable
|
1719 |
|
|
-- CS_for_gaps -- CS generation for the gaps between address ranges
|
1720 |
|
|
-- CS_Out -- Chip select
|
1721 |
|
|
-- RdCE_Out -- Read Chip enable
|
1722 |
|
|
-- WrCE_Out -- Write chip enable
|
1723 |
|
|
-------------------------------------------------------------------------------
|
1724 |
|
|
-------------------------------------------------------------------------------
|
1725 |
|
|
-- Entity Declaration
|
1726 |
|
|
-------------------------------------------------------------------------------
|
1727 |
|
|
|
1728 |
|
|
entity address_decoder is
|
1729 |
|
|
generic (
|
1730 |
|
|
C_BUS_AWIDTH : integer := 32;
|
1731 |
|
|
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
|
1732 |
|
|
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
|
1733 |
|
|
(
|
1734 |
|
|
X"0000_0000_1000_0000", -- IP user0 base address
|
1735 |
|
|
X"0000_0000_1000_01FF", -- IP user0 high address
|
1736 |
|
|
X"0000_0000_1000_0200", -- IP user1 base address
|
1737 |
|
|
X"0000_0000_1000_02FF" -- IP user1 high address
|
1738 |
|
|
);
|
1739 |
|
|
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
|
1740 |
|
|
(
|
1741 |
|
|
8, -- User0 CE Number
|
1742 |
|
|
1 -- User1 CE Number
|
1743 |
|
|
);
|
1744 |
|
|
C_FAMILY : string := "virtex6"
|
1745 |
|
|
);
|
1746 |
|
|
port (
|
1747 |
|
|
Bus_clk : in std_logic;
|
1748 |
|
|
Bus_rst : in std_logic;
|
1749 |
|
|
|
1750 |
|
|
-- PLB Interface signals
|
1751 |
|
|
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
|
1752 |
|
|
Address_Valid_Erly : in std_logic;
|
1753 |
|
|
Bus_RNW : in std_logic;
|
1754 |
|
|
Bus_RNW_Erly : in std_logic;
|
1755 |
|
|
|
1756 |
|
|
-- Registering control signals
|
1757 |
|
|
CS_CE_ld_enable : in std_logic;
|
1758 |
|
|
Clear_CS_CE_Reg : in std_logic;
|
1759 |
|
|
RW_CE_ld_enable : in std_logic;
|
1760 |
|
|
CS_for_gaps : out std_logic;
|
1761 |
|
|
-- Decode output signals
|
1762 |
|
|
CS_Out : out std_logic_vector
|
1763 |
|
|
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
|
1764 |
|
|
RdCE_Out : out std_logic_vector
|
1765 |
|
|
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
|
1766 |
|
|
WrCE_Out : out std_logic_vector
|
1767 |
|
|
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
|
1768 |
|
|
);
|
1769 |
|
|
end entity address_decoder;
|
1770 |
|
|
|
1771 |
|
|
-------------------------------------------------------------------------------
|
1772 |
|
|
-- Architecture section
|
1773 |
|
|
-------------------------------------------------------------------------------
|
1774 |
|
|
|
1775 |
|
|
architecture IMP of address_decoder is
|
1776 |
|
|
----------------------------------------------------------------------------------
|
1777 |
|
|
-- below attributes are added to reduce the synth warnings in Vivado tool
|
1778 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
1779 |
|
|
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
|
1780 |
|
|
----------------------------------------------------------------------------------
|
1781 |
|
|
|
1782 |
|
|
-- local type declarations ----------------------------------------------------
|
1783 |
|
|
type decode_bit_array_type is Array(natural range 0 to (
|
1784 |
|
|
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
|
1785 |
|
|
integer;
|
1786 |
|
|
|
1787 |
|
|
type short_addr_array_type is Array(natural range 0 to
|
1788 |
|
|
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
|
1789 |
|
|
std_logic_vector(0 to C_BUS_AWIDTH-1);
|
1790 |
|
|
-------------------------------------------------------------------------------
|
1791 |
|
|
-- Function Declarations
|
1792 |
|
|
-------------------------------------------------------------------------------
|
1793 |
|
|
|
1794 |
|
|
-------------------------------------------------------------------------------
|
1795 |
|
|
-- This function converts a 64 bit address range array to a AWIDTH bit
|
1796 |
|
|
-- address range array.
|
1797 |
|
|
-------------------------------------------------------------------------------
|
1798 |
|
|
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
|
1799 |
|
|
awidth : integer)
|
1800 |
|
|
return short_addr_array_type is
|
1801 |
|
|
|
1802 |
|
|
variable temp_addr : std_logic_vector(0 to 63);
|
1803 |
|
|
variable slv_array : short_addr_array_type;
|
1804 |
|
|
begin
|
1805 |
|
|
for array_index in 0 to slv64_addr_array'length-1 loop
|
1806 |
|
|
temp_addr := slv64_addr_array(array_index);
|
1807 |
|
|
slv_array(array_index) := temp_addr((64-awidth) to 63);
|
1808 |
|
|
end loop;
|
1809 |
|
|
return(slv_array);
|
1810 |
|
|
end function slv64_2_slv_awidth;
|
1811 |
|
|
|
1812 |
|
|
-------------------------------------------------------------------------------
|
1813 |
|
|
--Function Addr_bits
|
1814 |
|
|
--function to convert an address range (base address and an upper address)
|
1815 |
|
|
--into the number of upper address bits needed for decoding a device
|
1816 |
|
|
--select signal. will handle slices and big or little endian
|
1817 |
|
|
-------------------------------------------------------------------------------
|
1818 |
|
|
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
|
1819 |
|
|
return integer is
|
1820 |
|
|
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
|
1821 |
|
|
begin
|
1822 |
|
|
addr_nor := x xor y;
|
1823 |
|
|
for i in 0 to C_BUS_AWIDTH-1 loop
|
1824 |
|
|
if addr_nor(i)='1' then
|
1825 |
|
|
return i;
|
1826 |
|
|
end if;
|
1827 |
|
|
end loop;
|
1828 |
|
|
--coverage off
|
1829 |
|
|
return(C_BUS_AWIDTH);
|
1830 |
|
|
--coverage on
|
1831 |
|
|
end function Addr_Bits;
|
1832 |
|
|
|
1833 |
|
|
|
1834 |
|
|
-------------------------------------------------------------------------------
|
1835 |
|
|
--Function Get_Addr_Bits
|
1836 |
|
|
--function calculates the array which has the decode bits for the each address
|
1837 |
|
|
--range.
|
1838 |
|
|
-------------------------------------------------------------------------------
|
1839 |
|
|
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
|
1840 |
|
|
return decode_bit_array_type is
|
1841 |
|
|
|
1842 |
|
|
variable num_bits : decode_bit_array_type;
|
1843 |
|
|
begin
|
1844 |
|
|
for i in 0 to ((baseaddrs'length)/2)-1 loop
|
1845 |
|
|
|
1846 |
|
|
num_bits(i) := Addr_Bits (baseaddrs(i*2),
|
1847 |
|
|
baseaddrs(i*2+1));
|
1848 |
|
|
end loop;
|
1849 |
|
|
return(num_bits);
|
1850 |
|
|
end function Get_Addr_Bits;
|
1851 |
|
|
|
1852 |
|
|
|
1853 |
|
|
-------------------------------------------------------------------------------
|
1854 |
|
|
-- NEEDED_ADDR_BITS
|
1855 |
|
|
--
|
1856 |
|
|
-- Function Description:
|
1857 |
|
|
-- This function calculates the number of address bits required
|
1858 |
|
|
-- to support the CE generation logic. This is determined by
|
1859 |
|
|
-- multiplying the number of CEs for an address space by the
|
1860 |
|
|
-- data width of the address space (in bytes). Each address
|
1861 |
|
|
-- space entry is processed and the biggest of the spaces is
|
1862 |
|
|
-- used to set the number of address bits required to be latched
|
1863 |
|
|
-- and used for CE decoding. A minimum value of 1 is returned by
|
1864 |
|
|
-- this function.
|
1865 |
|
|
--
|
1866 |
|
|
-------------------------------------------------------------------------------
|
1867 |
|
|
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
|
1868 |
|
|
return integer is
|
1869 |
|
|
|
1870 |
|
|
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
|
1871 |
|
|
variable biggest : integer := 2;
|
1872 |
|
|
variable req_ce_addr_size : integer := 0;
|
1873 |
|
|
variable num_addr_bits : integer := 0;
|
1874 |
|
|
begin
|
1875 |
|
|
|
1876 |
|
|
for i in 0 to NUM_CE_ENTRIES-1 loop
|
1877 |
|
|
req_ce_addr_size := ce_array(i) * 4;
|
1878 |
|
|
if (req_ce_addr_size > biggest) Then
|
1879 |
|
|
biggest := req_ce_addr_size;
|
1880 |
|
|
end if;
|
1881 |
|
|
end loop;
|
1882 |
|
|
num_addr_bits := clog2(biggest);
|
1883 |
|
|
return(num_addr_bits);
|
1884 |
|
|
end function NEEDED_ADDR_BITS;
|
1885 |
|
|
|
1886 |
|
|
-----------------------------------------------------------------------------
|
1887 |
|
|
-- Function calc_high_address
|
1888 |
|
|
--
|
1889 |
|
|
-- This function is used to calculate the high address of the each address
|
1890 |
|
|
-- range
|
1891 |
|
|
-----------------------------------------------------------------------------
|
1892 |
|
|
function calc_high_address (high_address : short_addr_array_type;
|
1893 |
|
|
index : integer) return std_logic_vector is
|
1894 |
|
|
|
1895 |
|
|
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
|
1896 |
|
|
|
1897 |
|
|
begin
|
1898 |
|
|
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
|
1899 |
|
|
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
|
1900 |
|
|
else
|
1901 |
|
|
calc_high_addr := high_address(index*2+2);
|
1902 |
|
|
end if;
|
1903 |
|
|
return(calc_high_addr);
|
1904 |
|
|
end function calc_high_address;
|
1905 |
|
|
|
1906 |
|
|
----------------------------------------------------------------------------
|
1907 |
|
|
-- Constant Declarations
|
1908 |
|
|
-------------------------------------------------------------------------------
|
1909 |
|
|
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
|
1910 |
|
|
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
|
1911 |
|
|
C_BUS_AWIDTH);
|
1912 |
|
|
|
1913 |
|
|
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
|
1914 |
|
|
|
1915 |
|
|
constant DECODE_BITS : decode_bit_array_type :=
|
1916 |
|
|
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
|
1917 |
|
|
|
1918 |
|
|
constant NUM_CE_SIGNALS : integer :=
|
1919 |
|
|
calc_num_ce(C_ARD_NUM_CE_ARRAY);
|
1920 |
|
|
|
1921 |
|
|
constant NUM_S_H_ADDR_BITS : integer :=
|
1922 |
|
|
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
|
1923 |
|
|
-------------------------------------------------------------------------------
|
1924 |
|
|
-- Signal Declarations
|
1925 |
|
|
-------------------------------------------------------------------------------
|
1926 |
|
|
signal pselect_hit_i : std_logic_vector
|
1927 |
|
|
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
|
1928 |
|
|
signal cs_out_i : std_logic_vector
|
1929 |
|
|
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
|
1930 |
|
|
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
|
1931 |
|
|
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
|
1932 |
|
|
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
|
1933 |
|
|
|
1934 |
|
|
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
|
1935 |
|
|
|
1936 |
|
|
signal cs_ce_clr : std_logic;
|
1937 |
|
|
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
|
1938 |
|
|
|
1939 |
|
|
signal Bus_RNW_reg : std_logic;
|
1940 |
|
|
-------------------------------------------------------------------------------
|
1941 |
|
|
-- Begin architecture
|
1942 |
|
|
-------------------------------------------------------------------------------
|
1943 |
|
|
begin -- architecture IMP
|
1944 |
|
|
|
1945 |
|
|
|
1946 |
|
|
-- Register clears
|
1947 |
|
|
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
|
1948 |
|
|
|
1949 |
|
|
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
|
1950 |
|
|
to C_BUS_AWIDTH-1);
|
1951 |
|
|
-------------------------------------------------------------------------------
|
1952 |
|
|
-- MEM_DECODE_GEN: Universal Address Decode Block
|
1953 |
|
|
-------------------------------------------------------------------------------
|
1954 |
|
|
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
|
1955 |
|
|
---------------
|
1956 |
|
|
constant CE_INDEX_START : integer
|
1957 |
|
|
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
|
1958 |
|
|
constant CE_ADDR_SIZE : Integer range 0 to 15
|
1959 |
|
|
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
|
1960 |
|
|
constant OFFSET : integer := 2;
|
1961 |
|
|
|
1962 |
|
|
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
|
1963 |
|
|
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
|
1964 |
|
|
|
1965 |
|
|
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
|
1966 |
|
|
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
|
1967 |
|
|
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
|
1968 |
|
|
---------
|
1969 |
|
|
begin
|
1970 |
|
|
---------
|
1971 |
|
|
|
1972 |
|
|
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
|
1973 |
|
|
-- -----------------
|
1974 |
|
|
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
|
1975 |
|
|
-- Instantiate the basic Base Address Decoders
|
1976 |
|
|
MEM_SELECT_I: entity axi_lite_ipif_v3_0_4.pselect_f
|
1977 |
|
|
generic map
|
1978 |
|
|
(
|
1979 |
|
|
C_AB => DECODE_BITS(bar_index),
|
1980 |
|
|
C_AW => C_BUS_AWIDTH,
|
1981 |
|
|
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
|
1982 |
|
|
C_FAMILY => C_FAMILY
|
1983 |
|
|
)
|
1984 |
|
|
port map
|
1985 |
|
|
(
|
1986 |
|
|
A => Address_In_Erly, -- [in]
|
1987 |
|
|
AValid => Address_Valid_Erly, -- [in]
|
1988 |
|
|
CS => pselect_hit_i(bar_index) -- [out]
|
1989 |
|
|
);
|
1990 |
|
|
end generate GEN_FOR_MULTI_CS;
|
1991 |
|
|
|
1992 |
|
|
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
|
1993 |
|
|
-- ---------------
|
1994 |
|
|
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
|
1995 |
|
|
pselect_hit_i(bar_index) <= Address_Valid_Erly;
|
1996 |
|
|
end generate GEN_FOR_ONE_CS;
|
1997 |
|
|
|
1998 |
|
|
|
1999 |
|
|
-- Instantate backend registers for the Chip Selects
|
2000 |
|
|
BKEND_CS_REG : process(Bus_Clk)
|
2001 |
|
|
begin
|
2002 |
|
|
if(Bus_Clk'EVENT and Bus_Clk = '1')then
|
2003 |
|
|
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
|
2004 |
|
|
cs_out_i(bar_index) <= '0';
|
2005 |
|
|
elsif(CS_CE_ld_enable='1')then
|
2006 |
|
|
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
|
2007 |
|
|
end if;
|
2008 |
|
|
end if;
|
2009 |
|
|
end process BKEND_CS_REG;
|
2010 |
|
|
|
2011 |
|
|
-------------------------------------------------------------------------
|
2012 |
|
|
-- PER_CE_GEN: Now expand the individual CEs for each base address.
|
2013 |
|
|
-------------------------------------------------------------------------
|
2014 |
|
|
PER_CE_GEN: for j in natural range 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
|
2015 |
|
|
-----------
|
2016 |
|
|
begin
|
2017 |
|
|
-----------
|
2018 |
|
|
----------------------------------------------------------------------
|
2019 |
|
|
-- CE decoders for multiple CE's
|
2020 |
|
|
----------------------------------------------------------------------
|
2021 |
|
|
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
|
2022 |
|
|
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
|
2023 |
|
|
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
|
2024 |
|
|
begin
|
2025 |
|
|
CE_I : entity axi_lite_ipif_v3_0_4.pselect_f
|
2026 |
|
|
generic map (
|
2027 |
|
|
C_AB => CE_ADDR_SIZE ,
|
2028 |
|
|
C_AW => CE_ADDR_SIZE ,
|
2029 |
|
|
C_BAR => BAR ,
|
2030 |
|
|
C_FAMILY => C_FAMILY
|
2031 |
|
|
)
|
2032 |
|
|
port map (
|
2033 |
|
|
A => addr_out_s_h
|
2034 |
|
|
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
|
2035 |
|
|
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
|
2036 |
|
|
AValid => pselect_hit_i(bar_index) ,
|
2037 |
|
|
CS => ce_expnd_i(CE_INDEX_START+j)
|
2038 |
|
|
);
|
2039 |
|
|
end generate MULTIPLE_CES_THIS_CS_GEN;
|
2040 |
|
|
--------------------------------------
|
2041 |
|
|
----------------------------------------------------------------------
|
2042 |
|
|
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
|
2043 |
|
|
----------------------------------------------------------------------
|
2044 |
|
|
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
|
2045 |
|
|
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
|
2046 |
|
|
end generate;
|
2047 |
|
|
-------------
|
2048 |
|
|
end generate PER_CE_GEN;
|
2049 |
|
|
------------------------
|
2050 |
|
|
end generate MEM_DECODE_GEN;
|
2051 |
|
|
|
2052 |
|
|
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
|
2053 |
|
|
-- address. This is need to generate the CE's separately.
|
2054 |
|
|
|
2055 |
|
|
RNW_REG_P:process(Bus_Clk)
|
2056 |
|
|
begin
|
2057 |
|
|
if(Bus_Clk'EVENT and Bus_Clk = '1')then
|
2058 |
|
|
if(RW_CE_ld_enable='1')then
|
2059 |
|
|
Bus_RNW_reg <= Bus_RNW_Erly;
|
2060 |
|
|
end if;
|
2061 |
|
|
end if;
|
2062 |
|
|
end process RNW_REG_P;
|
2063 |
|
|
|
2064 |
|
|
---------------------------------------------------------------------------
|
2065 |
|
|
-- GEN_BKEND_CE_REGISTERS
|
2066 |
|
|
-- This ForGen implements the backend registering for
|
2067 |
|
|
-- the CE, RdCE, and WrCE output buses.
|
2068 |
|
|
---------------------------------------------------------------------------
|
2069 |
|
|
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
|
2070 |
|
|
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
|
2071 |
|
|
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
|
2072 |
|
|
------
|
2073 |
|
|
begin
|
2074 |
|
|
------
|
2075 |
|
|
|
2076 |
|
|
|
2077 |
|
|
BKEND_RDCE_REG : process(Bus_Clk)
|
2078 |
|
|
begin
|
2079 |
|
|
if(Bus_Clk'EVENT and Bus_Clk = '1')then
|
2080 |
|
|
if(cs_ce_clr='1')then
|
2081 |
|
|
ce_out_i(ce_index) <= '0';
|
2082 |
|
|
elsif(RW_CE_ld_enable='1')then
|
2083 |
|
|
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
|
2084 |
|
|
end if;
|
2085 |
|
|
end if;
|
2086 |
|
|
end process BKEND_RDCE_REG;
|
2087 |
|
|
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
|
2088 |
|
|
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
|
2089 |
|
|
|
2090 |
|
|
-------------------------------
|
2091 |
|
|
end generate GEN_BKEND_CE_REGISTERS;
|
2092 |
|
|
-------------------------------------------------------------------------------
|
2093 |
|
|
|
2094 |
|
|
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
|
2095 |
|
|
---------------------------------
|
2096 |
|
|
CS_Out <= cs_out_i ;
|
2097 |
|
|
RdCE_Out <= rdce_out_i ;
|
2098 |
|
|
WrCE_Out <= wrce_out_i ;
|
2099 |
|
|
|
2100 |
|
|
end architecture IMP;
|
2101 |
|
|
|
2102 |
|
|
|
2103 |
|
|
-------------------------------------------------------------------
|
2104 |
|
|
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
|
2105 |
|
|
--
|
2106 |
|
|
-- This file contains confidential and proprietary information
|
2107 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
2108 |
|
|
-- international copyright and other intellectual property
|
2109 |
|
|
-- laws.
|
2110 |
|
|
--
|
2111 |
|
|
-- DISCLAIMER
|
2112 |
|
|
-- This disclaimer is not a license and does not grant any
|
2113 |
|
|
-- rights to the materials distributed herewith. Except as
|
2114 |
|
|
-- otherwise provided in a valid license issued to you by
|
2115 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
2116 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
2117 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
2118 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
2119 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
2120 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
2121 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
2122 |
|
|
-- including negligence, or under any other theory of
|
2123 |
|
|
-- liability) for any loss or damage of any kind or nature
|
2124 |
|
|
-- related to, arising under or in connection with these
|
2125 |
|
|
-- materials, including for any direct, or any indirect,
|
2126 |
|
|
-- special, incidental, or consequential loss or damage
|
2127 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
2128 |
|
|
-- loss or damage suffered as a result of any action brought
|
2129 |
|
|
-- by a third party) even if such damage or loss was
|
2130 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
2131 |
|
|
-- possibility of the same.
|
2132 |
|
|
--
|
2133 |
|
|
-- CRITICAL APPLICATIONS
|
2134 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
2135 |
|
|
-- safe, or for use in any application requiring fail-safe
|
2136 |
|
|
-- performance, such as life-support or safety devices or
|
2137 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
2138 |
|
|
-- applications related to the deployment of airbags, or any
|
2139 |
|
|
-- other applications that could lead to death, personal
|
2140 |
|
|
-- injury, or severe property or environmental damage
|
2141 |
|
|
-- (individually and collectively, "Critical
|
2142 |
|
|
-- Applications"). Customer assumes the sole risk and
|
2143 |
|
|
-- liability of any use of Xilinx products in Critical
|
2144 |
|
|
-- Applications, subject only to applicable laws and
|
2145 |
|
|
-- regulations governing limitations on product liability.
|
2146 |
|
|
--
|
2147 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
2148 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
2149 |
|
|
-------------------------------------------------------------------
|
2150 |
|
|
-- ************************************************************************
|
2151 |
|
|
--
|
2152 |
|
|
-------------------------------------------------------------------------------
|
2153 |
|
|
-- Filename: slave_attachment.vhd
|
2154 |
|
|
-- Version: v2.0
|
2155 |
|
|
-- Description: AXI slave attachment supporting single transfers
|
2156 |
|
|
-------------------------------------------------------------------------------
|
2157 |
|
|
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
|
2158 |
|
|
--
|
2159 |
|
|
-- --axi_lite_ipif.vhd
|
2160 |
|
|
-- --slave_attachment.vhd
|
2161 |
|
|
-- --address_decoder.vhd
|
2162 |
|
|
-------------------------------------------------------------------------------
|
2163 |
|
|
-- Author: BSB
|
2164 |
|
|
--
|
2165 |
|
|
-- History:
|
2166 |
|
|
--
|
2167 |
|
|
-- BSB 05/20/10 -- First version
|
2168 |
|
|
-- ~~~~~~
|
2169 |
|
|
-- - Created the first version v1.00.a
|
2170 |
|
|
-- ^^^^^^
|
2171 |
|
|
-- ~~~~~~
|
2172 |
|
|
-- SK 06/09/10 -- updated to reduce the utilization
|
2173 |
|
|
-- 1. State machine is re-designed
|
2174 |
|
|
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
|
2175 |
|
|
-- 3. Address decoding is done only for the required address bits and not complete
|
2176 |
|
|
-- 32 bits
|
2177 |
|
|
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
|
2178 |
|
|
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
|
2179 |
|
|
-- function.
|
2180 |
|
|
-- ^^^^^^
|
2181 |
|
|
-- ~~~~~~
|
2182 |
|
|
-- SK 12/16/12 -- v2.0
|
2183 |
|
|
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
|
2184 |
|
|
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
|
2185 |
|
|
-- 3. updated the proc common version to proc_common_base_v5_0
|
2186 |
|
|
-- 4. No Logic Updates
|
2187 |
|
|
-- ^^^^^^
|
2188 |
|
|
-------------------------------------------------------------------------------
|
2189 |
|
|
-- Naming Conventions:
|
2190 |
|
|
-- active low signals: "*_n"
|
2191 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
2192 |
|
|
-- reset signals: "rst", "rst_n"
|
2193 |
|
|
-- generics: "C_*"
|
2194 |
|
|
-- user defined types: "*_TYPE"
|
2195 |
|
|
-- access_cs machine next state: "*_ns"
|
2196 |
|
|
-- state machine current state: "*_cs"
|
2197 |
|
|
-- combinatorial signals: "*_cmb"
|
2198 |
|
|
-- pipelined or register delay signals: "*_d#"
|
2199 |
|
|
-- counter signals: "*cnt*"
|
2200 |
|
|
-- clock enable signals: "*_ce"
|
2201 |
|
|
-- internal version of output port "*_i"
|
2202 |
|
|
-- device pins: "*_pin"
|
2203 |
|
|
-- ports: - Names begin with Uppercase
|
2204 |
|
|
-- processes: "*_PROCESS"
|
2205 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
2206 |
|
|
-------------------------------------------------------------------------------
|
2207 |
|
|
library ieee;
|
2208 |
|
|
use ieee.std_logic_1164.all;
|
2209 |
|
|
use ieee.numeric_std.all;
|
2210 |
|
|
use ieee.std_logic_unsigned.all;
|
2211 |
|
|
use ieee.std_logic_misc.all;
|
2212 |
|
|
|
2213 |
|
|
--library proc_common_base_v5_0;
|
2214 |
|
|
--use proc_common_base_v5_0.proc_common_pkg.clog2;
|
2215 |
|
|
--use proc_common_base_v5_0.ipif_pkg.all;
|
2216 |
|
|
|
2217 |
|
|
library axi_lite_ipif_v3_0_4;
|
2218 |
|
|
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
|
2219 |
|
|
|
2220 |
|
|
-------------------------------------------------------------------------------
|
2221 |
|
|
-- Definition of Generics
|
2222 |
|
|
-------------------------------------------------------------------------------
|
2223 |
|
|
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
|
2224 |
|
|
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
|
2225 |
|
|
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
|
2226 |
|
|
-- C_USE_WSTRB -- Use write strobs or not
|
2227 |
|
|
-- C_DPHASE_TIMEOUT -- Data phase time out counter
|
2228 |
|
|
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
|
2229 |
|
|
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
|
2230 |
|
|
-- C_FAMILY -- Target FPGA family
|
2231 |
|
|
-------------------------------------------------------------------------------
|
2232 |
|
|
-- Definition of Ports
|
2233 |
|
|
-------------------------------------------------------------------------------
|
2234 |
|
|
-- S_AXI_ACLK -- AXI Clock
|
2235 |
|
|
-- S_AXI_ARESET -- AXI Reset
|
2236 |
|
|
-- S_AXI_AWADDR -- AXI Write address
|
2237 |
|
|
-- S_AXI_AWVALID -- Write address valid
|
2238 |
|
|
-- S_AXI_AWREADY -- Write address ready
|
2239 |
|
|
-- S_AXI_WDATA -- Write data
|
2240 |
|
|
-- S_AXI_WSTRB -- Write strobes
|
2241 |
|
|
-- S_AXI_WVALID -- Write valid
|
2242 |
|
|
-- S_AXI_WREADY -- Write ready
|
2243 |
|
|
-- S_AXI_BRESP -- Write response
|
2244 |
|
|
-- S_AXI_BVALID -- Write response valid
|
2245 |
|
|
-- S_AXI_BREADY -- Response ready
|
2246 |
|
|
-- S_AXI_ARADDR -- Read address
|
2247 |
|
|
-- S_AXI_ARVALID -- Read address valid
|
2248 |
|
|
-- S_AXI_ARREADY -- Read address ready
|
2249 |
|
|
-- S_AXI_RDATA -- Read data
|
2250 |
|
|
-- S_AXI_RRESP -- Read response
|
2251 |
|
|
-- S_AXI_RVALID -- Read valid
|
2252 |
|
|
-- S_AXI_RREADY -- Read ready
|
2253 |
|
|
-- Bus2IP_Clk -- Synchronization clock provided to User IP
|
2254 |
|
|
-- Bus2IP_Reset -- Active high reset for use by the User IP
|
2255 |
|
|
-- Bus2IP_Addr -- Desired address of read or write operation
|
2256 |
|
|
-- Bus2IP_RNW -- Read or write indicator for the transaction
|
2257 |
|
|
-- Bus2IP_BE -- Byte enables for the data bus
|
2258 |
|
|
-- Bus2IP_CS -- Chip select for the transcations
|
2259 |
|
|
-- Bus2IP_RdCE -- Chip enables for the read
|
2260 |
|
|
-- Bus2IP_WrCE -- Chip enables for the write
|
2261 |
|
|
-- Bus2IP_Data -- Write data bus to the User IP
|
2262 |
|
|
-- IP2Bus_Data -- Input Read Data bus from the User IP
|
2263 |
|
|
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
|
2264 |
|
|
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
|
2265 |
|
|
-- IP2Bus_Error -- Error signal from the IP
|
2266 |
|
|
-------------------------------------------------------------------------------
|
2267 |
|
|
|
2268 |
|
|
entity slave_attachment is
|
2269 |
|
|
generic (
|
2270 |
|
|
|
2271 |
|
|
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
|
2272 |
|
|
(
|
2273 |
|
|
X"0000_0000_7000_0000", -- IP user0 base address
|
2274 |
|
|
X"0000_0000_7000_00FF", -- IP user0 high address
|
2275 |
|
|
X"0000_0000_7000_0100", -- IP user1 base address
|
2276 |
|
|
X"0000_0000_7000_01FF" -- IP user1 high address
|
2277 |
|
|
);
|
2278 |
|
|
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
|
2279 |
|
|
(
|
2280 |
|
|
1, -- User0 CE Number
|
2281 |
|
|
8 -- User1 CE Number
|
2282 |
|
|
);
|
2283 |
|
|
C_IPIF_ABUS_WIDTH : integer := 32;
|
2284 |
|
|
C_IPIF_DBUS_WIDTH : integer := 32;
|
2285 |
|
|
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
|
2286 |
|
|
C_USE_WSTRB : integer := 0;
|
2287 |
|
|
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
|
2288 |
|
|
C_FAMILY : string := "virtex6"
|
2289 |
|
|
);
|
2290 |
|
|
port(
|
2291 |
|
|
-- AXI signals
|
2292 |
|
|
S_AXI_ACLK : in std_logic;
|
2293 |
|
|
S_AXI_ARESETN : in std_logic;
|
2294 |
|
|
S_AXI_AWADDR : in std_logic_vector
|
2295 |
|
|
(C_IPIF_ABUS_WIDTH-1 downto 0);
|
2296 |
|
|
S_AXI_AWVALID : in std_logic;
|
2297 |
|
|
S_AXI_AWREADY : out std_logic;
|
2298 |
|
|
S_AXI_WDATA : in std_logic_vector
|
2299 |
|
|
(C_IPIF_DBUS_WIDTH-1 downto 0);
|
2300 |
|
|
S_AXI_WSTRB : in std_logic_vector
|
2301 |
|
|
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
|
2302 |
|
|
S_AXI_WVALID : in std_logic;
|
2303 |
|
|
S_AXI_WREADY : out std_logic;
|
2304 |
|
|
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
2305 |
|
|
S_AXI_BVALID : out std_logic;
|
2306 |
|
|
S_AXI_BREADY : in std_logic;
|
2307 |
|
|
S_AXI_ARADDR : in std_logic_vector
|
2308 |
|
|
(C_IPIF_ABUS_WIDTH-1 downto 0);
|
2309 |
|
|
S_AXI_ARVALID : in std_logic;
|
2310 |
|
|
S_AXI_ARREADY : out std_logic;
|
2311 |
|
|
S_AXI_RDATA : out std_logic_vector
|
2312 |
|
|
(C_IPIF_DBUS_WIDTH-1 downto 0);
|
2313 |
|
|
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
2314 |
|
|
S_AXI_RVALID : out std_logic;
|
2315 |
|
|
S_AXI_RREADY : in std_logic;
|
2316 |
|
|
-- Controls to the IP/IPIF modules
|
2317 |
|
|
Bus2IP_Clk : out std_logic;
|
2318 |
|
|
Bus2IP_Resetn : out std_logic;
|
2319 |
|
|
Bus2IP_Addr : out std_logic_vector
|
2320 |
|
|
(C_IPIF_ABUS_WIDTH-1 downto 0);
|
2321 |
|
|
Bus2IP_RNW : out std_logic;
|
2322 |
|
|
Bus2IP_BE : out std_logic_vector
|
2323 |
|
|
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
|
2324 |
|
|
Bus2IP_CS : out std_logic_vector
|
2325 |
|
|
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
|
2326 |
|
|
Bus2IP_RdCE : out std_logic_vector
|
2327 |
|
|
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
|
2328 |
|
|
Bus2IP_WrCE : out std_logic_vector
|
2329 |
|
|
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
|
2330 |
|
|
Bus2IP_Data : out std_logic_vector
|
2331 |
|
|
((C_IPIF_DBUS_WIDTH-1) downto 0);
|
2332 |
|
|
IP2Bus_Data : in std_logic_vector
|
2333 |
|
|
((C_IPIF_DBUS_WIDTH-1) downto 0);
|
2334 |
|
|
IP2Bus_WrAck : in std_logic;
|
2335 |
|
|
IP2Bus_RdAck : in std_logic;
|
2336 |
|
|
IP2Bus_Error : in std_logic
|
2337 |
|
|
);
|
2338 |
|
|
end entity slave_attachment;
|
2339 |
|
|
|
2340 |
|
|
-------------------------------------------------------------------------------
|
2341 |
|
|
architecture imp of slave_attachment is
|
2342 |
|
|
----------------------------------------------------------------------------------
|
2343 |
|
|
-- below attributes are added to reduce the synth warnings in Vivado tool
|
2344 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
2345 |
|
|
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
|
2346 |
|
|
----------------------------------------------------------------------------------
|
2347 |
|
|
|
2348 |
|
|
-------------------------------------------------------------------------------
|
2349 |
|
|
-- Get_Addr_Bits: Function Declarations
|
2350 |
|
|
-------------------------------------------------------------------------------
|
2351 |
|
|
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
|
2352 |
|
|
variable i : integer := 0;
|
2353 |
|
|
begin
|
2354 |
|
|
for i in 31 downto 0 loop
|
2355 |
|
|
if y(i)='1' then
|
2356 |
|
|
return (i);
|
2357 |
|
|
end if;
|
2358 |
|
|
end loop;
|
2359 |
|
|
return -1;
|
2360 |
|
|
end function Get_Addr_Bits;
|
2361 |
|
|
|
2362 |
|
|
-------------------------------------------------------------------------------
|
2363 |
|
|
-- Constant Declarations
|
2364 |
|
|
-------------------------------------------------------------------------------
|
2365 |
|
|
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
|
2366 |
|
|
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
|
2367 |
|
|
|
2368 |
|
|
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
|
2369 |
|
|
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
|
2370 |
|
|
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
|
2371 |
|
|
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
|
2372 |
|
|
-------------------------------------------------------------------------------
|
2373 |
|
|
-- Signal and Type Declarations
|
2374 |
|
|
-------------------------------------------------------------------------------
|
2375 |
|
|
signal s_axi_bvalid_i : std_logic:= '0';
|
2376 |
|
|
signal s_axi_arready_i : std_logic;
|
2377 |
|
|
signal s_axi_rvalid_i : std_logic:= '0';
|
2378 |
|
|
signal start : std_logic;
|
2379 |
|
|
signal start2 : std_logic;
|
2380 |
|
|
-- Intermediate IPIC signals
|
2381 |
|
|
signal bus2ip_addr_i : std_logic_vector
|
2382 |
|
|
((C_IPIF_ABUS_WIDTH-1) downto 0);
|
2383 |
|
|
signal timeout : std_logic;
|
2384 |
|
|
|
2385 |
|
|
signal rd_done,wr_done : std_logic;
|
2386 |
|
|
signal rd_done1,wr_done1 : std_logic;
|
2387 |
|
|
--signal rd_done2,wr_done2 : std_logic;
|
2388 |
|
|
signal wrack_1,rdack_1 : std_logic;
|
2389 |
|
|
--signal wrack_2,rdack_2 : std_logic;
|
2390 |
|
|
signal rst : std_logic;
|
2391 |
|
|
signal temp_i : std_logic;
|
2392 |
|
|
|
2393 |
|
|
type BUS_ACCESS_STATES is (
|
2394 |
|
|
SM_IDLE,
|
2395 |
|
|
SM_READ,
|
2396 |
|
|
SM_WRITE,
|
2397 |
|
|
SM_RESP
|
2398 |
|
|
);
|
2399 |
|
|
signal state : BUS_ACCESS_STATES;
|
2400 |
|
|
|
2401 |
|
|
signal cs_for_gaps_i : std_logic;
|
2402 |
|
|
signal bus2ip_rnw_i : std_logic;
|
2403 |
|
|
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
|
2404 |
|
|
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
|
2405 |
|
|
signal s_axi_rdata_i : std_logic_vector
|
2406 |
|
|
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
|
2407 |
|
|
signal is_read, is_write : std_logic;
|
2408 |
|
|
-------------------------------------------------------------------------------
|
2409 |
|
|
-- begin the architecture logic
|
2410 |
|
|
-------------------------------------------------------------------------------
|
2411 |
|
|
begin
|
2412 |
|
|
|
2413 |
|
|
-------------------------------------------------------------------------------
|
2414 |
|
|
-- Address registered
|
2415 |
|
|
-------------------------------------------------------------------------------
|
2416 |
|
|
Bus2IP_Clk <= S_AXI_ACLK;
|
2417 |
|
|
Bus2IP_Resetn <= S_AXI_ARESETN;
|
2418 |
|
|
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
|
2419 |
|
|
-- else
|
2420 |
|
|
-- '0';
|
2421 |
|
|
BUS2IP_RNW <= bus2ip_rnw_i;
|
2422 |
|
|
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
|
2423 |
|
|
else
|
2424 |
|
|
(others => '1');
|
2425 |
|
|
Bus2IP_Data <= S_AXI_WDATA;
|
2426 |
|
|
Bus2IP_Addr <= bus2ip_addr_i;
|
2427 |
|
|
|
2428 |
|
|
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
|
2429 |
|
|
-- read and write channel. so onlyone address is used for decoding as well as
|
2430 |
|
|
-- passing it to IP.
|
2431 |
|
|
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
|
2432 |
|
|
-- when (S_AXI_ARVALID='1')
|
2433 |
|
|
-- else
|
2434 |
|
|
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
|
2435 |
|
|
|
2436 |
|
|
--------------------------------------------------------------------------------
|
2437 |
|
|
-- start signal will be used to latch the incoming address
|
2438 |
|
|
|
2439 |
|
|
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
|
2440 |
|
|
-- when (state = SM_IDLE)
|
2441 |
|
|
-- else
|
2442 |
|
|
-- '0';
|
2443 |
|
|
|
2444 |
|
|
-- x_done signals are used to release the hold from AXI, it will generate "ready"
|
2445 |
|
|
-- signal on the read and write address channels.
|
2446 |
|
|
|
2447 |
|
|
rd_done <= IP2Bus_RdAck or (timeout and is_read);
|
2448 |
|
|
wr_done <= IP2Bus_WrAck or (timeout and is_write);
|
2449 |
|
|
|
2450 |
|
|
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
|
2451 |
|
|
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
|
2452 |
|
|
|
2453 |
|
|
temp_i <= rd_done or wr_done;
|
2454 |
|
|
-------------------------------------------------------------------------------
|
2455 |
|
|
-- Address Decoder Component Instance
|
2456 |
|
|
--
|
2457 |
|
|
-- This component decodes the specified base address pairs and outputs the
|
2458 |
|
|
-- specified number of chip enables and the target bus size.
|
2459 |
|
|
-------------------------------------------------------------------------------
|
2460 |
|
|
I_DECODER : entity axi_lite_ipif_v3_0_4.address_decoder
|
2461 |
|
|
generic map
|
2462 |
|
|
(
|
2463 |
|
|
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
|
2464 |
|
|
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
|
2465 |
|
|
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
|
2466 |
|
|
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
|
2467 |
|
|
C_FAMILY => "nofamily"
|
2468 |
|
|
)
|
2469 |
|
|
port map
|
2470 |
|
|
(
|
2471 |
|
|
Bus_clk => S_AXI_ACLK,
|
2472 |
|
|
Bus_rst => S_AXI_ARESETN,
|
2473 |
|
|
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
|
2474 |
|
|
Address_Valid_Erly => start2,
|
2475 |
|
|
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
|
2476 |
|
|
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
|
2477 |
|
|
CS_CE_ld_enable => start2,
|
2478 |
|
|
Clear_CS_CE_Reg => temp_i,
|
2479 |
|
|
RW_CE_ld_enable => start2,
|
2480 |
|
|
CS_for_gaps => open,
|
2481 |
|
|
-- Decode output signals
|
2482 |
|
|
CS_Out => Bus2IP_CS,
|
2483 |
|
|
RdCE_Out => Bus2IP_RdCE,
|
2484 |
|
|
WrCE_Out => Bus2IP_WrCE
|
2485 |
|
|
);
|
2486 |
|
|
|
2487 |
|
|
|
2488 |
|
|
-- REGISTERING_RESET_P: Invert the reset coming from AXI
|
2489 |
|
|
-----------------------
|
2490 |
|
|
REGISTERING_RESET_P : process (S_AXI_ACLK) is
|
2491 |
|
|
begin
|
2492 |
|
|
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
|
2493 |
|
|
rst <= not S_AXI_ARESETN;
|
2494 |
|
|
end if;
|
2495 |
|
|
end process REGISTERING_RESET_P;
|
2496 |
|
|
|
2497 |
|
|
|
2498 |
|
|
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
|
2499 |
|
|
begin
|
2500 |
|
|
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
|
2501 |
|
|
if (rst = '1') then
|
2502 |
|
|
-- wrack_1 <= '0';
|
2503 |
|
|
-- rdack_1 <= '0';
|
2504 |
|
|
-- wrack_2 <= '0';
|
2505 |
|
|
-- rdack_2 <= '0';
|
2506 |
|
|
-- wr_done2 <= '0';
|
2507 |
|
|
-- rd_done2 <= '0';
|
2508 |
|
|
bus2ip_rnw_i <= '0';
|
2509 |
|
|
bus2ip_addr_i <= (others => '0');
|
2510 |
|
|
start2 <= '0';
|
2511 |
|
|
else
|
2512 |
|
|
-- wrack_1 <= IP2Bus_WrAck;
|
2513 |
|
|
-- rdack_1 <= IP2Bus_RdAck;
|
2514 |
|
|
-- wrack_2 <= wrack_1;
|
2515 |
|
|
-- rdack_2 <= rdack_1;
|
2516 |
|
|
-- wr_done2 <= wr_done1;
|
2517 |
|
|
-- rd_done2 <= rd_done1;
|
2518 |
|
|
|
2519 |
|
|
if (state = SM_IDLE and S_AXI_ARVALID='1') then
|
2520 |
|
|
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
|
2521 |
|
|
bus2ip_rnw_i <= '1';
|
2522 |
|
|
start2 <= '1';
|
2523 |
|
|
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
|
2524 |
|
|
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
|
2525 |
|
|
bus2ip_rnw_i <= '0';
|
2526 |
|
|
start2 <= '1';
|
2527 |
|
|
else
|
2528 |
|
|
bus2ip_rnw_i <= bus2ip_rnw_i;
|
2529 |
|
|
bus2ip_addr_i <= bus2ip_addr_i;
|
2530 |
|
|
start2 <= '0';
|
2531 |
|
|
end if;
|
2532 |
|
|
end if;
|
2533 |
|
|
end if;
|
2534 |
|
|
end process REGISTERING_RESET_P2;
|
2535 |
|
|
|
2536 |
|
|
|
2537 |
|
|
-------------------------------------------------------------------------------
|
2538 |
|
|
-- AXI Transaction Controller
|
2539 |
|
|
-------------------------------------------------------------------------------
|
2540 |
|
|
-- Access_Control: As per suggestion to optimize the core, the below state machine
|
2541 |
|
|
-- is re-coded. Latches are removed from original suggestions
|
2542 |
|
|
Access_Control : process (S_AXI_ACLK) is
|
2543 |
|
|
begin
|
2544 |
|
|
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
|
2545 |
|
|
if rst = '1' then
|
2546 |
|
|
state <= SM_IDLE;
|
2547 |
|
|
is_read <= '0';
|
2548 |
|
|
is_write <= '0';
|
2549 |
|
|
else
|
2550 |
|
|
case state is
|
2551 |
|
|
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
|
2552 |
|
|
state <= SM_READ;
|
2553 |
|
|
is_read <='1';
|
2554 |
|
|
is_write <= '0';
|
2555 |
|
|
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
|
2556 |
|
|
state <= SM_WRITE;
|
2557 |
|
|
is_read <='0';
|
2558 |
|
|
is_write <= '1';
|
2559 |
|
|
else
|
2560 |
|
|
state <= SM_IDLE;
|
2561 |
|
|
is_read <='0';
|
2562 |
|
|
is_write <= '0';
|
2563 |
|
|
end if;
|
2564 |
|
|
|
2565 |
|
|
when SM_READ => if rd_done = '1' then
|
2566 |
|
|
state <= SM_RESP;
|
2567 |
|
|
else
|
2568 |
|
|
state <= SM_READ;
|
2569 |
|
|
end if;
|
2570 |
|
|
|
2571 |
|
|
when SM_WRITE=> if (wr_done = '1') then
|
2572 |
|
|
state <= SM_RESP;
|
2573 |
|
|
else
|
2574 |
|
|
state <= SM_WRITE;
|
2575 |
|
|
end if;
|
2576 |
|
|
|
2577 |
|
|
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
|
2578 |
|
|
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
|
2579 |
|
|
state <= SM_IDLE;
|
2580 |
|
|
is_read <='0';
|
2581 |
|
|
is_write <= '0';
|
2582 |
|
|
else
|
2583 |
|
|
state <= SM_RESP;
|
2584 |
|
|
end if;
|
2585 |
|
|
-- coverage off
|
2586 |
|
|
when others => state <= SM_IDLE;
|
2587 |
|
|
-- coverage on
|
2588 |
|
|
end case;
|
2589 |
|
|
end if;
|
2590 |
|
|
end if;
|
2591 |
|
|
end process Access_Control;
|
2592 |
|
|
|
2593 |
|
|
-------------------------------------------------------------------------------
|
2594 |
|
|
-- AXI Transaction Controller signals registered
|
2595 |
|
|
-------------------------------------------------------------------------------
|
2596 |
|
|
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
|
2597 |
|
|
-----------------------
|
2598 |
|
|
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
|
2599 |
|
|
begin
|
2600 |
|
|
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
|
2601 |
|
|
if (rst = '1') then
|
2602 |
|
|
s_axi_rresp_i <= (others => '0');
|
2603 |
|
|
s_axi_rdata_i <= (others => '0');
|
2604 |
|
|
elsif state = SM_READ then
|
2605 |
|
|
s_axi_rresp_i <= (IP2Bus_Error) & '0';
|
2606 |
|
|
s_axi_rdata_i <= IP2Bus_Data;
|
2607 |
|
|
end if;
|
2608 |
|
|
end if;
|
2609 |
|
|
end process S_AXI_RDATA_RESP_P;
|
2610 |
|
|
|
2611 |
|
|
S_AXI_RRESP <= s_axi_rresp_i;
|
2612 |
|
|
S_AXI_RDATA <= s_axi_rdata_i;
|
2613 |
|
|
-----------------------------
|
2614 |
|
|
|
2615 |
|
|
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
|
2616 |
|
|
----------------------
|
2617 |
|
|
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
|
2618 |
|
|
begin
|
2619 |
|
|
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
|
2620 |
|
|
if (rst = '1') then
|
2621 |
|
|
s_axi_rvalid_i <= '0';
|
2622 |
|
|
elsif ((state = SM_READ) and rd_done = '1') then
|
2623 |
|
|
s_axi_rvalid_i <= '1';
|
2624 |
|
|
elsif (S_AXI_RREADY = '1') then
|
2625 |
|
|
s_axi_rvalid_i <= '0';
|
2626 |
|
|
end if;
|
2627 |
|
|
end if;
|
2628 |
|
|
end process S_AXI_RVALID_I_P;
|
2629 |
|
|
|
2630 |
|
|
-- -- S_AXI_BRESP_P: Below process provides logic for write response
|
2631 |
|
|
-- -----------------
|
2632 |
|
|
S_AXI_BRESP_P : process (S_AXI_ACLK) is
|
2633 |
|
|
begin
|
2634 |
|
|
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
|
2635 |
|
|
if (rst = '1') then
|
2636 |
|
|
s_axi_bresp_i <= (others => '0');
|
2637 |
|
|
elsif (state = SM_WRITE) then
|
2638 |
|
|
s_axi_bresp_i <= (IP2Bus_Error) & '0';
|
2639 |
|
|
end if;
|
2640 |
|
|
end if;
|
2641 |
|
|
end process S_AXI_BRESP_P;
|
2642 |
|
|
|
2643 |
|
|
S_AXI_BRESP <= s_axi_bresp_i;
|
2644 |
|
|
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
|
2645 |
|
|
-------------------
|
2646 |
|
|
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
|
2647 |
|
|
begin
|
2648 |
|
|
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
|
2649 |
|
|
if rst = '1' then
|
2650 |
|
|
s_axi_bvalid_i <= '0';
|
2651 |
|
|
elsif ((state = SM_WRITE) and wr_done = '1') then
|
2652 |
|
|
s_axi_bvalid_i <= '1';
|
2653 |
|
|
elsif (S_AXI_BREADY = '1') then
|
2654 |
|
|
s_axi_bvalid_i <= '0';
|
2655 |
|
|
end if;
|
2656 |
|
|
end if;
|
2657 |
|
|
end process S_AXI_BVALID_I_P;
|
2658 |
|
|
-----------------------------------------------------------------------------
|
2659 |
|
|
|
2660 |
|
|
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
|
2661 |
|
|
--------------
|
2662 |
|
|
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
|
2663 |
|
|
|
2664 |
|
|
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
|
2665 |
|
|
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
|
2666 |
|
|
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
|
2667 |
|
|
-- condition to be captured as a carry into this "extra" bit.
|
2668 |
|
|
begin
|
2669 |
|
|
|
2670 |
|
|
DPTO_CNT_P : process (S_AXI_ACLK) is
|
2671 |
|
|
begin
|
2672 |
|
|
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
|
2673 |
|
|
if ((state = SM_IDLE) or (state = SM_RESP)) then
|
2674 |
|
|
dpto_cnt <= (others=>'0');
|
2675 |
|
|
else
|
2676 |
|
|
dpto_cnt <= dpto_cnt + 1;
|
2677 |
|
|
end if;
|
2678 |
|
|
end if;
|
2679 |
|
|
end process DPTO_CNT_P;
|
2680 |
|
|
|
2681 |
|
|
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
|
2682 |
|
|
|
2683 |
|
|
end generate INCLUDE_DPHASE_TIMER;
|
2684 |
|
|
|
2685 |
|
|
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
|
2686 |
|
|
timeout <= '0';
|
2687 |
|
|
end generate EXCLUDE_DPHASE_TIMER;
|
2688 |
|
|
|
2689 |
|
|
-----------------------------------------------------------------------------
|
2690 |
|
|
S_AXI_BVALID <= s_axi_bvalid_i;
|
2691 |
|
|
S_AXI_RVALID <= s_axi_rvalid_i;
|
2692 |
|
|
-----------------------------------------------------------------------------
|
2693 |
|
|
S_AXI_ARREADY <= rd_done;
|
2694 |
|
|
S_AXI_AWREADY <= wr_done;
|
2695 |
|
|
S_AXI_WREADY <= wr_done;
|
2696 |
|
|
-------------------------------------------------------------------------------
|
2697 |
|
|
end imp;
|
2698 |
|
|
|
2699 |
|
|
|
2700 |
|
|
-------------------------------------------------------------------
|
2701 |
|
|
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
|
2702 |
|
|
--
|
2703 |
|
|
-- This file contains confidential and proprietary information
|
2704 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
2705 |
|
|
-- international copyright and other intellectual property
|
2706 |
|
|
-- laws.
|
2707 |
|
|
--
|
2708 |
|
|
-- DISCLAIMER
|
2709 |
|
|
-- This disclaimer is not a license and does not grant any
|
2710 |
|
|
-- rights to the materials distributed herewith. Except as
|
2711 |
|
|
-- otherwise provided in a valid license issued to you by
|
2712 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
2713 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
2714 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
2715 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
2716 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
2717 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
2718 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
2719 |
|
|
-- including negligence, or under any other theory of
|
2720 |
|
|
-- liability) for any loss or damage of any kind or nature
|
2721 |
|
|
-- related to, arising under or in connection with these
|
2722 |
|
|
-- materials, including for any direct, or any indirect,
|
2723 |
|
|
-- special, incidental, or consequential loss or damage
|
2724 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
2725 |
|
|
-- loss or damage suffered as a result of any action brought
|
2726 |
|
|
-- by a third party) even if such damage or loss was
|
2727 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
2728 |
|
|
-- possibility of the same.
|
2729 |
|
|
--
|
2730 |
|
|
-- CRITICAL APPLICATIONS
|
2731 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
2732 |
|
|
-- safe, or for use in any application requiring fail-safe
|
2733 |
|
|
-- performance, such as life-support or safety devices or
|
2734 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
2735 |
|
|
-- applications related to the deployment of airbags, or any
|
2736 |
|
|
-- other applications that could lead to death, personal
|
2737 |
|
|
-- injury, or severe property or environmental damage
|
2738 |
|
|
-- (individually and collectively, "Critical
|
2739 |
|
|
-- Applications"). Customer assumes the sole risk and
|
2740 |
|
|
-- liability of any use of Xilinx products in Critical
|
2741 |
|
|
-- Applications, subject only to applicable laws and
|
2742 |
|
|
-- regulations governing limitations on product liability.
|
2743 |
|
|
--
|
2744 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
2745 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
2746 |
|
|
-------------------------------------------------------------------
|
2747 |
|
|
-- ************************************************************************
|
2748 |
|
|
--
|
2749 |
|
|
-------------------------------------------------------------------------------
|
2750 |
|
|
-- Filename: axi_lite_ipif.vhd
|
2751 |
|
|
-- Version: v2.0
|
2752 |
|
|
-- Description: This is the top level design file for the axi_lite_ipif
|
2753 |
|
|
-- function. It provides a standardized slave interface
|
2754 |
|
|
-- between the IP and the AXI. This version supports
|
2755 |
|
|
-- single read/write transfers only. It does not provide
|
2756 |
|
|
-- address pipelining or simultaneous read and write
|
2757 |
|
|
-- operations.
|
2758 |
|
|
-------------------------------------------------------------------------------
|
2759 |
|
|
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
|
2760 |
|
|
--
|
2761 |
|
|
-- --axi_lite_ipif.vhd
|
2762 |
|
|
-- --slave_attachment.vhd
|
2763 |
|
|
-- --address_decoder.vhd
|
2764 |
|
|
-------------------------------------------------------------------------------
|
2765 |
|
|
-- Author: BSB
|
2766 |
|
|
--
|
2767 |
|
|
-- History:
|
2768 |
|
|
--
|
2769 |
|
|
-- BSB 05/20/10 -- First version
|
2770 |
|
|
-- ~~~~~~
|
2771 |
|
|
-- - Created the first version v1.00.a
|
2772 |
|
|
-- ^^^^^^
|
2773 |
|
|
-- ~~~~~~
|
2774 |
|
|
-- SK 06/09/10 -- v1.01.a
|
2775 |
|
|
-- 1. updated to reduce the utilization
|
2776 |
|
|
-- Closed CR #574507
|
2777 |
|
|
-- 2. Optimized the state machine code
|
2778 |
|
|
-- 3. Optimized the address decoder logic to generate the CE's with common logic
|
2779 |
|
|
-- 4. Address GAP decoding logic is removed and timeout counter is made active
|
2780 |
|
|
-- for all transactions.
|
2781 |
|
|
-- ^^^^^^
|
2782 |
|
|
-- ~~~~~~
|
2783 |
|
|
-- SK 12/16/12 -- v2.0
|
2784 |
|
|
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
|
2785 |
|
|
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
|
2786 |
|
|
-- 3. updated the proc common version to proc_common_base_v5_0
|
2787 |
|
|
-- 4. No Logic Updates
|
2788 |
|
|
-- ^^^^^^
|
2789 |
|
|
-------------------------------------------------------------------------------
|
2790 |
|
|
-- Naming Conventions:
|
2791 |
|
|
-- active low signals: "*_n"
|
2792 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
2793 |
|
|
-- reset signals: "rst", "rst_n"
|
2794 |
|
|
-- generics: "C_*"
|
2795 |
|
|
-- user defined types: "*_TYPE"
|
2796 |
|
|
-- state machine next state: "*_ns"
|
2797 |
|
|
-- state machine current state: "*_cs"
|
2798 |
|
|
-- combinatorial signals: "*_cmb"
|
2799 |
|
|
-- pipelined or register delay signals: "*_d#"
|
2800 |
|
|
-- counter signals: "*cnt*"
|
2801 |
|
|
-- clock enable signals: "*_ce"
|
2802 |
|
|
-- internal version of output port "*_i"
|
2803 |
|
|
-- device pins: "*_pin"
|
2804 |
|
|
-- ports: - Names begin with Uppercase
|
2805 |
|
|
-- processes: "*_PROCESS"
|
2806 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
2807 |
|
|
-------------------------------------------------------------------------------
|
2808 |
|
|
library ieee;
|
2809 |
|
|
use ieee.std_logic_1164.all;
|
2810 |
|
|
use ieee.std_logic_unsigned.all;
|
2811 |
|
|
use ieee.numeric_std.all;
|
2812 |
|
|
use ieee.std_logic_misc.all;
|
2813 |
|
|
|
2814 |
|
|
--library proc_common_base_v5_0;
|
2815 |
|
|
--use proc_common_base_v5_0.ipif_pkg.all;
|
2816 |
|
|
|
2817 |
|
|
library axi_lite_ipif_v3_0_4;
|
2818 |
|
|
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
|
2819 |
|
|
|
2820 |
|
|
-------------------------------------------------------------------------------
|
2821 |
|
|
-- Definition of Generics
|
2822 |
|
|
-------------------------------------------------------------------------------
|
2823 |
|
|
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
|
2824 |
|
|
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
|
2825 |
|
|
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
|
2826 |
|
|
-- C_USE_WSTRB -- Use write strobs or not
|
2827 |
|
|
-- C_DPHASE_TIMEOUT -- Data phase time out counter
|
2828 |
|
|
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
|
2829 |
|
|
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
|
2830 |
|
|
-- C_FAMILY -- Target FPGA family
|
2831 |
|
|
-------------------------------------------------------------------------------
|
2832 |
|
|
-- Definition of Ports
|
2833 |
|
|
-------------------------------------------------------------------------------
|
2834 |
|
|
-- S_AXI_ACLK -- AXI Clock
|
2835 |
|
|
-- S_AXI_ARESETN -- AXI Reset
|
2836 |
|
|
-- S_AXI_AWADDR -- AXI Write address
|
2837 |
|
|
-- S_AXI_AWVALID -- Write address valid
|
2838 |
|
|
-- S_AXI_AWREADY -- Write address ready
|
2839 |
|
|
-- S_AXI_WDATA -- Write data
|
2840 |
|
|
-- S_AXI_WSTRB -- Write strobes
|
2841 |
|
|
-- S_AXI_WVALID -- Write valid
|
2842 |
|
|
-- S_AXI_WREADY -- Write ready
|
2843 |
|
|
-- S_AXI_BRESP -- Write response
|
2844 |
|
|
-- S_AXI_BVALID -- Write response valid
|
2845 |
|
|
-- S_AXI_BREADY -- Response ready
|
2846 |
|
|
-- S_AXI_ARADDR -- Read address
|
2847 |
|
|
-- S_AXI_ARVALID -- Read address valid
|
2848 |
|
|
-- S_AXI_ARREADY -- Read address ready
|
2849 |
|
|
-- S_AXI_RDATA -- Read data
|
2850 |
|
|
-- S_AXI_RRESP -- Read response
|
2851 |
|
|
-- S_AXI_RVALID -- Read valid
|
2852 |
|
|
-- S_AXI_RREADY -- Read ready
|
2853 |
|
|
-- Bus2IP_Clk -- Synchronization clock provided to User IP
|
2854 |
|
|
-- Bus2IP_Reset -- Active high reset for use by the User IP
|
2855 |
|
|
-- Bus2IP_Addr -- Desired address of read or write operation
|
2856 |
|
|
-- Bus2IP_RNW -- Read or write indicator for the transaction
|
2857 |
|
|
-- Bus2IP_BE -- Byte enables for the data bus
|
2858 |
|
|
-- Bus2IP_CS -- Chip select for the transcations
|
2859 |
|
|
-- Bus2IP_RdCE -- Chip enables for the read
|
2860 |
|
|
-- Bus2IP_WrCE -- Chip enables for the write
|
2861 |
|
|
-- Bus2IP_Data -- Write data bus to the User IP
|
2862 |
|
|
-- IP2Bus_Data -- Input Read Data bus from the User IP
|
2863 |
|
|
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
|
2864 |
|
|
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
|
2865 |
|
|
-- IP2Bus_Error -- Error signal from the IP
|
2866 |
|
|
-------------------------------------------------------------------------------
|
2867 |
|
|
|
2868 |
|
|
entity axi_lite_ipif is
|
2869 |
|
|
generic (
|
2870 |
|
|
|
2871 |
|
|
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
|
2872 |
|
|
C_S_AXI_ADDR_WIDTH : integer := 32;
|
2873 |
|
|
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
|
2874 |
|
|
C_USE_WSTRB : integer := 0;
|
2875 |
|
|
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
|
2876 |
|
|
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
|
2877 |
|
|
(
|
2878 |
|
|
X"0000_0000_7000_0000", -- IP user0 base address
|
2879 |
|
|
X"0000_0000_7000_00FF", -- IP user0 high address
|
2880 |
|
|
X"0000_0000_7000_0100", -- IP user1 base address
|
2881 |
|
|
X"0000_0000_7000_01FF" -- IP user1 high address
|
2882 |
|
|
);
|
2883 |
|
|
|
2884 |
|
|
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
|
2885 |
|
|
(
|
2886 |
|
|
4, -- User0 CE Number
|
2887 |
|
|
12 -- User1 CE Number
|
2888 |
|
|
);
|
2889 |
|
|
C_FAMILY : string := "virtex6"
|
2890 |
|
|
);
|
2891 |
|
|
port (
|
2892 |
|
|
|
2893 |
|
|
--System signals
|
2894 |
|
|
S_AXI_ACLK : in std_logic;
|
2895 |
|
|
S_AXI_ARESETN : in std_logic;
|
2896 |
|
|
S_AXI_AWADDR : in std_logic_vector
|
2897 |
|
|
(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
2898 |
|
|
S_AXI_AWVALID : in std_logic;
|
2899 |
|
|
S_AXI_AWREADY : out std_logic;
|
2900 |
|
|
S_AXI_WDATA : in std_logic_vector
|
2901 |
|
|
(C_S_AXI_DATA_WIDTH-1 downto 0);
|
2902 |
|
|
S_AXI_WSTRB : in std_logic_vector
|
2903 |
|
|
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
2904 |
|
|
S_AXI_WVALID : in std_logic;
|
2905 |
|
|
S_AXI_WREADY : out std_logic;
|
2906 |
|
|
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
2907 |
|
|
S_AXI_BVALID : out std_logic;
|
2908 |
|
|
S_AXI_BREADY : in std_logic;
|
2909 |
|
|
S_AXI_ARADDR : in std_logic_vector
|
2910 |
|
|
(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
2911 |
|
|
S_AXI_ARVALID : in std_logic;
|
2912 |
|
|
S_AXI_ARREADY : out std_logic;
|
2913 |
|
|
S_AXI_RDATA : out std_logic_vector
|
2914 |
|
|
(C_S_AXI_DATA_WIDTH-1 downto 0);
|
2915 |
|
|
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
2916 |
|
|
S_AXI_RVALID : out std_logic;
|
2917 |
|
|
S_AXI_RREADY : in std_logic;
|
2918 |
|
|
-- Controls to the IP/IPIF modules
|
2919 |
|
|
Bus2IP_Clk : out std_logic;
|
2920 |
|
|
Bus2IP_Resetn : out std_logic;
|
2921 |
|
|
Bus2IP_Addr : out std_logic_vector
|
2922 |
|
|
((C_S_AXI_ADDR_WIDTH-1) downto 0);
|
2923 |
|
|
Bus2IP_RNW : out std_logic;
|
2924 |
|
|
Bus2IP_BE : out std_logic_vector
|
2925 |
|
|
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
|
2926 |
|
|
Bus2IP_CS : out std_logic_vector
|
2927 |
|
|
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
|
2928 |
|
|
Bus2IP_RdCE : out std_logic_vector
|
2929 |
|
|
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
|
2930 |
|
|
Bus2IP_WrCE : out std_logic_vector
|
2931 |
|
|
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
|
2932 |
|
|
Bus2IP_Data : out std_logic_vector
|
2933 |
|
|
((C_S_AXI_DATA_WIDTH-1) downto 0);
|
2934 |
|
|
IP2Bus_Data : in std_logic_vector
|
2935 |
|
|
((C_S_AXI_DATA_WIDTH-1) downto 0);
|
2936 |
|
|
IP2Bus_WrAck : in std_logic;
|
2937 |
|
|
IP2Bus_RdAck : in std_logic;
|
2938 |
|
|
IP2Bus_Error : in std_logic
|
2939 |
|
|
|
2940 |
|
|
);
|
2941 |
|
|
|
2942 |
|
|
end axi_lite_ipif;
|
2943 |
|
|
|
2944 |
|
|
-------------------------------------------------------------------------------
|
2945 |
|
|
-- Architecture
|
2946 |
|
|
-------------------------------------------------------------------------------
|
2947 |
|
|
|
2948 |
|
|
architecture imp of axi_lite_ipif is
|
2949 |
|
|
----------------------------------------------------------------------------------
|
2950 |
|
|
-- below attributes are added to reduce the synth warnings in Vivado tool
|
2951 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
2952 |
|
|
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
|
2953 |
|
|
----------------------------------------------------------------------------------
|
2954 |
|
|
|
2955 |
|
|
-------------------------------------------------------------------------------
|
2956 |
|
|
-- Begin architecture logic
|
2957 |
|
|
-------------------------------------------------------------------------------
|
2958 |
|
|
begin
|
2959 |
|
|
|
2960 |
|
|
-------------------------------------------------------------------------------
|
2961 |
|
|
-- Slave Attachment
|
2962 |
|
|
-------------------------------------------------------------------------------
|
2963 |
|
|
|
2964 |
|
|
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment
|
2965 |
|
|
generic map(
|
2966 |
|
|
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
|
2967 |
|
|
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
|
2968 |
|
|
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
|
2969 |
|
|
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
|
2970 |
|
|
C_USE_WSTRB => C_USE_WSTRB,
|
2971 |
|
|
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
|
2972 |
|
|
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
|
2973 |
|
|
C_FAMILY => C_FAMILY
|
2974 |
|
|
)
|
2975 |
|
|
port map(
|
2976 |
|
|
-- AXI signals
|
2977 |
|
|
S_AXI_ACLK => S_AXI_ACLK,
|
2978 |
|
|
S_AXI_ARESETN => S_AXI_ARESETN,
|
2979 |
|
|
S_AXI_AWADDR => S_AXI_AWADDR,
|
2980 |
|
|
S_AXI_AWVALID => S_AXI_AWVALID,
|
2981 |
|
|
S_AXI_AWREADY => S_AXI_AWREADY,
|
2982 |
|
|
S_AXI_WDATA => S_AXI_WDATA,
|
2983 |
|
|
S_AXI_WSTRB => S_AXI_WSTRB,
|
2984 |
|
|
S_AXI_WVALID => S_AXI_WVALID,
|
2985 |
|
|
S_AXI_WREADY => S_AXI_WREADY,
|
2986 |
|
|
S_AXI_BRESP => S_AXI_BRESP,
|
2987 |
|
|
S_AXI_BVALID => S_AXI_BVALID,
|
2988 |
|
|
S_AXI_BREADY => S_AXI_BREADY,
|
2989 |
|
|
S_AXI_ARADDR => S_AXI_ARADDR,
|
2990 |
|
|
S_AXI_ARVALID => S_AXI_ARVALID,
|
2991 |
|
|
S_AXI_ARREADY => S_AXI_ARREADY,
|
2992 |
|
|
S_AXI_RDATA => S_AXI_RDATA,
|
2993 |
|
|
S_AXI_RRESP => S_AXI_RRESP,
|
2994 |
|
|
S_AXI_RVALID => S_AXI_RVALID,
|
2995 |
|
|
S_AXI_RREADY => S_AXI_RREADY,
|
2996 |
|
|
-- IPIC signals
|
2997 |
|
|
Bus2IP_Clk => Bus2IP_Clk,
|
2998 |
|
|
Bus2IP_Resetn => Bus2IP_Resetn,
|
2999 |
|
|
Bus2IP_Addr => Bus2IP_Addr,
|
3000 |
|
|
Bus2IP_RNW => Bus2IP_RNW,
|
3001 |
|
|
Bus2IP_BE => Bus2IP_BE,
|
3002 |
|
|
Bus2IP_CS => Bus2IP_CS,
|
3003 |
|
|
Bus2IP_RdCE => Bus2IP_RdCE,
|
3004 |
|
|
Bus2IP_WrCE => Bus2IP_WrCE,
|
3005 |
|
|
Bus2IP_Data => Bus2IP_Data,
|
3006 |
|
|
IP2Bus_Data => IP2Bus_Data,
|
3007 |
|
|
IP2Bus_WrAck => IP2Bus_WrAck,
|
3008 |
|
|
IP2Bus_RdAck => IP2Bus_RdAck,
|
3009 |
|
|
IP2Bus_Error => IP2Bus_Error
|
3010 |
|
|
);
|
3011 |
|
|
|
3012 |
|
|
end imp;
|
3013 |
|
|
|
3014 |
|
|
|