1 |
2 |
vv_gulyaev |
-- dynshreg_i_f - entity / architecture pair
|
2 |
|
|
-------------------------------------------------------------------------------
|
3 |
|
|
--
|
4 |
|
|
-- *************************************************************************
|
5 |
|
|
-- ** **
|
6 |
|
|
-- ** DISCLAIMER OF LIABILITY **
|
7 |
|
|
-- ** **
|
8 |
|
|
-- ** This text/file contains proprietary, confidential **
|
9 |
|
|
-- ** information of Xilinx, Inc., is distributed under **
|
10 |
|
|
-- ** license from Xilinx, Inc., and may be used, copied **
|
11 |
|
|
-- ** and/or disclosed only pursuant to the terms of a valid **
|
12 |
|
|
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
|
13 |
|
|
-- ** grants you a license to use this text/file solely for **
|
14 |
|
|
-- ** design, simulation, implementation and creation of **
|
15 |
|
|
-- ** design files limited to Xilinx devices or technologies. **
|
16 |
|
|
-- ** Use with non-Xilinx devices or technologies is expressly **
|
17 |
|
|
-- ** prohibited and immediately terminates your license unless **
|
18 |
|
|
-- ** covered by a separate agreement. **
|
19 |
|
|
-- ** **
|
20 |
|
|
-- ** Xilinx is providing this design, code, or information **
|
21 |
|
|
-- ** "as-is" solely for use in developing programs and **
|
22 |
|
|
-- ** solutions for Xilinx devices, with no obligation on the **
|
23 |
|
|
-- ** part of Xilinx to provide support. By providing this design, **
|
24 |
|
|
-- ** code, or information as one possible implementation of **
|
25 |
|
|
-- ** this feature, application or standard, Xilinx is making no **
|
26 |
|
|
-- ** representation that this implementation is free from any **
|
27 |
|
|
-- ** claims of infringement. You are responsible for obtaining **
|
28 |
|
|
-- ** any rights you may require for your implementation. **
|
29 |
|
|
-- ** Xilinx expressly disclaims any warranty whatsoever with **
|
30 |
|
|
-- ** respect to the adequacy of the implementation, including **
|
31 |
|
|
-- ** but not limited to any warranties or representations that this **
|
32 |
|
|
-- ** implementation is free from claims of infringement, implied **
|
33 |
|
|
-- ** warranties of merchantability or fitness for a particular **
|
34 |
|
|
-- ** purpose. **
|
35 |
|
|
-- ** **
|
36 |
|
|
-- ** Xilinx products are not intended for use in life support **
|
37 |
|
|
-- ** appliances, devices, or systems. Use in such applications is **
|
38 |
|
|
-- ** expressly prohibited. **
|
39 |
|
|
-- ** **
|
40 |
|
|
-- ** Any modifications that are made to the Source Code are **
|
41 |
|
|
-- ** done at the user’s sole risk and will be unsupported. **
|
42 |
|
|
-- ** The Xilinx Support Hotline does not have access to source **
|
43 |
|
|
-- ** code and therefore cannot answer specific questions related **
|
44 |
|
|
-- ** to source HDL. The Xilinx Hotline support of original source **
|
45 |
|
|
-- ** code IP shall only address issues and questions related **
|
46 |
|
|
-- ** to the standard Netlist version of the core (and thus **
|
47 |
|
|
-- ** indirectly, the original core source). **
|
48 |
|
|
-- ** **
|
49 |
|
|
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
|
50 |
|
|
-- ** **
|
51 |
|
|
-- ** This copyright and support notice must be retained as part **
|
52 |
|
|
-- ** of this text at all times. **
|
53 |
|
|
-- ** **
|
54 |
|
|
-- *************************************************************************
|
55 |
|
|
--
|
56 |
|
|
-------------------------------------------------------------------------------
|
57 |
|
|
-- Filename: dynshreg_i_f.vhd
|
58 |
|
|
--
|
59 |
|
|
-- Description: This module implements a dynamic shift register with clock
|
60 |
|
|
-- enable. (Think, for example, of the function of the SRL16E.)
|
61 |
|
|
-- The width and depth of the shift register are selectable
|
62 |
|
|
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
|
63 |
|
|
-- allows the implementation to be tailored to the target
|
64 |
|
|
-- FPGA family. An inferred implementation is used if C_FAMILY
|
65 |
|
|
-- is "nofamily" (the default) or if synthesis will not produce
|
66 |
|
|
-- an optimal implementation. Otherwise, a structural
|
67 |
|
|
-- implementation will be generated.
|
68 |
|
|
--
|
69 |
|
|
-- There is no restriction on the values of C_WIDTH and
|
70 |
|
|
-- C_DEPTH and, in particular, the C_DEPTH does not have
|
71 |
|
|
-- to be a power of two.
|
72 |
|
|
--
|
73 |
|
|
-- This version allows the client to specify the initial value
|
74 |
|
|
-- of the contents of the shift register, as applied
|
75 |
|
|
-- during configuration.
|
76 |
|
|
--
|
77 |
|
|
--
|
78 |
|
|
-- VHDL-Standard: VHDL'93
|
79 |
|
|
-------------------------------------------------------------------------------
|
80 |
|
|
-- Naming Conventions:
|
81 |
|
|
-- active low signals: "*_n"
|
82 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
83 |
|
|
-- reset signals: "rst", "rst_n"
|
84 |
|
|
-- generics: "C_*"
|
85 |
|
|
-- user defined types: "*_TYPE"
|
86 |
|
|
-- state machine next state: "*_ns"
|
87 |
|
|
-- state machine current state: "*_cs"
|
88 |
|
|
-- combinatorial signals: "*_com"
|
89 |
|
|
-- pipelined or register delay signals: "*_d#"
|
90 |
|
|
-- counter signals: "*cnt*"
|
91 |
|
|
-- clock enable signals: "*_ce"
|
92 |
|
|
-- internal version of output port "*_i"
|
93 |
|
|
-- device pins: "*_pin"
|
94 |
|
|
-- ports: - Names begin with Uppercase
|
95 |
|
|
-- processes: "*_PROCESS"
|
96 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
97 |
|
|
-------------------------------------------------------------------------------
|
98 |
|
|
-- predecessor value by # clks: "*_p#"
|
99 |
|
|
|
100 |
|
|
---(
|
101 |
|
|
library ieee;
|
102 |
|
|
use ieee.std_logic_1164.all;
|
103 |
|
|
use ieee.numeric_std.UNSIGNED;
|
104 |
|
|
use ieee.numeric_std.TO_INTEGER;
|
105 |
|
|
--
|
106 |
|
|
library lib_pkg_v1_0_2;
|
107 |
|
|
use lib_pkg_v1_0_2.all;
|
108 |
|
|
use lib_pkg_v1_0_2.lib_pkg.clog2;
|
109 |
|
|
|
110 |
|
|
|
111 |
|
|
--------------------------------------------------------------------------------
|
112 |
|
|
-- Explanations of generics and ports regarding aspects that may not be obvious.
|
113 |
|
|
--
|
114 |
|
|
-- C_DWIDTH
|
115 |
|
|
--------
|
116 |
|
|
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
|
117 |
|
|
-- natural or preferrable way of excluding a dynamic shift register
|
118 |
|
|
-- in a client than using a VHDL Generate statement. However, this usage is not
|
119 |
|
|
-- tested, and the user should expect that some VHDL tools will be deficient
|
120 |
|
|
-- with respect to handling this properly.
|
121 |
|
|
--
|
122 |
|
|
-- C_INIT_VALUE
|
123 |
|
|
---------------
|
124 |
|
|
-- C_INIT_VALUE can be used to specify the initial values of the elements
|
125 |
|
|
-- in the dynamic shift register, i.e. the values to be present after config-
|
126 |
|
|
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
|
127 |
|
|
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
|
128 |
|
|
-- is replicated as many times as needed (possibly fractionally the last time)
|
129 |
|
|
-- to form a full initial value that is the size of the shift register.
|
130 |
|
|
-- So, if C_INIT_VALUE is left at its default value--an array of size one
|
131 |
|
|
-- whose value is '0'--the shift register will initialize with all bits at
|
132 |
|
|
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
|
133 |
|
|
-- null (size zero) array.
|
134 |
|
|
-- When determined according to the rules outlined above, the full
|
135 |
|
|
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
|
136 |
|
|
-- is allocated to the addresses of the dynamic shift register in this
|
137 |
|
|
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
|
138 |
|
|
-- the corresponding indices at address 0, the second C_DWIDTH values
|
139 |
|
|
-- assigned to address 1, and so forth.
|
140 |
|
|
-- Please note that the shift register is not resettable after configuration.
|
141 |
|
|
--
|
142 |
|
|
-- Addr
|
143 |
|
|
----
|
144 |
|
|
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
|
145 |
|
|
-- the most recently shifted-in element to appear at Dout, Addr=1
|
146 |
|
|
-- the second most recently shifted in element, etc. If C_DEPTH is not
|
147 |
|
|
-- a power of two, then not all of the values of Addr correspond to an
|
148 |
|
|
-- element in the shift register. When such an address is applied, the value
|
149 |
|
|
-- of Dout is undefined until a valid address is established.
|
150 |
|
|
--------------------------------------------------------------------------------
|
151 |
|
|
entity dynshreg_i_f is
|
152 |
|
|
generic (
|
153 |
|
|
C_DEPTH : positive := 32;
|
154 |
|
|
C_DWIDTH : natural := 1;
|
155 |
|
|
C_INIT_VALUE : bit_vector := "0";
|
156 |
|
|
C_FAMILY : string := "nofamily"
|
157 |
|
|
);
|
158 |
|
|
port (
|
159 |
|
|
Clk : in std_logic;
|
160 |
|
|
Clken : in std_logic;
|
161 |
|
|
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
|
162 |
|
|
Din : in std_logic_vector(0 to C_DWIDTH-1);
|
163 |
|
|
Dout : out std_logic_vector(0 to C_DWIDTH-1)
|
164 |
|
|
);
|
165 |
|
|
end dynshreg_i_f;
|
166 |
|
|
|
167 |
|
|
|
168 |
|
|
architecture behavioral of dynshreg_i_f is
|
169 |
|
|
|
170 |
|
|
constant USE_INFERRED : boolean := true;
|
171 |
|
|
type bv2sl_type is array(bit) of std_logic;
|
172 |
|
|
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
|
173 |
|
|
function min(a, b: natural) return natural is
|
174 |
|
|
begin
|
175 |
|
|
if a<b then return a; else return b; end if;
|
176 |
|
|
end min;
|
177 |
|
|
|
178 |
|
|
--
|
179 |
|
|
------------------------------------------------------------------------------
|
180 |
|
|
-- Function used to establish the full initial value. (See the comments for
|
181 |
|
|
-- C_INIT_VALUE, above.)
|
182 |
|
|
------------------------------------------------------------------------------
|
183 |
|
|
function full_initial_value(w : natural; d : positive; v : bit_vector
|
184 |
|
|
) return bit_vector is
|
185 |
|
|
variable r : bit_vector(0 to w*d-1);
|
186 |
|
|
variable i, j : natural;
|
187 |
|
|
-- i - the index where filling of r continues
|
188 |
|
|
-- j - the amount to fill on the cur. iteration of the while loop
|
189 |
|
|
begin
|
190 |
|
|
if w = 0 then null; -- Handle the case where the shift reg width is zero
|
191 |
|
|
elsif v'length = 0 then r := (others => '0');
|
192 |
|
|
else
|
193 |
|
|
i := 0;
|
194 |
|
|
while i /= r'length loop
|
195 |
|
|
j := min(v'length, r'length-i);
|
196 |
|
|
r(i to i+j-1) := v(0 to j-1);
|
197 |
|
|
i := i+j;
|
198 |
|
|
end loop;
|
199 |
|
|
end if;
|
200 |
|
|
return r;
|
201 |
|
|
end full_initial_value;
|
202 |
|
|
|
203 |
|
|
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
|
204 |
|
|
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
|
205 |
|
|
|
206 |
|
|
-- As of I.32, XST is not infering optimal dynamic shift registers for
|
207 |
|
|
-- depths not a power of two (by not taking advantage of don't care
|
208 |
|
|
-- at output when address not within the range of the depth)
|
209 |
|
|
-- or a power of two less than the native SRL depth (by building shift
|
210 |
|
|
-- register out of discrete FFs and LUTs instead of SRLs).
|
211 |
|
|
|
212 |
|
|
----------------------------------------------------------------------------
|
213 |
|
|
-- Unisim components declared locally for maximum avoidance of default
|
214 |
|
|
-- binding and vcomponents version issues.
|
215 |
|
|
----------------------------------------------------------------------------
|
216 |
|
|
|
217 |
|
|
|
218 |
|
|
begin
|
219 |
|
|
|
220 |
|
|
INFERRED_GEN : if USE_INFERRED = true generate
|
221 |
|
|
--
|
222 |
|
|
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
|
223 |
|
|
--
|
224 |
|
|
function fill_data(w: natural; d: positive; v: bit_vector
|
225 |
|
|
) return dataType is
|
226 |
|
|
variable r : dataType;
|
227 |
|
|
begin
|
228 |
|
|
for i in 0 to d-1 loop
|
229 |
|
|
for j in 0 to w-1 loop
|
230 |
|
|
r(i)(j) := bv2sl(v(i*w+j));
|
231 |
|
|
end loop;
|
232 |
|
|
end loop;
|
233 |
|
|
return r;
|
234 |
|
|
end fill_data;
|
235 |
|
|
|
236 |
|
|
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
|
237 |
|
|
--
|
238 |
|
|
begin
|
239 |
|
|
process(Clk)
|
240 |
|
|
begin
|
241 |
|
|
if Clk'event and Clk = '1' then
|
242 |
|
|
if Clken = '1' then
|
243 |
|
|
data <= Din & data(0 to C_DEPTH-2);
|
244 |
|
|
end if;
|
245 |
|
|
end if;
|
246 |
|
|
end process;
|
247 |
|
|
|
248 |
|
|
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
|
249 |
|
|
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
|
250 |
|
|
else
|
251 |
|
|
(others => '-');
|
252 |
|
|
end generate INFERRED_GEN;
|
253 |
|
|
---)
|
254 |
|
|
|
255 |
|
|
end behavioral;
|
256 |
|
|
|
257 |
|
|
|
258 |
|
|
-------------------------------------------------------------------------------
|
259 |
|
|
-- uartlite_tx - entity/architecture pair
|
260 |
|
|
-------------------------------------------------------------------------------
|
261 |
|
|
--
|
262 |
|
|
-- *******************************************************************
|
263 |
|
|
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
|
264 |
|
|
-- -- ** *
|
265 |
|
|
-- -- ** This file contains confidential and proprietary information *
|
266 |
|
|
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
|
267 |
|
|
-- -- ** international copyright and other intellectual property *
|
268 |
|
|
-- -- ** laws. *
|
269 |
|
|
-- -- ** *
|
270 |
|
|
-- -- ** DISCLAIMER *
|
271 |
|
|
-- -- ** This disclaimer is not a license and does not grant any *
|
272 |
|
|
-- -- ** rights to the materials distributed herewith. Except as *
|
273 |
|
|
-- -- ** otherwise provided in a valid license issued to you by *
|
274 |
|
|
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
|
275 |
|
|
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
276 |
|
|
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
277 |
|
|
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
278 |
|
|
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
279 |
|
|
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
280 |
|
|
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
|
281 |
|
|
-- -- ** including negligence, or under any other theory of *
|
282 |
|
|
-- -- ** liability) for any loss or damage of any kind or nature *
|
283 |
|
|
-- -- ** related to, arising under or in connection with these *
|
284 |
|
|
-- -- ** materials, including for any direct, or any indirect, *
|
285 |
|
|
-- -- ** special, incidental, or consequential loss or damage *
|
286 |
|
|
-- -- ** (including loss of data, profits, goodwill, or any type of *
|
287 |
|
|
-- -- ** loss or damage suffered as a result of any action brought *
|
288 |
|
|
-- -- ** by a third party) even if such damage or loss was *
|
289 |
|
|
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
|
290 |
|
|
-- -- ** possibility of the same. *
|
291 |
|
|
-- -- ** *
|
292 |
|
|
-- -- ** CRITICAL APPLICATIONS *
|
293 |
|
|
-- -- ** Xilinx products are not designed or intended to be fail- *
|
294 |
|
|
-- -- ** safe, or for use in any application requiring fail-safe *
|
295 |
|
|
-- -- ** performance, such as life-support or safety devices or *
|
296 |
|
|
-- -- ** systems, Class III medical devices, nuclear facilities, *
|
297 |
|
|
-- -- ** applications related to the deployment of airbags, or any *
|
298 |
|
|
-- -- ** other applications that could lead to death, personal *
|
299 |
|
|
-- -- ** injury, or severe property or environmental damage *
|
300 |
|
|
-- -- ** (individually and collectively, "Critical *
|
301 |
|
|
-- -- ** Applications"). Customer assumes the sole risk and *
|
302 |
|
|
-- -- ** liability of any use of Xilinx products in Critical *
|
303 |
|
|
-- -- ** Applications, subject only to applicable laws and *
|
304 |
|
|
-- -- ** regulations governing limitations on product liability. *
|
305 |
|
|
-- -- ** *
|
306 |
|
|
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
307 |
|
|
-- -- ** PART OF THIS FILE AT ALL TIMES. *
|
308 |
|
|
-- *******************************************************************
|
309 |
|
|
--
|
310 |
|
|
-------------------------------------------------------------------------------
|
311 |
|
|
-- Filename: uartlite_tx.vhd
|
312 |
|
|
-- Version: v2.0
|
313 |
|
|
-- Description: UART Lite Transmit Interface Module
|
314 |
|
|
--
|
315 |
|
|
-- VHDL-Standard: VHDL'93
|
316 |
|
|
-------------------------------------------------------------------------------
|
317 |
|
|
-------------------------------------------------------------------------------
|
318 |
|
|
-- Naming Conventions:
|
319 |
|
|
-- active low signals: "*_n"
|
320 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
321 |
|
|
-- reset signals: "rst", "rst_n"
|
322 |
|
|
-- generics: "C_*"
|
323 |
|
|
-- user defined types: "*_TYPE"
|
324 |
|
|
-- state machine next state: "*_ns"
|
325 |
|
|
-- state machine current state: "*_cs"
|
326 |
|
|
-- combinatorial signals: "*_com"
|
327 |
|
|
-- pipelined or register delay signals: "*_d#"
|
328 |
|
|
-- counter signals: "*cnt*"
|
329 |
|
|
-- clock enable signals: "*_ce"
|
330 |
|
|
-- internal version of output port "*_i"
|
331 |
|
|
-- device pins: "*_pin"
|
332 |
|
|
-- ports: - Names begin with Uppercase
|
333 |
|
|
-- processes: "*_PROCESS"
|
334 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
335 |
|
|
-------------------------------------------------------------------------------
|
336 |
|
|
library IEEE;
|
337 |
|
|
use IEEE.std_logic_1164.all;
|
338 |
|
|
use IEEE.numeric_std.UNSIGNED;
|
339 |
|
|
use IEEE.numeric_std.to_unsigned;
|
340 |
|
|
use IEEE.numeric_std."-";
|
341 |
|
|
|
342 |
|
|
library lib_srl_fifo_v1_0_2;
|
343 |
|
|
-- dynshreg_i_f refered from proc_common_v4_0_20_a
|
344 |
|
|
library axi_uartlite_v2_0_19;
|
345 |
|
|
-- uartlite_core refered from axi_uartlite_v2_0_19
|
346 |
|
|
use axi_uartlite_v2_0_19.all;
|
347 |
|
|
-- srl_fifo_f refered from proc_common_v4_0_20_a
|
348 |
|
|
use lib_srl_fifo_v1_0_2.srl_fifo_f;
|
349 |
|
|
|
350 |
|
|
-------------------------------------------------------------------------------
|
351 |
|
|
-- Port Declaration
|
352 |
|
|
-------------------------------------------------------------------------------
|
353 |
|
|
-------------------------------------------------------------------------------
|
354 |
|
|
-- Definition of Generics :
|
355 |
|
|
-------------------------------------------------------------------------------
|
356 |
|
|
-- UART Lite generics
|
357 |
|
|
-- C_DATA_BITS -- The number of data bits in the serial frame
|
358 |
|
|
-- C_USE_PARITY -- Determines whether parity is used or not
|
359 |
|
|
-- C_ODD_PARITY -- If parity is used determines whether parity
|
360 |
|
|
-- is even or odd
|
361 |
|
|
-- System generics
|
362 |
|
|
-- C_FAMILY -- Xilinx FPGA Family
|
363 |
|
|
-------------------------------------------------------------------------------
|
364 |
|
|
-------------------------------------------------------------------------------
|
365 |
|
|
-- Definition of Ports :
|
366 |
|
|
-------------------------------------------------------------------------------
|
367 |
|
|
-- System Signals
|
368 |
|
|
-- Clk -- Clock signal
|
369 |
|
|
-- Rst -- Reset signal
|
370 |
|
|
-- UART Lite interface
|
371 |
|
|
-- TX -- Transmit Data
|
372 |
|
|
-- Internal UART interface signals
|
373 |
|
|
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
|
374 |
|
|
-- Write_TX_FIFO -- Write transmit FIFO
|
375 |
|
|
-- Reset_TX_FIFO -- Reset transmit FIFO
|
376 |
|
|
-- TX_Data -- Transmit data input
|
377 |
|
|
-- TX_Buffer_Full -- Transmit buffer full
|
378 |
|
|
-- TX_Buffer_Empty -- Transmit buffer empty
|
379 |
|
|
-------------------------------------------------------------------------------
|
380 |
|
|
-------------------------------------------------------------------------------
|
381 |
|
|
-- Entity Section
|
382 |
|
|
-------------------------------------------------------------------------------
|
383 |
|
|
entity uartlite_tx is
|
384 |
|
|
generic
|
385 |
|
|
(
|
386 |
|
|
C_FAMILY : string := "virtex7";
|
387 |
|
|
C_DATA_BITS : integer range 5 to 8 := 8;
|
388 |
|
|
C_USE_PARITY : integer range 0 to 1 := 0;
|
389 |
|
|
C_ODD_PARITY : integer range 0 to 1 := 0
|
390 |
|
|
);
|
391 |
|
|
port
|
392 |
|
|
(
|
393 |
|
|
Clk : in std_logic;
|
394 |
|
|
Reset : in std_logic;
|
395 |
|
|
EN_16x_Baud : in std_logic;
|
396 |
|
|
TX : out std_logic;
|
397 |
|
|
Write_TX_FIFO : in std_logic;
|
398 |
|
|
Reset_TX_FIFO : in std_logic;
|
399 |
|
|
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
|
400 |
|
|
TX_Buffer_Full : out std_logic;
|
401 |
|
|
TX_Buffer_Empty : out std_logic
|
402 |
|
|
);
|
403 |
|
|
end entity uartlite_tx;
|
404 |
|
|
|
405 |
|
|
-------------------------------------------------------------------------------
|
406 |
|
|
-- Architecture Section
|
407 |
|
|
-------------------------------------------------------------------------------
|
408 |
|
|
architecture RTL of uartlite_tx is
|
409 |
|
|
-- Pragma Added to supress synth warnings
|
410 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
411 |
|
|
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
|
412 |
|
|
|
413 |
|
|
type bo2sl_type is array(boolean) of std_logic;
|
414 |
|
|
constant bo2sl : bo2sl_type := (false => '0', true => '1');
|
415 |
|
|
|
416 |
|
|
-------------------------------------------------------------------------
|
417 |
|
|
-- Constant Declarations
|
418 |
|
|
-------------------------------------------------------------------------
|
419 |
|
|
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
|
420 |
|
|
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
|
421 |
|
|
|
422 |
|
|
-------------------------------------------------------------------------
|
423 |
|
|
-- Signal Declarations
|
424 |
|
|
-------------------------------------------------------------------------
|
425 |
|
|
signal parity : std_logic;
|
426 |
|
|
signal tx_Run1 : std_logic;
|
427 |
|
|
signal select_Parity : std_logic;
|
428 |
|
|
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
|
429 |
|
|
signal div16 : std_logic;
|
430 |
|
|
signal tx_Data_Enable : std_logic;
|
431 |
|
|
signal tx_Start : std_logic;
|
432 |
|
|
signal tx_DataBits : std_logic;
|
433 |
|
|
signal tx_Run : std_logic;
|
434 |
|
|
signal mux_sel : std_logic_vector(0 to 2);
|
435 |
|
|
signal mux_sel_is_zero : std_logic;
|
436 |
|
|
signal mux_01 : std_logic;
|
437 |
|
|
signal mux_23 : std_logic;
|
438 |
|
|
signal mux_45 : std_logic;
|
439 |
|
|
signal mux_67 : std_logic;
|
440 |
|
|
signal mux_0123 : std_logic;
|
441 |
|
|
signal mux_4567 : std_logic;
|
442 |
|
|
signal mux_Out : std_logic;
|
443 |
|
|
signal serial_Data : std_logic;
|
444 |
|
|
signal fifo_Read : std_logic;
|
445 |
|
|
signal fifo_Data_Present : std_logic := '0';
|
446 |
|
|
signal fifo_Data_Empty : std_logic;
|
447 |
|
|
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
|
448 |
|
|
signal fifo_wr : std_logic;
|
449 |
|
|
signal fifo_rd : std_logic;
|
450 |
|
|
signal tx_buffer_full_i : std_logic;
|
451 |
|
|
signal TX_FIFO_Reset : std_logic;
|
452 |
|
|
|
453 |
|
|
begin -- architecture IMP
|
454 |
|
|
|
455 |
|
|
---------------------------------------------------------------------------
|
456 |
|
|
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
|
457 |
|
|
-- gets shifted for 16 times(as Addr = 15) when
|
458 |
|
|
-- EN_16x_Baud is high.
|
459 |
|
|
---------------------------------------------------------------------------
|
460 |
|
|
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0_19.dynshreg_i_f
|
461 |
|
|
generic map
|
462 |
|
|
(
|
463 |
|
|
C_DEPTH => 16,
|
464 |
|
|
C_DWIDTH => 1,
|
465 |
|
|
C_INIT_VALUE => X"8000",
|
466 |
|
|
C_FAMILY => C_FAMILY
|
467 |
|
|
)
|
468 |
|
|
port map
|
469 |
|
|
(
|
470 |
|
|
Clk => Clk,
|
471 |
|
|
Clken => EN_16x_Baud,
|
472 |
|
|
Addr => "1111",
|
473 |
|
|
Din(0) => div16,
|
474 |
|
|
Dout(0) => div16
|
475 |
|
|
);
|
476 |
|
|
|
477 |
|
|
------------------------------------------------------------------------
|
478 |
|
|
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
|
479 |
|
|
-- EN_16x_Baud is 1. It will deasserted in the
|
480 |
|
|
-- next clock cycle.
|
481 |
|
|
------------------------------------------------------------------------
|
482 |
|
|
TX_DATA_ENABLE_DFF: Process (Clk) is
|
483 |
|
|
begin
|
484 |
|
|
if (Clk'event and Clk = '1') then -- rising clock edge
|
485 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
486 |
|
|
tx_Data_Enable <= '0';
|
487 |
|
|
else
|
488 |
|
|
if (tx_Data_Enable = '1') then
|
489 |
|
|
tx_Data_Enable <= '0';
|
490 |
|
|
elsif (EN_16x_Baud = '1') then
|
491 |
|
|
tx_Data_Enable <= div16;
|
492 |
|
|
end if;
|
493 |
|
|
end if;
|
494 |
|
|
end if;
|
495 |
|
|
end process TX_DATA_ENABLE_DFF;
|
496 |
|
|
|
497 |
|
|
------------------------------------------------------------------------
|
498 |
|
|
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
|
499 |
|
|
------------------------------------------------------------------------
|
500 |
|
|
TX_START_DFF : process (Clk) is
|
501 |
|
|
begin
|
502 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
503 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
504 |
|
|
tx_Start <= '0';
|
505 |
|
|
else
|
506 |
|
|
tx_Start <= (not(tx_Run) and (tx_Start or
|
507 |
|
|
(fifo_Data_Present and tx_Data_Enable)));
|
508 |
|
|
end if;
|
509 |
|
|
end if;
|
510 |
|
|
end process TX_START_DFF;
|
511 |
|
|
|
512 |
|
|
--------------------------------------------------------------------------
|
513 |
|
|
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
|
514 |
|
|
--------------------------------------------------------------------------
|
515 |
|
|
TX_DATA_DFF : process (Clk) is
|
516 |
|
|
begin
|
517 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
518 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
519 |
|
|
tx_DataBits <= '0';
|
520 |
|
|
else
|
521 |
|
|
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
|
522 |
|
|
(tx_Start and tx_Data_Enable)));
|
523 |
|
|
end if;
|
524 |
|
|
end if;
|
525 |
|
|
end process TX_DATA_DFF;
|
526 |
|
|
|
527 |
|
|
-------------------------------------------------------------------------
|
528 |
|
|
-- COUNTER : If mux_sel is zero then reload with the init value else if
|
529 |
|
|
-- tx_DataBits = '1', decrement
|
530 |
|
|
-------------------------------------------------------------------------
|
531 |
|
|
COUNTER : process (Clk) is
|
532 |
|
|
begin -- process Mux_Addr_DFF
|
533 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
534 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
535 |
|
|
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
|
536 |
|
|
mux_sel'length));
|
537 |
|
|
elsif (tx_Data_Enable = '1') then
|
538 |
|
|
if (mux_sel_is_zero = '1') then
|
539 |
|
|
mux_sel <= MUX_SEL_INIT;
|
540 |
|
|
elsif (tx_DataBits = '1') then
|
541 |
|
|
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
|
542 |
|
|
end if;
|
543 |
|
|
end if;
|
544 |
|
|
end if;
|
545 |
|
|
end process COUNTER;
|
546 |
|
|
|
547 |
|
|
------------------------------------------------------------------------
|
548 |
|
|
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
|
549 |
|
|
------------------------------------------------------------------------
|
550 |
|
|
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
|
551 |
|
|
|
552 |
|
|
--------------------------------------------------------------------------
|
553 |
|
|
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
|
554 |
|
|
-- data has been transmitted
|
555 |
|
|
--------------------------------------------------------------------------
|
556 |
|
|
FIFO_READ_DFF : process (Clk) is
|
557 |
|
|
begin -- process FIFO_Read_DFF
|
558 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
559 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
560 |
|
|
fifo_Read <= '0';
|
561 |
|
|
else
|
562 |
|
|
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
|
563 |
|
|
end if;
|
564 |
|
|
end if;
|
565 |
|
|
end process FIFO_READ_DFF;
|
566 |
|
|
--------------------------------------------------------------------------
|
567 |
|
|
-- Select which bit within the data word to transmit
|
568 |
|
|
--------------------------------------------------------------------------
|
569 |
|
|
|
570 |
|
|
--------------------------------------------------------------------------
|
571 |
|
|
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
|
572 |
|
|
-- bit because of parity generation
|
573 |
|
|
--------------------------------------------------------------------------
|
574 |
|
|
|
575 |
|
|
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
|
576 |
|
|
|
577 |
|
|
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
|
578 |
|
|
fifo_DOut(C_DATA_BITS-1);
|
579 |
|
|
|
580 |
|
|
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
|
581 |
|
|
data_to_transfer(0);
|
582 |
|
|
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
|
583 |
|
|
data_to_transfer(2);
|
584 |
|
|
|
585 |
|
|
--------------------------------------------------------------------------
|
586 |
|
|
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
|
587 |
|
|
--------------------------------------------------------------------------
|
588 |
|
|
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
|
589 |
|
|
mux_45 <= data_to_transfer(4);
|
590 |
|
|
mux_67 <= '0';
|
591 |
|
|
end generate DATA_BITS_IS_5;
|
592 |
|
|
|
593 |
|
|
--------------------------------------------------------------------------
|
594 |
|
|
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
|
595 |
|
|
--------------------------------------------------------------------------
|
596 |
|
|
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
|
597 |
|
|
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
|
598 |
|
|
data_to_transfer(4);
|
599 |
|
|
mux_67 <= '0';
|
600 |
|
|
end generate DATA_BITS_IS_6;
|
601 |
|
|
|
602 |
|
|
--------------------------------------------------------------------------
|
603 |
|
|
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
|
604 |
|
|
--------------------------------------------------------------------------
|
605 |
|
|
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
|
606 |
|
|
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
|
607 |
|
|
data_to_transfer(4);
|
608 |
|
|
mux_67 <= data_to_transfer(6);
|
609 |
|
|
end generate DATA_BITS_IS_7;
|
610 |
|
|
|
611 |
|
|
--------------------------------------------------------------------------
|
612 |
|
|
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
|
613 |
|
|
--------------------------------------------------------------------------
|
614 |
|
|
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
|
615 |
|
|
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
|
616 |
|
|
data_to_transfer(4);
|
617 |
|
|
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
|
618 |
|
|
data_to_transfer(6);
|
619 |
|
|
end generate DATA_BITS_IS_8;
|
620 |
|
|
|
621 |
|
|
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
|
622 |
|
|
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
|
623 |
|
|
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
|
624 |
|
|
|
625 |
|
|
--------------------------------------------------------------------------
|
626 |
|
|
-- SERIAL_DATA_DFF : Register the mux_Out
|
627 |
|
|
--------------------------------------------------------------------------
|
628 |
|
|
SERIAL_DATA_DFF : process (Clk) is
|
629 |
|
|
begin
|
630 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
631 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
632 |
|
|
serial_Data <= '0';
|
633 |
|
|
else
|
634 |
|
|
serial_Data <= mux_Out;
|
635 |
|
|
end if;
|
636 |
|
|
end if;
|
637 |
|
|
end process SERIAL_DATA_DFF;
|
638 |
|
|
|
639 |
|
|
--------------------------------------------------------------------------
|
640 |
|
|
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
|
641 |
|
|
-- Force a '1' when tx_run is '0', Idle
|
642 |
|
|
-- otherwise put out the serial_data
|
643 |
|
|
--------------------------------------------------------------------------
|
644 |
|
|
SERIAL_OUT_DFF : process (Clk) is
|
645 |
|
|
begin -- process Serial_Out_DFF
|
646 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
647 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
648 |
|
|
TX <= '1';
|
649 |
|
|
else
|
650 |
|
|
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
|
651 |
|
|
end if;
|
652 |
|
|
end if;
|
653 |
|
|
end process SERIAL_OUT_DFF;
|
654 |
|
|
|
655 |
|
|
--------------------------------------------------------------------------
|
656 |
|
|
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
|
657 |
|
|
--------------------------------------------------------------------------
|
658 |
|
|
USING_PARITY : if (C_USE_PARITY = 1) generate
|
659 |
|
|
|
660 |
|
|
PARITY_DFF: Process (Clk) is
|
661 |
|
|
begin
|
662 |
|
|
if (Clk'event and Clk = '1') then
|
663 |
|
|
if (tx_Start = '1') then
|
664 |
|
|
parity <= bo2sl(C_ODD_PARITY = 1);
|
665 |
|
|
elsif (tx_Data_Enable = '1') then
|
666 |
|
|
parity <= parity xor serial_Data;
|
667 |
|
|
end if;
|
668 |
|
|
end if;
|
669 |
|
|
end process PARITY_DFF;
|
670 |
|
|
|
671 |
|
|
TX_RUN1_DFF : process (Clk) is
|
672 |
|
|
begin
|
673 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
674 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
675 |
|
|
tx_Run1 <= '0';
|
676 |
|
|
elsif (tx_Data_Enable = '1') then
|
677 |
|
|
tx_Run1 <= tx_DataBits;
|
678 |
|
|
end if;
|
679 |
|
|
end if;
|
680 |
|
|
end process TX_RUN1_DFF;
|
681 |
|
|
|
682 |
|
|
tx_Run <= tx_Run1 or tx_DataBits;
|
683 |
|
|
|
684 |
|
|
SELECT_PARITY_DFF : process (Clk) is
|
685 |
|
|
begin
|
686 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
687 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
688 |
|
|
select_Parity <= '0';
|
689 |
|
|
elsif (tx_Data_Enable = '1') then
|
690 |
|
|
select_Parity <= mux_sel_is_zero;
|
691 |
|
|
end if;
|
692 |
|
|
end if;
|
693 |
|
|
end process SELECT_PARITY_DFF;
|
694 |
|
|
|
695 |
|
|
end generate USING_PARITY;
|
696 |
|
|
|
697 |
|
|
--------------------------------------------------------------------------
|
698 |
|
|
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
|
699 |
|
|
--------------------------------------------------------------------------
|
700 |
|
|
NO_PARITY : if (C_USE_PARITY = 0) generate
|
701 |
|
|
tx_Run <= tx_DataBits;
|
702 |
|
|
select_Parity <= '0';
|
703 |
|
|
end generate NO_PARITY;
|
704 |
|
|
|
705 |
|
|
--------------------------------------------------------------------------
|
706 |
|
|
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
|
707 |
|
|
--------------------------------------------------------------------------
|
708 |
|
|
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
|
709 |
|
|
|
710 |
|
|
--------------------------------------------------------------------------
|
711 |
|
|
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
|
712 |
|
|
--------------------------------------------------------------------------
|
713 |
|
|
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
|
714 |
|
|
|
715 |
|
|
--------------------------------------------------------------------------
|
716 |
|
|
-- Reset TX FIFO when requested from the control register or system reset
|
717 |
|
|
--------------------------------------------------------------------------
|
718 |
|
|
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
|
719 |
|
|
|
720 |
|
|
--------------------------------------------------------------------------
|
721 |
|
|
-- SRL_FIFO_I : Transmit FIFO Interface
|
722 |
|
|
--------------------------------------------------------------------------
|
723 |
|
|
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
|
724 |
|
|
generic map
|
725 |
|
|
(
|
726 |
|
|
C_DWIDTH => C_DATA_BITS,
|
727 |
|
|
C_DEPTH => 16,
|
728 |
|
|
C_FAMILY => C_FAMILY
|
729 |
|
|
)
|
730 |
|
|
port map
|
731 |
|
|
(
|
732 |
|
|
Clk => Clk,
|
733 |
|
|
Reset => TX_FIFO_Reset,
|
734 |
|
|
FIFO_Write => fifo_wr,
|
735 |
|
|
Data_In => TX_Data,
|
736 |
|
|
FIFO_Read => fifo_rd,
|
737 |
|
|
Data_Out => fifo_DOut,
|
738 |
|
|
FIFO_Full => tx_buffer_full_i,
|
739 |
|
|
FIFO_Empty => fifo_Data_Empty
|
740 |
|
|
);
|
741 |
|
|
|
742 |
|
|
TX_Buffer_Full <= tx_buffer_full_i;
|
743 |
|
|
TX_Buffer_Empty <= fifo_Data_Empty;
|
744 |
|
|
fifo_Data_Present <= not fifo_Data_Empty;
|
745 |
|
|
|
746 |
|
|
end architecture RTL;
|
747 |
|
|
|
748 |
|
|
|
749 |
|
|
-------------------------------------------------------------------------------
|
750 |
|
|
-- uartlite_rx - entity/architecture pair
|
751 |
|
|
-------------------------------------------------------------------------------
|
752 |
|
|
--
|
753 |
|
|
-- *******************************************************************
|
754 |
|
|
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
|
755 |
|
|
-- -- ** *
|
756 |
|
|
-- -- ** This file contains confidential and proprietary information *
|
757 |
|
|
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
|
758 |
|
|
-- -- ** international copyright and other intellectual property *
|
759 |
|
|
-- -- ** laws. *
|
760 |
|
|
-- -- ** *
|
761 |
|
|
-- -- ** DISCLAIMER *
|
762 |
|
|
-- -- ** This disclaimer is not a license and does not grant any *
|
763 |
|
|
-- -- ** rights to the materials distributed herewith. Except as *
|
764 |
|
|
-- -- ** otherwise provided in a valid license issued to you by *
|
765 |
|
|
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
|
766 |
|
|
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
767 |
|
|
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
768 |
|
|
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
769 |
|
|
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
770 |
|
|
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
771 |
|
|
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
|
772 |
|
|
-- -- ** including negligence, or under any other theory of *
|
773 |
|
|
-- -- ** liability) for any loss or damage of any kind or nature *
|
774 |
|
|
-- -- ** related to, arising under or in connection with these *
|
775 |
|
|
-- -- ** materials, including for any direct, or any indirect, *
|
776 |
|
|
-- -- ** special, incidental, or consequential loss or damage *
|
777 |
|
|
-- -- ** (including loss of data, profits, goodwill, or any type of *
|
778 |
|
|
-- -- ** loss or damage suffered as a result of any action brought *
|
779 |
|
|
-- -- ** by a third party) even if such damage or loss was *
|
780 |
|
|
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
|
781 |
|
|
-- -- ** possibility of the same. *
|
782 |
|
|
-- -- ** *
|
783 |
|
|
-- -- ** CRITICAL APPLICATIONS *
|
784 |
|
|
-- -- ** Xilinx products are not designed or intended to be fail- *
|
785 |
|
|
-- -- ** safe, or for use in any application requiring fail-safe *
|
786 |
|
|
-- -- ** performance, such as life-support or safety devices or *
|
787 |
|
|
-- -- ** systems, Class III medical devices, nuclear facilities, *
|
788 |
|
|
-- -- ** applications related to the deployment of airbags, or any *
|
789 |
|
|
-- -- ** other applications that could lead to death, personal *
|
790 |
|
|
-- -- ** injury, or severe property or environmental damage *
|
791 |
|
|
-- -- ** (individually and collectively, "Critical *
|
792 |
|
|
-- -- ** Applications"). Customer assumes the sole risk and *
|
793 |
|
|
-- -- ** liability of any use of Xilinx products in Critical *
|
794 |
|
|
-- -- ** Applications, subject only to applicable laws and *
|
795 |
|
|
-- -- ** regulations governing limitations on product liability. *
|
796 |
|
|
-- -- ** *
|
797 |
|
|
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
798 |
|
|
-- -- ** PART OF THIS FILE AT ALL TIMES. *
|
799 |
|
|
-- *******************************************************************
|
800 |
|
|
--
|
801 |
|
|
-------------------------------------------------------------------------------
|
802 |
|
|
-- Filename: uartlite_rx.vhd
|
803 |
|
|
-- Version: v2.0
|
804 |
|
|
-- Description: UART Lite Receive Interface Module
|
805 |
|
|
--
|
806 |
|
|
-- VHDL-Standard: VHDL'93
|
807 |
|
|
-------------------------------------------------------------------------------
|
808 |
|
|
-------------------------------------------------------------------------------
|
809 |
|
|
-- Naming Conventions:
|
810 |
|
|
-- active low signals: "*_n"
|
811 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
812 |
|
|
-- reset signals: "rst", "rst_n"
|
813 |
|
|
-- generics: "C_*"
|
814 |
|
|
-- user defined types: "*_TYPE"
|
815 |
|
|
-- state machine next state: "*_ns"
|
816 |
|
|
-- state machine current state: "*_cs"
|
817 |
|
|
-- combinatorial signals: "*_com"
|
818 |
|
|
-- pipelined or register delay signals: "*_d#"
|
819 |
|
|
-- counter signals: "*cnt*"
|
820 |
|
|
-- clock enable signals: "*_ce"
|
821 |
|
|
-- internal version of output port "*_i"
|
822 |
|
|
-- device pins: "*_pin"
|
823 |
|
|
-- ports: - Names begin with Uppercase
|
824 |
|
|
-- processes: "*_PROCESS"
|
825 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
826 |
|
|
-------------------------------------------------------------------------------
|
827 |
|
|
library IEEE;
|
828 |
|
|
use IEEE.std_logic_1164.all;
|
829 |
|
|
|
830 |
|
|
library lib_srl_fifo_v1_0_2;
|
831 |
|
|
library lib_cdc_v1_0_2;
|
832 |
|
|
use lib_cdc_v1_0_2.cdc_sync;
|
833 |
|
|
|
834 |
|
|
-- dynshreg_i_f refered from proc_common_v4_0_2
|
835 |
|
|
-- srl_fifo_f refered from proc_common_v4_0_2
|
836 |
|
|
use lib_srl_fifo_v1_0_2.srl_fifo_f;
|
837 |
|
|
|
838 |
|
|
library axi_uartlite_v2_0_19;
|
839 |
|
|
-- uartlite_core refered from axi_uartlite_v2_0_19
|
840 |
|
|
use axi_uartlite_v2_0_19.all;
|
841 |
|
|
|
842 |
|
|
-------------------------------------------------------------------------------
|
843 |
|
|
-- Port Declaration
|
844 |
|
|
-------------------------------------------------------------------------------
|
845 |
|
|
-------------------------------------------------------------------------------
|
846 |
|
|
-- Definition of Generics :
|
847 |
|
|
-------------------------------------------------------------------------------
|
848 |
|
|
-- UART Lite generics
|
849 |
|
|
-- C_DATA_BITS -- The number of data bits in the serial frame
|
850 |
|
|
-- C_USE_PARITY -- Determines whether parity is used or not
|
851 |
|
|
-- C_ODD_PARITY -- If parity is used determines whether parity
|
852 |
|
|
-- is even or odd
|
853 |
|
|
--
|
854 |
|
|
-- System generics
|
855 |
|
|
-- C_FAMILY -- Xilinx FPGA Family
|
856 |
|
|
-------------------------------------------------------------------------------
|
857 |
|
|
-------------------------------------------------------------------------------
|
858 |
|
|
-- Definition of Ports :
|
859 |
|
|
-------------------------------------------------------------------------------
|
860 |
|
|
-- System Signals
|
861 |
|
|
-- Clk -- Clock signal
|
862 |
|
|
-- Rst -- Reset signal
|
863 |
|
|
-- UART Lite interface
|
864 |
|
|
-- RX -- Receive Data
|
865 |
|
|
|
866 |
|
|
-- Internal UART interface signals
|
867 |
|
|
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
|
868 |
|
|
-- Read_RX_FIFO -- Read receive FIFO
|
869 |
|
|
-- Reset_RX_FIFO -- Reset receive FIFO
|
870 |
|
|
-- RX_Data -- Receive data output
|
871 |
|
|
-- RX_Data_Present -- Receive data present
|
872 |
|
|
-- RX_Buffer_Full -- Receive buffer full
|
873 |
|
|
-- RX_Frame_Error -- Receive frame error
|
874 |
|
|
-- RX_Overrun_Error -- Receive overrun error
|
875 |
|
|
-- RX_Parity_Error -- Receive parity error
|
876 |
|
|
|
877 |
|
|
-------------------------------------------------------------------------------
|
878 |
|
|
-------------------------------------------------------------------------------
|
879 |
|
|
-- Entity Section
|
880 |
|
|
-------------------------------------------------------------------------------
|
881 |
|
|
entity uartlite_rx is
|
882 |
|
|
generic
|
883 |
|
|
(
|
884 |
|
|
C_FAMILY : string := "virtex7";
|
885 |
|
|
C_DATA_BITS : integer range 5 to 8 := 8;
|
886 |
|
|
C_USE_PARITY : integer range 0 to 1 := 0;
|
887 |
|
|
C_ODD_PARITY : integer range 0 to 1 := 0
|
888 |
|
|
);
|
889 |
|
|
port
|
890 |
|
|
(
|
891 |
|
|
Clk : in std_logic;
|
892 |
|
|
Reset : in std_logic;
|
893 |
|
|
EN_16x_Baud : in std_logic;
|
894 |
|
|
RX : in std_logic;
|
895 |
|
|
Read_RX_FIFO : in std_logic;
|
896 |
|
|
Reset_RX_FIFO : in std_logic;
|
897 |
|
|
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
|
898 |
|
|
RX_Data_Present : out std_logic;
|
899 |
|
|
RX_Buffer_Full : out std_logic;
|
900 |
|
|
RX_Frame_Error : out std_logic;
|
901 |
|
|
RX_Overrun_Error : out std_logic;
|
902 |
|
|
RX_Parity_Error : out std_logic
|
903 |
|
|
);
|
904 |
|
|
end entity uartlite_rx;
|
905 |
|
|
|
906 |
|
|
-------------------------------------------------------------------------------
|
907 |
|
|
-- Architecture Section
|
908 |
|
|
-------------------------------------------------------------------------------
|
909 |
|
|
architecture RTL of uartlite_rx is
|
910 |
|
|
-- Pragma Added to supress synth warnings
|
911 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
912 |
|
|
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
|
913 |
|
|
|
914 |
|
|
type bo2sl_type is array(boolean) of std_logic;
|
915 |
|
|
|
916 |
|
|
constant bo2sl : bo2sl_type := (false => '0', true => '1');
|
917 |
|
|
|
918 |
|
|
---------------------------------------------------------------------------
|
919 |
|
|
-- Constant declarations
|
920 |
|
|
---------------------------------------------------------------------------
|
921 |
|
|
constant SERIAL_TO_PAR_LENGTH : integer :=
|
922 |
|
|
C_DATA_BITS + C_USE_PARITY;
|
923 |
|
|
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
|
924 |
|
|
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
|
925 |
|
|
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
|
926 |
|
|
|
927 |
|
|
---------------------------------------------------------------------------
|
928 |
|
|
-- Signal declarations
|
929 |
|
|
---------------------------------------------------------------------------
|
930 |
|
|
signal start_Edge_Detected : boolean;
|
931 |
|
|
signal start_Edge_Detected_Bit : std_logic;
|
932 |
|
|
signal running : boolean;
|
933 |
|
|
signal recycle : std_logic;
|
934 |
|
|
signal sample_Point : std_logic;
|
935 |
|
|
signal stop_Bit_Position : std_logic;
|
936 |
|
|
signal fifo_Write : std_logic;
|
937 |
|
|
|
938 |
|
|
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
|
939 |
|
|
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
|
940 |
|
|
signal calc_parity : std_logic;
|
941 |
|
|
signal parity : std_logic;
|
942 |
|
|
signal RX_Buffer_Full_I : std_logic;
|
943 |
|
|
signal RX_D1 : std_logic;
|
944 |
|
|
signal RX_D2 : std_logic;
|
945 |
|
|
signal rx_1 : std_logic;
|
946 |
|
|
signal rx_2 : std_logic;
|
947 |
|
|
signal rx_3 : std_logic;
|
948 |
|
|
signal rx_4 : std_logic;
|
949 |
|
|
signal rx_5 : std_logic;
|
950 |
|
|
signal rx_6 : std_logic;
|
951 |
|
|
signal rx_7 : std_logic;
|
952 |
|
|
signal rx_8 : std_logic;
|
953 |
|
|
signal rx_9 : std_logic;
|
954 |
|
|
signal rx_Data_Empty : std_logic := '0';
|
955 |
|
|
signal fifo_wr : std_logic;
|
956 |
|
|
signal fifo_rd : std_logic;
|
957 |
|
|
signal RX_FIFO_Reset : std_logic;
|
958 |
|
|
signal valid_rx : std_logic;
|
959 |
|
|
signal valid_start : std_logic;
|
960 |
|
|
signal frame_err_ocrd : std_logic;
|
961 |
|
|
signal frame_err : std_logic;
|
962 |
|
|
|
963 |
|
|
begin -- architecture RTL
|
964 |
|
|
|
965 |
|
|
---------------------------------------------------------------------------
|
966 |
|
|
-- RX_SAMPLING : Double sample RX to avoid meta-stability
|
967 |
|
|
---------------------------------------------------------------------------
|
968 |
|
|
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
|
969 |
|
|
generic map (
|
970 |
|
|
C_CDC_TYPE => 1,
|
971 |
|
|
C_RESET_STATE => 0,
|
972 |
|
|
C_SINGLE_BIT => 1,
|
973 |
|
|
C_VECTOR_WIDTH => 32,
|
974 |
|
|
C_MTBF_STAGES => 4
|
975 |
|
|
)
|
976 |
|
|
port map (
|
977 |
|
|
prmry_aclk => '0',
|
978 |
|
|
prmry_resetn => '0',
|
979 |
|
|
prmry_in => RX,
|
980 |
|
|
prmry_vect_in => (others => '0'),
|
981 |
|
|
|
982 |
|
|
scndry_aclk => Clk,
|
983 |
|
|
scndry_resetn => '0',
|
984 |
|
|
scndry_out => RX_D2,
|
985 |
|
|
scndry_vect_out => open
|
986 |
|
|
);
|
987 |
|
|
|
988 |
|
|
|
989 |
|
|
-- RX_SAMPLING: process (Clk) is
|
990 |
|
|
-- begin -- process RX_Sampling
|
991 |
|
|
-- if Clk'event and Clk = '1' then -- rising clock edge
|
992 |
|
|
-- if Reset = '1' then -- synchronous reset (active high)
|
993 |
|
|
-- RX_D1 <= '1';
|
994 |
|
|
-- RX_D2 <= '1';
|
995 |
|
|
-- else
|
996 |
|
|
-- RX_D1 <= RX;
|
997 |
|
|
-- RX_D2 <= RX_D1;
|
998 |
|
|
-- end if;
|
999 |
|
|
-- end if;
|
1000 |
|
|
-- end process RX_SAMPLING;
|
1001 |
|
|
|
1002 |
|
|
-------------------------------------------------------------------------------
|
1003 |
|
|
-- Detect a falling edge on RX and start a new reception if idle
|
1004 |
|
|
-------------------------------------------------------------------------------
|
1005 |
|
|
|
1006 |
|
|
---------------------------------------------------------------------------
|
1007 |
|
|
-- detect the start of the frame
|
1008 |
|
|
---------------------------------------------------------------------------
|
1009 |
|
|
RX_DFFS : process (Clk) is
|
1010 |
|
|
begin -- process Prev_RX_DFFS
|
1011 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1012 |
|
|
if (Reset = '1') then
|
1013 |
|
|
rx_1 <= '0';
|
1014 |
|
|
rx_2 <= '0';
|
1015 |
|
|
rx_3 <= '0';
|
1016 |
|
|
rx_4 <= '0';
|
1017 |
|
|
rx_5 <= '0';
|
1018 |
|
|
rx_6 <= '0';
|
1019 |
|
|
rx_7 <= '0';
|
1020 |
|
|
rx_8 <= '0';
|
1021 |
|
|
rx_9 <= '0';
|
1022 |
|
|
elsif (EN_16x_Baud = '1') then
|
1023 |
|
|
rx_1 <= RX_D2;
|
1024 |
|
|
rx_2 <= rx_1;
|
1025 |
|
|
rx_3 <= rx_2;
|
1026 |
|
|
rx_4 <= rx_3;
|
1027 |
|
|
rx_5 <= rx_4;
|
1028 |
|
|
rx_6 <= rx_5;
|
1029 |
|
|
rx_7 <= rx_6;
|
1030 |
|
|
rx_8 <= rx_7;
|
1031 |
|
|
rx_9 <= rx_8;
|
1032 |
|
|
end if;
|
1033 |
|
|
end if;
|
1034 |
|
|
end process RX_DFFS;
|
1035 |
|
|
|
1036 |
|
|
---------------------------------------------------------------------------
|
1037 |
|
|
-- Start bit valid when RX is continuously low for atleast 8 samples
|
1038 |
|
|
---------------------------------------------------------------------------
|
1039 |
|
|
|
1040 |
|
|
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
|
1041 |
|
|
rx_4 or rx_3 or rx_2 or rx_1;
|
1042 |
|
|
|
1043 |
|
|
---------------------------------------------------------------------------
|
1044 |
|
|
-- START_EDGE_DFF : Start a new reception if idle
|
1045 |
|
|
---------------------------------------------------------------------------
|
1046 |
|
|
START_EDGE_DFF : process (Clk) is
|
1047 |
|
|
begin -- process Start_Edge_DFF
|
1048 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1049 |
|
|
if (Reset = '1') then
|
1050 |
|
|
start_Edge_Detected <= false;
|
1051 |
|
|
elsif (EN_16x_Baud = '1') then
|
1052 |
|
|
start_Edge_Detected <= ((not running) and
|
1053 |
|
|
(frame_err_ocrd = '0') and
|
1054 |
|
|
(rx_9 = '1') and
|
1055 |
|
|
(valid_start = '0'));
|
1056 |
|
|
end if;
|
1057 |
|
|
end if;
|
1058 |
|
|
end process START_EDGE_DFF;
|
1059 |
|
|
|
1060 |
|
|
---------------------------------------------------------------------------
|
1061 |
|
|
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
|
1062 |
|
|
-- and deasserted when the next low to high on RX
|
1063 |
|
|
---------------------------------------------------------------------------
|
1064 |
|
|
FRAME_ERR_CAPTURE : process (Clk) is
|
1065 |
|
|
begin -- process valid_rx_DFF
|
1066 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1067 |
|
|
if (Reset = '1') then -- synchronous reset (active high)
|
1068 |
|
|
frame_err_ocrd <= '0';
|
1069 |
|
|
elsif (frame_err = '1') then
|
1070 |
|
|
frame_err_ocrd <= '1';
|
1071 |
|
|
elsif (RX_D2 = '1') then
|
1072 |
|
|
frame_err_ocrd <= '0';
|
1073 |
|
|
end if;
|
1074 |
|
|
end if;
|
1075 |
|
|
end process FRAME_ERR_CAPTURE;
|
1076 |
|
|
|
1077 |
|
|
---------------------------------------------------------------------------
|
1078 |
|
|
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
|
1079 |
|
|
---------------------------------------------------------------------------
|
1080 |
|
|
VALID_XFER : process (Clk) is
|
1081 |
|
|
begin -- process valid_rx_DFF
|
1082 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1083 |
|
|
if (Reset = '1') then -- synchronous reset (active high)
|
1084 |
|
|
valid_rx <= '0';
|
1085 |
|
|
elsif (start_Edge_Detected = true) then
|
1086 |
|
|
valid_rx <= '1';
|
1087 |
|
|
elsif (fifo_Write = '1') then
|
1088 |
|
|
valid_rx <= '0';
|
1089 |
|
|
end if;
|
1090 |
|
|
end if;
|
1091 |
|
|
end process VALID_XFER;
|
1092 |
|
|
|
1093 |
|
|
---------------------------------------------------------------------------
|
1094 |
|
|
-- RUNNING_DFF : Running is '1' during a reception
|
1095 |
|
|
---------------------------------------------------------------------------
|
1096 |
|
|
RUNNING_DFF : process (Clk) is
|
1097 |
|
|
begin -- process Running_DFF
|
1098 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1099 |
|
|
if (Reset = '1') then -- synchronous reset (active high)
|
1100 |
|
|
running <= false;
|
1101 |
|
|
elsif (EN_16x_Baud = '1') then
|
1102 |
|
|
if (start_Edge_Detected) then
|
1103 |
|
|
running <= true;
|
1104 |
|
|
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
|
1105 |
|
|
running <= false;
|
1106 |
|
|
end if;
|
1107 |
|
|
end if;
|
1108 |
|
|
end if;
|
1109 |
|
|
end process RUNNING_DFF;
|
1110 |
|
|
|
1111 |
|
|
---------------------------------------------------------------------------
|
1112 |
|
|
-- Boolean to std logic conversion of start edge
|
1113 |
|
|
---------------------------------------------------------------------------
|
1114 |
|
|
|
1115 |
|
|
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
|
1116 |
|
|
|
1117 |
|
|
---------------------------------------------------------------------------
|
1118 |
|
|
-- After the start edge is detected, generate recycle to generate sample
|
1119 |
|
|
-- point
|
1120 |
|
|
---------------------------------------------------------------------------
|
1121 |
|
|
|
1122 |
|
|
recycle <= (valid_rx and (not stop_Bit_Position) and
|
1123 |
|
|
(start_Edge_Detected_Bit or sample_Point));
|
1124 |
|
|
|
1125 |
|
|
-------------------------------------------------------------------------
|
1126 |
|
|
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
|
1127 |
|
|
-- Starting with the first start_Edge_Detected_Bit and for every new
|
1128 |
|
|
-- sample_points until stop_Bit_Position is reached
|
1129 |
|
|
-------------------------------------------------------------------------
|
1130 |
|
|
DELAY_16_I : entity axi_uartlite_v2_0_19.dynshreg_i_f
|
1131 |
|
|
generic map
|
1132 |
|
|
(
|
1133 |
|
|
C_DEPTH => 16,
|
1134 |
|
|
C_DWIDTH => 1,
|
1135 |
|
|
C_FAMILY => C_FAMILY
|
1136 |
|
|
)
|
1137 |
|
|
port map
|
1138 |
|
|
(
|
1139 |
|
|
Clk => Clk,
|
1140 |
|
|
Clken => EN_16x_Baud,
|
1141 |
|
|
Addr => "1111",
|
1142 |
|
|
Din(0) => recycle,
|
1143 |
|
|
Dout(0) => sample_Point
|
1144 |
|
|
);
|
1145 |
|
|
|
1146 |
|
|
---------------------------------------------------------------------------
|
1147 |
|
|
-- STOP_BIT_HANDLER : Detect when the stop bit is received
|
1148 |
|
|
---------------------------------------------------------------------------
|
1149 |
|
|
STOP_BIT_HANDLER : process (Clk) is
|
1150 |
|
|
begin -- process Stop_Bit_Handler
|
1151 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1152 |
|
|
if (Reset = '1') then -- synchronous reset (active high)
|
1153 |
|
|
stop_Bit_Position <= '0';
|
1154 |
|
|
elsif (EN_16x_Baud = '1') then
|
1155 |
|
|
if (stop_Bit_Position = '0') then
|
1156 |
|
|
-- Start bit has reached the end of the shift register
|
1157 |
|
|
-- (Stop bit position)
|
1158 |
|
|
stop_Bit_Position <= sample_Point and
|
1159 |
|
|
fifo_din(STOP_BIT_POS);
|
1160 |
|
|
elsif (sample_Point = '1') then
|
1161 |
|
|
-- if stop_Bit_Position is 1 clear it at next sample_Point
|
1162 |
|
|
stop_Bit_Position <= '0';
|
1163 |
|
|
end if;
|
1164 |
|
|
end if;
|
1165 |
|
|
end if;
|
1166 |
|
|
end process STOP_BIT_HANDLER;
|
1167 |
|
|
|
1168 |
|
|
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
|
1169 |
|
|
RX_Parity_Error <= '0' ;
|
1170 |
|
|
end generate USING_PARITY_NO;
|
1171 |
|
|
---------------------------------------------------------------------------
|
1172 |
|
|
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
|
1173 |
|
|
---------------------------------------------------------------------------
|
1174 |
|
|
USING_PARITY : if (C_USE_PARITY = 1) generate
|
1175 |
|
|
|
1176 |
|
|
PARITY_DFF: Process (Clk) is
|
1177 |
|
|
begin
|
1178 |
|
|
if (Clk'event and Clk = '1') then
|
1179 |
|
|
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
|
1180 |
|
|
parity <= bo2sl(C_ODD_PARITY = 1);
|
1181 |
|
|
elsif (EN_16x_Baud = '1') then
|
1182 |
|
|
parity <= calc_parity;
|
1183 |
|
|
end if;
|
1184 |
|
|
end if;
|
1185 |
|
|
end process PARITY_DFF;
|
1186 |
|
|
|
1187 |
|
|
calc_parity <= parity when (stop_Bit_Position or
|
1188 |
|
|
(not sample_Point)) = '1'
|
1189 |
|
|
else parity xor RX_D2;
|
1190 |
|
|
|
1191 |
|
|
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
|
1192 |
|
|
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
|
1193 |
|
|
when running and (RX_D2 /= parity) else '0';
|
1194 |
|
|
|
1195 |
|
|
end generate USING_PARITY;
|
1196 |
|
|
|
1197 |
|
|
fifo_din(0) <= RX_D2 and not Reset;
|
1198 |
|
|
|
1199 |
|
|
---------------------------------------------------------------------------
|
1200 |
|
|
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
|
1201 |
|
|
---------------------------------------------------------------------------
|
1202 |
|
|
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
|
1203 |
|
|
|
1204 |
|
|
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
|
1205 |
|
|
not sample_Point) = '1'
|
1206 |
|
|
else fifo_din(i-1);
|
1207 |
|
|
|
1208 |
|
|
BIT_I: Process (Clk) is
|
1209 |
|
|
begin
|
1210 |
|
|
if (Clk'event and Clk = '1') then
|
1211 |
|
|
if (Reset = '1') then
|
1212 |
|
|
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
|
1213 |
|
|
else -- others to '1'
|
1214 |
|
|
if (start_Edge_Detected_Bit = '1') then
|
1215 |
|
|
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
|
1216 |
|
|
-- others to '0'
|
1217 |
|
|
elsif (EN_16x_Baud = '1') then
|
1218 |
|
|
fifo_din(i) <= serial_to_Par(i);
|
1219 |
|
|
end if;
|
1220 |
|
|
end if;
|
1221 |
|
|
end if;
|
1222 |
|
|
end process BIT_I;
|
1223 |
|
|
|
1224 |
|
|
end generate SERIAL_TO_PARALLEL;
|
1225 |
|
|
|
1226 |
|
|
--------------------------------------------------------------------------
|
1227 |
|
|
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
|
1228 |
|
|
-- received and it is a '1'
|
1229 |
|
|
--------------------------------------------------------------------------
|
1230 |
|
|
FIFO_WRITE_DFF : process (Clk) is
|
1231 |
|
|
begin -- process FIFO_Write_DFF
|
1232 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1233 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
1234 |
|
|
fifo_Write <= '0';
|
1235 |
|
|
else
|
1236 |
|
|
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
|
1237 |
|
|
and EN_16x_Baud;
|
1238 |
|
|
end if;
|
1239 |
|
|
end if;
|
1240 |
|
|
end process FIFO_WRITE_DFF;
|
1241 |
|
|
|
1242 |
|
|
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
|
1243 |
|
|
and not RX_D2;
|
1244 |
|
|
|
1245 |
|
|
RX_Frame_Error <= frame_err;
|
1246 |
|
|
|
1247 |
|
|
--------------------------------------------------------------------------
|
1248 |
|
|
-- Write RX FIFO when FIFO is not full when valid data is reveived
|
1249 |
|
|
--------------------------------------------------------------------------
|
1250 |
|
|
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
|
1251 |
|
|
|
1252 |
|
|
--------------------------------------------------------------------------
|
1253 |
|
|
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
|
1254 |
|
|
--------------------------------------------------------------------------
|
1255 |
|
|
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
|
1256 |
|
|
|
1257 |
|
|
--------------------------------------------------------------------------
|
1258 |
|
|
-- Reset RX FIFO when requested from the control register or system reset
|
1259 |
|
|
--------------------------------------------------------------------------
|
1260 |
|
|
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
|
1261 |
|
|
|
1262 |
|
|
---------------------------------------------------------------------------
|
1263 |
|
|
-- SRL_FIFO_I : Receive FIFO Interface
|
1264 |
|
|
---------------------------------------------------------------------------
|
1265 |
|
|
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
|
1266 |
|
|
generic map
|
1267 |
|
|
(
|
1268 |
|
|
C_DWIDTH => C_DATA_BITS,
|
1269 |
|
|
C_DEPTH => 16,
|
1270 |
|
|
C_FAMILY => C_FAMILY
|
1271 |
|
|
)
|
1272 |
|
|
port map
|
1273 |
|
|
(
|
1274 |
|
|
Clk => Clk,
|
1275 |
|
|
Reset => RX_FIFO_Reset,
|
1276 |
|
|
FIFO_Write => fifo_wr,
|
1277 |
|
|
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
|
1278 |
|
|
FIFO_Read => fifo_rd,
|
1279 |
|
|
Data_Out => RX_Data,
|
1280 |
|
|
FIFO_Full => RX_Buffer_Full_I,
|
1281 |
|
|
FIFO_Empty => rx_Data_Empty,
|
1282 |
|
|
Addr => open
|
1283 |
|
|
);
|
1284 |
|
|
|
1285 |
|
|
RX_Data_Present <= not rx_Data_Empty;
|
1286 |
|
|
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
|
1287 |
|
|
-- the RX FIFO is read on the same cycle as it is written while full,
|
1288 |
|
|
-- there is no loss of data. However this case is not optimized and
|
1289 |
|
|
-- is also reported as an overrun.
|
1290 |
|
|
RX_Buffer_Full <= RX_Buffer_Full_I;
|
1291 |
|
|
|
1292 |
|
|
end architecture RTL;
|
1293 |
|
|
|
1294 |
|
|
|
1295 |
|
|
-------------------------------------------------------------------------------
|
1296 |
|
|
-- baudrate - entity/architecture pair
|
1297 |
|
|
-------------------------------------------------------------------------------
|
1298 |
|
|
--
|
1299 |
|
|
-- *******************************************************************
|
1300 |
|
|
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
|
1301 |
|
|
-- -- ** *
|
1302 |
|
|
-- -- ** This file contains confidential and proprietary information *
|
1303 |
|
|
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
|
1304 |
|
|
-- -- ** international copyright and other intellectual property *
|
1305 |
|
|
-- -- ** laws. *
|
1306 |
|
|
-- -- ** *
|
1307 |
|
|
-- -- ** DISCLAIMER *
|
1308 |
|
|
-- -- ** This disclaimer is not a license and does not grant any *
|
1309 |
|
|
-- -- ** rights to the materials distributed herewith. Except as *
|
1310 |
|
|
-- -- ** otherwise provided in a valid license issued to you by *
|
1311 |
|
|
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
|
1312 |
|
|
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
1313 |
|
|
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
1314 |
|
|
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
1315 |
|
|
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
1316 |
|
|
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
1317 |
|
|
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
|
1318 |
|
|
-- -- ** including negligence, or under any other theory of *
|
1319 |
|
|
-- -- ** liability) for any loss or damage of any kind or nature *
|
1320 |
|
|
-- -- ** related to, arising under or in connection with these *
|
1321 |
|
|
-- -- ** materials, including for any direct, or any indirect, *
|
1322 |
|
|
-- -- ** special, incidental, or consequential loss or damage *
|
1323 |
|
|
-- -- ** (including loss of data, profits, goodwill, or any type of *
|
1324 |
|
|
-- -- ** loss or damage suffered as a result of any action brought *
|
1325 |
|
|
-- -- ** by a third party) even if such damage or loss was *
|
1326 |
|
|
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
|
1327 |
|
|
-- -- ** possibility of the same. *
|
1328 |
|
|
-- -- ** *
|
1329 |
|
|
-- -- ** CRITICAL APPLICATIONS *
|
1330 |
|
|
-- -- ** Xilinx products are not designed or intended to be fail- *
|
1331 |
|
|
-- -- ** safe, or for use in any application requiring fail-safe *
|
1332 |
|
|
-- -- ** performance, such as life-support or safety devices or *
|
1333 |
|
|
-- -- ** systems, Class III medical devices, nuclear facilities, *
|
1334 |
|
|
-- -- ** applications related to the deployment of airbags, or any *
|
1335 |
|
|
-- -- ** other applications that could lead to death, personal *
|
1336 |
|
|
-- -- ** injury, or severe property or environmental damage *
|
1337 |
|
|
-- -- ** (individually and collectively, "Critical *
|
1338 |
|
|
-- -- ** Applications"). Customer assumes the sole risk and *
|
1339 |
|
|
-- -- ** liability of any use of Xilinx products in Critical *
|
1340 |
|
|
-- -- ** Applications, subject only to applicable laws and *
|
1341 |
|
|
-- -- ** regulations governing limitations on product liability. *
|
1342 |
|
|
-- -- ** *
|
1343 |
|
|
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
1344 |
|
|
-- -- ** PART OF THIS FILE AT ALL TIMES. *
|
1345 |
|
|
-- *******************************************************************
|
1346 |
|
|
--
|
1347 |
|
|
-------------------------------------------------------------------------------
|
1348 |
|
|
-- Filename: baudrate.vhd
|
1349 |
|
|
-- Version: v2.0
|
1350 |
|
|
-- Description: Baud rate enable logic
|
1351 |
|
|
--
|
1352 |
|
|
-- VHDL-Standard: VHDL'93
|
1353 |
|
|
-------------------------------------------------------------------------------
|
1354 |
|
|
-- ^^^^^^
|
1355 |
|
|
-------------------------------------------------------------------------------
|
1356 |
|
|
-- Naming Conventions:
|
1357 |
|
|
-- active low signals: "*_n"
|
1358 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
1359 |
|
|
-- reset signals: "rst", "rst_n"
|
1360 |
|
|
-- generics: "C_*"
|
1361 |
|
|
-- user defined types: "*_TYPE"
|
1362 |
|
|
-- state machine next state: "*_ns"
|
1363 |
|
|
-- state machine current state: "*_cs"
|
1364 |
|
|
-- combinatorial signals: "*_com"
|
1365 |
|
|
-- pipelined or register delay signals: "*_d#"
|
1366 |
|
|
-- counter signals: "*cnt*"
|
1367 |
|
|
-- clock enable signals: "*_ce"
|
1368 |
|
|
-- internal version of output port "*_i"
|
1369 |
|
|
-- device pins: "*_pin"
|
1370 |
|
|
-- ports: - Names begin with Uppercase
|
1371 |
|
|
-- processes: "*_PROCESS"
|
1372 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
1373 |
|
|
-------------------------------------------------------------------------------
|
1374 |
|
|
|
1375 |
|
|
library IEEE;
|
1376 |
|
|
use IEEE.std_logic_1164.all;
|
1377 |
|
|
|
1378 |
|
|
-------------------------------------------------------------------------------
|
1379 |
|
|
-- Port Declaration
|
1380 |
|
|
-------------------------------------------------------------------------------
|
1381 |
|
|
-------------------------------------------------------------------------------
|
1382 |
|
|
-- Definition of Generics :
|
1383 |
|
|
-------------------------------------------------------------------------------
|
1384 |
|
|
-- UART Lite generics
|
1385 |
|
|
-- C_RATIO -- The ratio between clk and the asked baudrate
|
1386 |
|
|
-- multiplied with 16
|
1387 |
|
|
-------------------------------------------------------------------------------
|
1388 |
|
|
-------------------------------------------------------------------------------
|
1389 |
|
|
-- Definition of Ports :
|
1390 |
|
|
-------------------------------------------------------------------------------
|
1391 |
|
|
-- System Signals
|
1392 |
|
|
-- Clk -- Clock signal
|
1393 |
|
|
-- Reset -- Reset signal
|
1394 |
|
|
-- Internal UART interface signals
|
1395 |
|
|
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
|
1396 |
|
|
-------------------------------------------------------------------------------
|
1397 |
|
|
-------------------------------------------------------------------------------
|
1398 |
|
|
-- Entity Section
|
1399 |
|
|
-------------------------------------------------------------------------------
|
1400 |
|
|
|
1401 |
|
|
entity baudrate is
|
1402 |
|
|
generic
|
1403 |
|
|
(
|
1404 |
|
|
C_RATIO : integer := 48 -- The ratio between clk and the asked
|
1405 |
|
|
-- baudrate multiplied with 16
|
1406 |
|
|
);
|
1407 |
|
|
port
|
1408 |
|
|
(
|
1409 |
|
|
Clk : in std_logic;
|
1410 |
|
|
Reset : in std_logic;
|
1411 |
|
|
EN_16x_Baud : out std_logic
|
1412 |
|
|
);
|
1413 |
|
|
end entity baudrate;
|
1414 |
|
|
|
1415 |
|
|
-------------------------------------------------------------------------------
|
1416 |
|
|
-- Architecture Section
|
1417 |
|
|
-------------------------------------------------------------------------------
|
1418 |
|
|
architecture RTL of baudrate is
|
1419 |
|
|
-- Pragma Added to supress synth warnings
|
1420 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
1421 |
|
|
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
|
1422 |
|
|
|
1423 |
|
|
---------------------------------------------------------------------------
|
1424 |
|
|
-- Signal Declarations
|
1425 |
|
|
---------------------------------------------------------------------------
|
1426 |
|
|
signal count : natural range 0 to C_RATIO-1;
|
1427 |
|
|
|
1428 |
|
|
begin -- architecture VHDL_RTL
|
1429 |
|
|
|
1430 |
|
|
---------------------------------------------------------------------------
|
1431 |
|
|
-- COUNTER_PROCESS : Down counter for generating EN_16x_Baud signal
|
1432 |
|
|
---------------------------------------------------------------------------
|
1433 |
|
|
COUNTER_PROCESS : process (Clk) is
|
1434 |
|
|
begin
|
1435 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1436 |
|
|
if (Reset = '1') then
|
1437 |
|
|
count <= 0;
|
1438 |
|
|
EN_16x_Baud <= '0';
|
1439 |
|
|
else
|
1440 |
|
|
if (count = 0) then
|
1441 |
|
|
count <= C_RATIO-1;
|
1442 |
|
|
EN_16x_Baud <= '1';
|
1443 |
|
|
else
|
1444 |
|
|
count <= count - 1;
|
1445 |
|
|
EN_16x_Baud <= '0';
|
1446 |
|
|
end if;
|
1447 |
|
|
end if;
|
1448 |
|
|
end if;
|
1449 |
|
|
end process COUNTER_PROCESS;
|
1450 |
|
|
|
1451 |
|
|
end architecture RTL;
|
1452 |
|
|
|
1453 |
|
|
|
1454 |
|
|
-------------------------------------------------------------------------------
|
1455 |
|
|
-- uartlite_core - entity/architecture pair
|
1456 |
|
|
-------------------------------------------------------------------------------
|
1457 |
|
|
--
|
1458 |
|
|
-- *******************************************************************
|
1459 |
|
|
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
|
1460 |
|
|
-- -- ** *
|
1461 |
|
|
-- -- ** This file contains confidential and proprietary information *
|
1462 |
|
|
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
|
1463 |
|
|
-- -- ** international copyright and other intellectual property *
|
1464 |
|
|
-- -- ** laws. *
|
1465 |
|
|
-- -- ** *
|
1466 |
|
|
-- -- ** DISCLAIMER *
|
1467 |
|
|
-- -- ** This disclaimer is not a license and does not grant any *
|
1468 |
|
|
-- -- ** rights to the materials distributed herewith. Except as *
|
1469 |
|
|
-- -- ** otherwise provided in a valid license issued to you by *
|
1470 |
|
|
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
|
1471 |
|
|
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
1472 |
|
|
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
1473 |
|
|
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
1474 |
|
|
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
1475 |
|
|
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
1476 |
|
|
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
|
1477 |
|
|
-- -- ** including negligence, or under any other theory of *
|
1478 |
|
|
-- -- ** liability) for any loss or damage of any kind or nature *
|
1479 |
|
|
-- -- ** related to, arising under or in connection with these *
|
1480 |
|
|
-- -- ** materials, including for any direct, or any indirect, *
|
1481 |
|
|
-- -- ** special, incidental, or consequential loss or damage *
|
1482 |
|
|
-- -- ** (including loss of data, profits, goodwill, or any type of *
|
1483 |
|
|
-- -- ** loss or damage suffered as a result of any action brought *
|
1484 |
|
|
-- -- ** by a third party) even if such damage or loss was *
|
1485 |
|
|
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
|
1486 |
|
|
-- -- ** possibility of the same. *
|
1487 |
|
|
-- -- ** *
|
1488 |
|
|
-- -- ** CRITICAL APPLICATIONS *
|
1489 |
|
|
-- -- ** Xilinx products are not designed or intended to be fail- *
|
1490 |
|
|
-- -- ** safe, or for use in any application requiring fail-safe *
|
1491 |
|
|
-- -- ** performance, such as life-support or safety devices or *
|
1492 |
|
|
-- -- ** systems, Class III medical devices, nuclear facilities, *
|
1493 |
|
|
-- -- ** applications related to the deployment of airbags, or any *
|
1494 |
|
|
-- -- ** other applications that could lead to death, personal *
|
1495 |
|
|
-- -- ** injury, or severe property or environmental damage *
|
1496 |
|
|
-- -- ** (individually and collectively, "Critical *
|
1497 |
|
|
-- -- ** Applications"). Customer assumes the sole risk and *
|
1498 |
|
|
-- -- ** liability of any use of Xilinx products in Critical *
|
1499 |
|
|
-- -- ** Applications, subject only to applicable laws and *
|
1500 |
|
|
-- -- ** regulations governing limitations on product liability. *
|
1501 |
|
|
-- -- ** *
|
1502 |
|
|
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
1503 |
|
|
-- -- ** PART OF THIS FILE AT ALL TIMES. *
|
1504 |
|
|
-- *******************************************************************
|
1505 |
|
|
--
|
1506 |
|
|
-------------------------------------------------------------------------------
|
1507 |
|
|
-- Filename: uartlite_core.vhd
|
1508 |
|
|
-- Version: v2.0
|
1509 |
|
|
-- Description: UART Lite core for implementing UART logic
|
1510 |
|
|
--
|
1511 |
|
|
-- VHDL-Standard: VHDL'93
|
1512 |
|
|
-------------------------------------------------------------------------------
|
1513 |
|
|
-------------------------------------------------------------------------------
|
1514 |
|
|
-- Naming Conventions:
|
1515 |
|
|
-- active low signals: "*_n"
|
1516 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
1517 |
|
|
-- reset signals: "rst", "rst_n"
|
1518 |
|
|
-- generics: "C_*"
|
1519 |
|
|
-- user defined types: "*_TYPE"
|
1520 |
|
|
-- state machine next state: "*_ns"
|
1521 |
|
|
-- state machine current state: "*_cs"
|
1522 |
|
|
-- combinatorial signals: "*_com"
|
1523 |
|
|
-- pipelined or register delay signals: "*_d#"
|
1524 |
|
|
-- counter signals: "*cnt*"
|
1525 |
|
|
-- clock enable signals: "*_ce"
|
1526 |
|
|
-- internal version of output port "*_i"
|
1527 |
|
|
-- device pins: "*_pin"
|
1528 |
|
|
-- ports: - Names begin with Uppercase
|
1529 |
|
|
-- processes: "*_PROCESS"
|
1530 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
1531 |
|
|
-------------------------------------------------------------------------------
|
1532 |
|
|
library IEEE;
|
1533 |
|
|
use IEEE.std_logic_1164.all;
|
1534 |
|
|
|
1535 |
|
|
library axi_uartlite_v2_0_19;
|
1536 |
|
|
-- baudrate refered from axi_uartlite_v2_0_19
|
1537 |
|
|
use axi_uartlite_v2_0_19.baudrate;
|
1538 |
|
|
-- uartlite_rx refered from axi_uartlite_v2_0_19
|
1539 |
|
|
use axi_uartlite_v2_0_19.uartlite_rx;
|
1540 |
|
|
-- uartlite_tx refered from axi_uartlite_v2_0_19
|
1541 |
|
|
use axi_uartlite_v2_0_19.uartlite_tx;
|
1542 |
|
|
|
1543 |
|
|
-------------------------------------------------------------------------------
|
1544 |
|
|
-- Port Declaration
|
1545 |
|
|
-------------------------------------------------------------------------------
|
1546 |
|
|
-------------------------------------------------------------------------------
|
1547 |
|
|
-- Definition of Generics :
|
1548 |
|
|
-------------------------------------------------------------------------------
|
1549 |
|
|
-- UART Lite generics
|
1550 |
|
|
-- C_DATA_BITS -- The number of data bits in the serial frame
|
1551 |
|
|
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
|
1552 |
|
|
-- peripheral in Hz
|
1553 |
|
|
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
|
1554 |
|
|
-- C_USE_PARITY -- Determines whether parity is used or not
|
1555 |
|
|
-- C_ODD_PARITY -- If parity is used determines whether parity
|
1556 |
|
|
-- is even or odd
|
1557 |
|
|
-- System generics
|
1558 |
|
|
-- C_FAMILY -- Xilinx FPGA Family
|
1559 |
|
|
-------------------------------------------------------------------------------
|
1560 |
|
|
-------------------------------------------------------------------------------
|
1561 |
|
|
-- Definition of Ports :
|
1562 |
|
|
-------------------------------------------------------------------------------
|
1563 |
|
|
-- System Signals
|
1564 |
|
|
-- Clk -- Clock signal
|
1565 |
|
|
-- Rst -- Reset signal
|
1566 |
|
|
-- Slave attachment interface
|
1567 |
|
|
-- bus2ip_data -- bus2ip data signal
|
1568 |
|
|
-- bus2ip_rdce -- bus2ip read CE
|
1569 |
|
|
-- bus2ip_wrce -- bus2ip write CE
|
1570 |
|
|
-- ip2bus_rdack -- ip2bus read acknowledgement
|
1571 |
|
|
-- ip2bus_wrack -- ip2bus write acknowledgement
|
1572 |
|
|
-- ip2bus_error -- ip2bus error
|
1573 |
|
|
-- SIn_DBus -- ip2bus data
|
1574 |
|
|
-- UART Lite interface
|
1575 |
|
|
-- RX -- Receive Data
|
1576 |
|
|
-- TX -- Transmit Data
|
1577 |
|
|
-- Interrupt -- UART Interrupt
|
1578 |
|
|
-------------------------------------------------------------------------------
|
1579 |
|
|
-------------------------------------------------------------------------------
|
1580 |
|
|
-- Entity Section
|
1581 |
|
|
-------------------------------------------------------------------------------
|
1582 |
|
|
entity uartlite_core is
|
1583 |
|
|
generic
|
1584 |
|
|
(
|
1585 |
|
|
C_FAMILY : string := "virtex7";
|
1586 |
|
|
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
|
1587 |
|
|
C_BAUDRATE : integer := 9600;
|
1588 |
|
|
C_DATA_BITS : integer range 5 to 8 := 8;
|
1589 |
|
|
C_USE_PARITY : integer range 0 to 1 := 0;
|
1590 |
|
|
C_ODD_PARITY : integer range 0 to 1 := 0
|
1591 |
|
|
);
|
1592 |
|
|
port
|
1593 |
|
|
(
|
1594 |
|
|
Clk : in std_logic;
|
1595 |
|
|
Reset : in std_logic;
|
1596 |
|
|
-- IPIF signals
|
1597 |
|
|
bus2ip_data : in std_logic_vector(0 to 7);
|
1598 |
|
|
bus2ip_rdce : in std_logic_vector(0 to 3);
|
1599 |
|
|
bus2ip_wrce : in std_logic_vector(0 to 3);
|
1600 |
|
|
bus2ip_cs : in std_logic;
|
1601 |
|
|
ip2bus_rdack : out std_logic;
|
1602 |
|
|
ip2bus_wrack : out std_logic;
|
1603 |
|
|
ip2bus_error : out std_logic;
|
1604 |
|
|
SIn_DBus : out std_logic_vector(0 to 7);
|
1605 |
|
|
-- UART signals
|
1606 |
|
|
RX : in std_logic;
|
1607 |
|
|
TX : out std_logic;
|
1608 |
|
|
Interrupt : out std_logic
|
1609 |
|
|
);
|
1610 |
|
|
end entity uartlite_core;
|
1611 |
|
|
|
1612 |
|
|
-------------------------------------------------------------------------------
|
1613 |
|
|
-- Architecture Section
|
1614 |
|
|
-------------------------------------------------------------------------------
|
1615 |
|
|
architecture RTL of uartlite_core is
|
1616 |
|
|
-- Pragma Added to supress synth warnings
|
1617 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
1618 |
|
|
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
|
1619 |
|
|
|
1620 |
|
|
---------------------------------------------------------------------------
|
1621 |
|
|
-- function declarations
|
1622 |
|
|
---------------------------------------------------------------------------
|
1623 |
|
|
|
1624 |
|
|
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
|
1625 |
|
|
C_BAUDRATE : integer ) return Integer is
|
1626 |
|
|
|
1627 |
|
|
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
|
1628 |
|
|
constant REMAINDER : integer :=
|
1629 |
|
|
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
|
1630 |
|
|
constant RATIO : integer :=
|
1631 |
|
|
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
|
1632 |
|
|
|
1633 |
|
|
begin
|
1634 |
|
|
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
|
1635 |
|
|
return (RATIO + 1);
|
1636 |
|
|
else
|
1637 |
|
|
return RATIO;
|
1638 |
|
|
end if;
|
1639 |
|
|
end function CALC_RATIO;
|
1640 |
|
|
|
1641 |
|
|
|
1642 |
|
|
---------------------------------------------------------------------------
|
1643 |
|
|
-- Constant declarations
|
1644 |
|
|
---------------------------------------------------------------------------
|
1645 |
|
|
|
1646 |
|
|
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
|
1647 |
|
|
|
1648 |
|
|
---------------------------------------------------------------------------
|
1649 |
|
|
-- Signal declarations
|
1650 |
|
|
---------------------------------------------------------------------------
|
1651 |
|
|
-- Read Only
|
1652 |
|
|
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
|
1653 |
|
|
|
1654 |
|
|
-- bit 7 rx_Data_Present
|
1655 |
|
|
-- bit 6 rx_Buffer_Full
|
1656 |
|
|
-- bit 5 tx_Buffer_Empty
|
1657 |
|
|
-- bit 4 tx_Buffer_Full
|
1658 |
|
|
-- bit 3 enable_interrupts
|
1659 |
|
|
-- bit 2 Overrun Error
|
1660 |
|
|
-- bit 1 Frame Error
|
1661 |
|
|
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
|
1662 |
|
|
|
1663 |
|
|
-- Write Only
|
1664 |
|
|
-- Below mentioned bits belong to Control Register and are declared as
|
1665 |
|
|
-- signals below
|
1666 |
|
|
-- bit 0-2 Dont'Care
|
1667 |
|
|
-- bit 3 enable_interrupts
|
1668 |
|
|
-- bit 4-5 Dont'Care
|
1669 |
|
|
-- bit 6 Reset_RX_FIFO
|
1670 |
|
|
-- bit 7 Reset_TX_FIFO
|
1671 |
|
|
|
1672 |
|
|
signal en_16x_Baud : std_logic;
|
1673 |
|
|
signal enable_interrupts : std_logic;
|
1674 |
|
|
signal reset_RX_FIFO : std_logic;
|
1675 |
|
|
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
|
1676 |
|
|
signal rx_Data_Present : std_logic;
|
1677 |
|
|
signal rx_Buffer_Full : std_logic;
|
1678 |
|
|
signal rx_Frame_Error : std_logic;
|
1679 |
|
|
signal rx_Overrun_Error : std_logic;
|
1680 |
|
|
signal rx_Parity_Error : std_logic;
|
1681 |
|
|
signal clr_Status : std_logic;
|
1682 |
|
|
signal reset_TX_FIFO : std_logic;
|
1683 |
|
|
signal tx_Buffer_Full : std_logic;
|
1684 |
|
|
signal tx_Buffer_Empty : std_logic;
|
1685 |
|
|
signal tx_Buffer_Empty_Pre : std_logic;
|
1686 |
|
|
signal rx_Data_Present_Pre : std_logic;
|
1687 |
|
|
|
1688 |
|
|
begin -- architecture IMP
|
1689 |
|
|
|
1690 |
|
|
---------------------------------------------------------------------------
|
1691 |
|
|
-- Generating the acknowledgement and error signals
|
1692 |
|
|
---------------------------------------------------------------------------
|
1693 |
|
|
|
1694 |
|
|
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
|
1695 |
|
|
or bus2ip_rdce(3);
|
1696 |
|
|
|
1697 |
|
|
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
|
1698 |
|
|
or bus2ip_wrce(2);
|
1699 |
|
|
|
1700 |
|
|
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
|
1701 |
|
|
(bus2ip_wrce(1) and tx_Buffer_Full) );
|
1702 |
|
|
-------------------------------------------------------------------------
|
1703 |
|
|
-- BAUD_RATE_I : Instansiating the baudrate module
|
1704 |
|
|
-------------------------------------------------------------------------
|
1705 |
|
|
BAUD_RATE_I : entity axi_uartlite_v2_0_19.baudrate
|
1706 |
|
|
generic map
|
1707 |
|
|
(
|
1708 |
|
|
C_RATIO => RATIO
|
1709 |
|
|
)
|
1710 |
|
|
port map
|
1711 |
|
|
(
|
1712 |
|
|
Clk => Clk,
|
1713 |
|
|
Reset => Reset,
|
1714 |
|
|
EN_16x_Baud => en_16x_Baud
|
1715 |
|
|
);
|
1716 |
|
|
|
1717 |
|
|
-------------------------------------------------------------------------
|
1718 |
|
|
-- Status register handling
|
1719 |
|
|
-------------------------------------------------------------------------
|
1720 |
|
|
status_reg(7) <= rx_Data_Present;
|
1721 |
|
|
status_reg(6) <= rx_Buffer_Full;
|
1722 |
|
|
status_reg(5) <= tx_Buffer_Empty;
|
1723 |
|
|
status_reg(4) <= tx_Buffer_Full;
|
1724 |
|
|
status_reg(3) <= enable_interrupts;
|
1725 |
|
|
|
1726 |
|
|
-------------------------------------------------------------------------
|
1727 |
|
|
-- CLEAR_STATUS_REG : Process to clear status register
|
1728 |
|
|
-------------------------------------------------------------------------
|
1729 |
|
|
CLEAR_STATUS_REG : process (Clk) is
|
1730 |
|
|
begin -- process Ctrl_Reg_DFF
|
1731 |
|
|
if Clk'event and Clk = '1' then
|
1732 |
|
|
if Reset = '1' then
|
1733 |
|
|
clr_Status <= '0';
|
1734 |
|
|
else
|
1735 |
|
|
clr_Status <= bus2ip_rdce(2);
|
1736 |
|
|
end if;
|
1737 |
|
|
end if;
|
1738 |
|
|
end process CLEAR_STATUS_REG;
|
1739 |
|
|
|
1740 |
|
|
-------------------------------------------------------------------------
|
1741 |
|
|
-- Process to register rx_Overrun_Error
|
1742 |
|
|
-------------------------------------------------------------------------
|
1743 |
|
|
RX_OVERRUN_ERROR_DFF: Process (Clk) is
|
1744 |
|
|
begin
|
1745 |
|
|
if (Clk'event and Clk = '1') then
|
1746 |
|
|
if ((Reset = '1') or (clr_Status = '1')) then
|
1747 |
|
|
status_reg(2) <= '0';
|
1748 |
|
|
elsif (rx_Overrun_Error = '1') then
|
1749 |
|
|
status_reg(2) <= '1';
|
1750 |
|
|
end if;
|
1751 |
|
|
end if;
|
1752 |
|
|
end process RX_OVERRUN_ERROR_DFF;
|
1753 |
|
|
|
1754 |
|
|
-------------------------------------------------------------------------
|
1755 |
|
|
-- Process to register rx_Frame_Error
|
1756 |
|
|
-------------------------------------------------------------------------
|
1757 |
|
|
RX_FRAME_ERROR_DFF: Process (Clk) is
|
1758 |
|
|
begin
|
1759 |
|
|
if (Clk'event and Clk = '1') then
|
1760 |
|
|
if (Reset = '1') then
|
1761 |
|
|
status_reg(1) <= '0';
|
1762 |
|
|
else
|
1763 |
|
|
if (clr_Status = '1') then
|
1764 |
|
|
status_reg(1) <= '0';
|
1765 |
|
|
elsif (rx_Frame_Error = '1') then
|
1766 |
|
|
status_reg(1) <= '1';
|
1767 |
|
|
end if;
|
1768 |
|
|
end if;
|
1769 |
|
|
end if;
|
1770 |
|
|
end process RX_FRAME_ERROR_DFF;
|
1771 |
|
|
|
1772 |
|
|
-------------------------------------------------------------------------
|
1773 |
|
|
-- If C_USE_PARITY = 1, register rx_Parity_Error
|
1774 |
|
|
-------------------------------------------------------------------------
|
1775 |
|
|
USING_PARITY : if (C_USE_PARITY = 1) generate
|
1776 |
|
|
RX_PARITY_ERROR_DFF: Process (Clk) is
|
1777 |
|
|
begin
|
1778 |
|
|
if (Clk'event and Clk = '1') then
|
1779 |
|
|
if (Reset = '1') then
|
1780 |
|
|
status_reg(0) <= '0';
|
1781 |
|
|
else
|
1782 |
|
|
if (clr_Status = '1') then
|
1783 |
|
|
status_reg(0) <= '0';
|
1784 |
|
|
elsif (rx_Parity_Error = '1') then
|
1785 |
|
|
status_reg(0) <= '1';
|
1786 |
|
|
end if;
|
1787 |
|
|
end if;
|
1788 |
|
|
end if;
|
1789 |
|
|
end process RX_PARITY_ERROR_DFF;
|
1790 |
|
|
end generate USING_PARITY;
|
1791 |
|
|
|
1792 |
|
|
-------------------------------------------------------------------------
|
1793 |
|
|
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
|
1794 |
|
|
-------------------------------------------------------------------------
|
1795 |
|
|
NO_PARITY : if (C_USE_PARITY = 0) generate
|
1796 |
|
|
status_reg(0) <= '0';
|
1797 |
|
|
end generate NO_PARITY;
|
1798 |
|
|
|
1799 |
|
|
-------------------------------------------------------------------------
|
1800 |
|
|
-- CTRL_REG_DFF : Control Register Handling
|
1801 |
|
|
-------------------------------------------------------------------------
|
1802 |
|
|
CTRL_REG_DFF : process (Clk) is
|
1803 |
|
|
begin -- process Ctrl_Reg_DFF
|
1804 |
|
|
if Clk'event and Clk = '1' then -- rising clock edge
|
1805 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
1806 |
|
|
reset_TX_FIFO <= '1';
|
1807 |
|
|
reset_RX_FIFO <= '1';
|
1808 |
|
|
enable_interrupts <= '0';
|
1809 |
|
|
elsif (bus2ip_wrce(3) = '1') then
|
1810 |
|
|
reset_RX_FIFO <= bus2ip_data(6);
|
1811 |
|
|
reset_TX_FIFO <= bus2ip_data(7);
|
1812 |
|
|
enable_interrupts <= bus2ip_data(3);
|
1813 |
|
|
else
|
1814 |
|
|
reset_TX_FIFO <= '0';
|
1815 |
|
|
reset_RX_FIFO <= '0';
|
1816 |
|
|
end if;
|
1817 |
|
|
end if;
|
1818 |
|
|
end process CTRL_REG_DFF;
|
1819 |
|
|
|
1820 |
|
|
-------------------------------------------------------------------------
|
1821 |
|
|
-- Tx Fifo Interrupt handling
|
1822 |
|
|
-------------------------------------------------------------------------
|
1823 |
|
|
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
|
1824 |
|
|
begin
|
1825 |
|
|
if (Clk'event and Clk = '1') then -- rising clock edge
|
1826 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
1827 |
|
|
tx_Buffer_Empty_Pre <= '0';
|
1828 |
|
|
else
|
1829 |
|
|
if (bus2ip_wrce(1) = '1') then
|
1830 |
|
|
tx_Buffer_Empty_Pre <= '0';
|
1831 |
|
|
else
|
1832 |
|
|
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
|
1833 |
|
|
end if;
|
1834 |
|
|
end if;
|
1835 |
|
|
end if;
|
1836 |
|
|
end process TX_BUFFER_EMPTY_DFF_I;
|
1837 |
|
|
|
1838 |
|
|
-------------------------------------------------------------------------
|
1839 |
|
|
-- Rx Fifo Interrupt handling
|
1840 |
|
|
-------------------------------------------------------------------------
|
1841 |
|
|
RX_BUFFER_DATA_DFF_I: Process (Clk) is
|
1842 |
|
|
begin
|
1843 |
|
|
if (Clk'event and Clk = '1') then -- rising clock edge
|
1844 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
1845 |
|
|
rx_Data_Present_Pre <= '0';
|
1846 |
|
|
else
|
1847 |
|
|
if (bus2ip_rdce(0) = '1') then
|
1848 |
|
|
rx_Data_Present_Pre <= '0';
|
1849 |
|
|
else
|
1850 |
|
|
rx_Data_Present_Pre <= rx_Data_Present;
|
1851 |
|
|
end if;
|
1852 |
|
|
end if;
|
1853 |
|
|
end if;
|
1854 |
|
|
end process RX_BUFFER_DATA_DFF_I;
|
1855 |
|
|
|
1856 |
|
|
-------------------------------------------------------------------------
|
1857 |
|
|
-- Interrupt register handling
|
1858 |
|
|
-------------------------------------------------------------------------
|
1859 |
|
|
INTERRUPT_DFF: process (Clk) is
|
1860 |
|
|
begin
|
1861 |
|
|
if Clk'event and Clk = '1' then
|
1862 |
|
|
if Reset = '1' then -- synchronous reset (active high)
|
1863 |
|
|
Interrupt <= '0';
|
1864 |
|
|
else
|
1865 |
|
|
Interrupt <= enable_interrupts and
|
1866 |
|
|
((rx_Data_Present and not rx_Data_Present_Pre) or
|
1867 |
|
|
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
|
1868 |
|
|
end if;
|
1869 |
|
|
end if;
|
1870 |
|
|
end process INTERRUPT_DFF;
|
1871 |
|
|
|
1872 |
|
|
-------------------------------------------------------------------------
|
1873 |
|
|
-- READ_MUX : Read bus interface handling
|
1874 |
|
|
-------------------------------------------------------------------------
|
1875 |
|
|
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
|
1876 |
|
|
begin -- process Read_Mux
|
1877 |
|
|
if (bus2ip_rdce(2) = '1') then
|
1878 |
|
|
SIn_DBus <= status_reg;
|
1879 |
|
|
elsif (bus2ip_rdce(0) = '1') then
|
1880 |
|
|
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
|
1881 |
|
|
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
|
1882 |
|
|
else
|
1883 |
|
|
SIn_DBus <= (others => '0');
|
1884 |
|
|
end if;
|
1885 |
|
|
end process READ_MUX;
|
1886 |
|
|
|
1887 |
|
|
-------------------------------------------------------------------------
|
1888 |
|
|
-- UARTLITE_RX_I : Instansiating the receive module
|
1889 |
|
|
-------------------------------------------------------------------------
|
1890 |
|
|
UARTLITE_RX_I : entity axi_uartlite_v2_0_19.uartlite_rx
|
1891 |
|
|
generic map
|
1892 |
|
|
(
|
1893 |
|
|
C_FAMILY => C_FAMILY,
|
1894 |
|
|
C_DATA_BITS => C_DATA_BITS,
|
1895 |
|
|
C_USE_PARITY => C_USE_PARITY,
|
1896 |
|
|
C_ODD_PARITY => C_ODD_PARITY
|
1897 |
|
|
)
|
1898 |
|
|
port map
|
1899 |
|
|
(
|
1900 |
|
|
Clk => Clk,
|
1901 |
|
|
Reset => Reset,
|
1902 |
|
|
EN_16x_Baud => en_16x_Baud,
|
1903 |
|
|
RX => RX,
|
1904 |
|
|
Read_RX_FIFO => bus2ip_rdce(0),
|
1905 |
|
|
Reset_RX_FIFO => reset_RX_FIFO,
|
1906 |
|
|
RX_Data => rx_Data,
|
1907 |
|
|
RX_Data_Present => rx_Data_Present,
|
1908 |
|
|
RX_Buffer_Full => rx_Buffer_Full,
|
1909 |
|
|
RX_Frame_Error => rx_Frame_Error,
|
1910 |
|
|
RX_Overrun_Error => rx_Overrun_Error,
|
1911 |
|
|
RX_Parity_Error => rx_Parity_Error
|
1912 |
|
|
);
|
1913 |
|
|
|
1914 |
|
|
-------------------------------------------------------------------------
|
1915 |
|
|
-- UARTLITE_TX_I : Instansiating the transmit module
|
1916 |
|
|
-------------------------------------------------------------------------
|
1917 |
|
|
UARTLITE_TX_I : entity axi_uartlite_v2_0_19.uartlite_tx
|
1918 |
|
|
generic map
|
1919 |
|
|
(
|
1920 |
|
|
C_FAMILY => C_FAMILY,
|
1921 |
|
|
C_DATA_BITS => C_DATA_BITS,
|
1922 |
|
|
C_USE_PARITY => C_USE_PARITY,
|
1923 |
|
|
C_ODD_PARITY => C_ODD_PARITY
|
1924 |
|
|
)
|
1925 |
|
|
port map
|
1926 |
|
|
(
|
1927 |
|
|
Clk => Clk,
|
1928 |
|
|
Reset => Reset,
|
1929 |
|
|
EN_16x_Baud => en_16x_Baud,
|
1930 |
|
|
TX => TX,
|
1931 |
|
|
Write_TX_FIFO => bus2ip_wrce(1),
|
1932 |
|
|
Reset_TX_FIFO => reset_TX_FIFO,
|
1933 |
|
|
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
|
1934 |
|
|
TX_Buffer_Full => tx_Buffer_Full,
|
1935 |
|
|
TX_Buffer_Empty => tx_Buffer_Empty
|
1936 |
|
|
);
|
1937 |
|
|
|
1938 |
|
|
end architecture RTL;
|
1939 |
|
|
|
1940 |
|
|
|
1941 |
|
|
-------------------------------------------------------------------------------
|
1942 |
|
|
-- axi_uartlite - entity/architecture pair
|
1943 |
|
|
-------------------------------------------------------------------------------
|
1944 |
|
|
--
|
1945 |
|
|
-- *******************************************************************
|
1946 |
|
|
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
|
1947 |
|
|
-- -- ** *
|
1948 |
|
|
-- -- ** This file contains confidential and proprietary information *
|
1949 |
|
|
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
|
1950 |
|
|
-- -- ** international copyright and other intellectual property *
|
1951 |
|
|
-- -- ** laws. *
|
1952 |
|
|
-- -- ** *
|
1953 |
|
|
-- -- ** DISCLAIMER *
|
1954 |
|
|
-- -- ** This disclaimer is not a license and does not grant any *
|
1955 |
|
|
-- -- ** rights to the materials distributed herewith. Except as *
|
1956 |
|
|
-- -- ** otherwise provided in a valid license issued to you by *
|
1957 |
|
|
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
|
1958 |
|
|
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
|
1959 |
|
|
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
|
1960 |
|
|
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
|
1961 |
|
|
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
|
1962 |
|
|
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
|
1963 |
|
|
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
|
1964 |
|
|
-- -- ** including negligence, or under any other theory of *
|
1965 |
|
|
-- -- ** liability) for any loss or damage of any kind or nature *
|
1966 |
|
|
-- -- ** related to, arising under or in connection with these *
|
1967 |
|
|
-- -- ** materials, including for any direct, or any indirect, *
|
1968 |
|
|
-- -- ** special, incidental, or consequential loss or damage *
|
1969 |
|
|
-- -- ** (including loss of data, profits, goodwill, or any type of *
|
1970 |
|
|
-- -- ** loss or damage suffered as a result of any action brought *
|
1971 |
|
|
-- -- ** by a third party) even if such damage or loss was *
|
1972 |
|
|
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
|
1973 |
|
|
-- -- ** possibility of the same. *
|
1974 |
|
|
-- -- ** *
|
1975 |
|
|
-- -- ** CRITICAL APPLICATIONS *
|
1976 |
|
|
-- -- ** Xilinx products are not designed or intended to be fail- *
|
1977 |
|
|
-- -- ** safe, or for use in any application requiring fail-safe *
|
1978 |
|
|
-- -- ** performance, such as life-support or safety devices or *
|
1979 |
|
|
-- -- ** systems, Class III medical devices, nuclear facilities, *
|
1980 |
|
|
-- -- ** applications related to the deployment of airbags, or any *
|
1981 |
|
|
-- -- ** other applications that could lead to death, personal *
|
1982 |
|
|
-- -- ** injury, or severe property or environmental damage *
|
1983 |
|
|
-- -- ** (individually and collectively, "Critical *
|
1984 |
|
|
-- -- ** Applications"). Customer assumes the sole risk and *
|
1985 |
|
|
-- -- ** liability of any use of Xilinx products in Critical *
|
1986 |
|
|
-- -- ** Applications, subject only to applicable laws and *
|
1987 |
|
|
-- -- ** regulations governing limitations on product liability. *
|
1988 |
|
|
-- -- ** *
|
1989 |
|
|
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
|
1990 |
|
|
-- -- ** PART OF THIS FILE AT ALL TIMES. *
|
1991 |
|
|
-- *******************************************************************
|
1992 |
|
|
--
|
1993 |
|
|
-------------------------------------------------------------------------------
|
1994 |
|
|
-- Filename: axi_uartlite.vhd
|
1995 |
|
|
-- Version: v1.02.a
|
1996 |
|
|
-- Description: AXI UART Lite Interface
|
1997 |
|
|
--
|
1998 |
|
|
-- VHDL-Standard: VHDL'93
|
1999 |
|
|
-------------------------------------------------------------------------------
|
2000 |
|
|
-------------------------------------------------------------------------------
|
2001 |
|
|
-- Naming Conventions:
|
2002 |
|
|
-- active low signals: "*_n"
|
2003 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
2004 |
|
|
-- reset signals: "rst", "rst_n"
|
2005 |
|
|
-- generics: "C_*"
|
2006 |
|
|
-- user defined types: "*_TYPE"
|
2007 |
|
|
-- state machine next state: "*_ns"
|
2008 |
|
|
-- state machine current state: "*_cs"
|
2009 |
|
|
-- combinatorial signals: "*_com"
|
2010 |
|
|
-- pipelined or register delay signals: "*_d#"
|
2011 |
|
|
-- counter signals: "*cnt*"
|
2012 |
|
|
-- clock enable signals: "*_ce"
|
2013 |
|
|
-- internal version of output port "*_i"
|
2014 |
|
|
-- device pins: "*_pin"
|
2015 |
|
|
-- ports: - Names begin with Uppercase
|
2016 |
|
|
-- processes: "*_PROCESS"
|
2017 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
2018 |
|
|
-------------------------------------------------------------------------------
|
2019 |
|
|
library IEEE;
|
2020 |
|
|
use IEEE.std_logic_1164.all;
|
2021 |
|
|
|
2022 |
|
|
library axi_lite_ipif_v3_0_4;
|
2023 |
|
|
-- SLV64_ARRAY_TYPE refered from ipif_pkg
|
2024 |
|
|
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
|
2025 |
|
|
-- INTEGER_ARRAY_TYPE refered from ipif_pkg
|
2026 |
|
|
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
|
2027 |
|
|
-- calc_num_ce comoponent refered from ipif_pkg
|
2028 |
|
|
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
|
2029 |
|
|
|
2030 |
|
|
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
|
2031 |
|
|
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
|
2032 |
|
|
|
2033 |
|
|
library axi_uartlite_v2_0_19;
|
2034 |
|
|
-- uartlite_core refered from axi_uartlite_v2_0_19
|
2035 |
|
|
use axi_uartlite_v2_0_19.uartlite_core;
|
2036 |
|
|
|
2037 |
|
|
-------------------------------------------------------------------------------
|
2038 |
|
|
-- Port Declaration
|
2039 |
|
|
-------------------------------------------------------------------------------
|
2040 |
|
|
-------------------------------------------------------------------------------
|
2041 |
|
|
-- Definition of Generics :
|
2042 |
|
|
-------------------------------------------------------------------------------
|
2043 |
|
|
-- System generics
|
2044 |
|
|
-- C_FAMILY -- Xilinx FPGA Family
|
2045 |
|
|
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
|
2046 |
|
|
-- peripheral in Hz
|
2047 |
|
|
-- AXI generics
|
2048 |
|
|
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
|
2049 |
|
|
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
|
2050 |
|
|
--
|
2051 |
|
|
-- UART Lite generics
|
2052 |
|
|
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
|
2053 |
|
|
-- C_DATA_BITS -- The number of data bits in the serial frame
|
2054 |
|
|
-- C_USE_PARITY -- Determines whether parity is used or not
|
2055 |
|
|
-- C_ODD_PARITY -- If parity is used determines whether parity
|
2056 |
|
|
-- is even or odd
|
2057 |
|
|
-------------------------------------------------------------------------------
|
2058 |
|
|
-------------------------------------------------------------------------------
|
2059 |
|
|
-- Definition of Ports :
|
2060 |
|
|
-------------------------------------------------------------------------------
|
2061 |
|
|
--System signals
|
2062 |
|
|
-- s_axi_aclk -- AXI Clock
|
2063 |
|
|
-- s_axi_aresetn -- AXI Reset
|
2064 |
|
|
-- Interrupt -- UART Interrupt
|
2065 |
|
|
--AXI signals
|
2066 |
|
|
-- s_axi_awaddr -- AXI Write address
|
2067 |
|
|
-- s_axi_awvalid -- Write address valid
|
2068 |
|
|
-- s_axi_awready -- Write address ready
|
2069 |
|
|
-- s_axi_wdata -- Write data
|
2070 |
|
|
-- s_axi_wstrb -- Write strobes
|
2071 |
|
|
-- s_axi_wvalid -- Write valid
|
2072 |
|
|
-- s_axi_wready -- Write ready
|
2073 |
|
|
-- s_axi_bresp -- Write response
|
2074 |
|
|
-- s_axi_bvalid -- Write response valid
|
2075 |
|
|
-- s_axi_bready -- Response ready
|
2076 |
|
|
-- s_axi_araddr -- Read address
|
2077 |
|
|
-- s_axi_arvalid -- Read address valid
|
2078 |
|
|
-- s_axi_arready -- Read address ready
|
2079 |
|
|
-- s_axi_rdata -- Read data
|
2080 |
|
|
-- s_axi_rresp -- Read response
|
2081 |
|
|
-- s_axi_rvalid -- Read valid
|
2082 |
|
|
-- s_axi_rready -- Read ready
|
2083 |
|
|
--UARTLite Interface Signals
|
2084 |
|
|
-- rx -- Receive Data
|
2085 |
|
|
-- tx -- Transmit Data
|
2086 |
|
|
-------------------------------------------------------------------------------
|
2087 |
|
|
-------------------------------------------------------------------------------
|
2088 |
|
|
-- Entity Section
|
2089 |
|
|
-------------------------------------------------------------------------------
|
2090 |
|
|
entity axi_uartlite is
|
2091 |
|
|
generic
|
2092 |
|
|
(
|
2093 |
|
|
-- -- System Parameter
|
2094 |
|
|
C_FAMILY : string := "virtex7";
|
2095 |
|
|
C_S_AXI_ACLK_FREQ_HZ : integer := 100_000_000;
|
2096 |
|
|
-- -- AXI Parameters
|
2097 |
|
|
C_S_AXI_ADDR_WIDTH : integer := 4;
|
2098 |
|
|
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
|
2099 |
|
|
-- -- UARTLite Parameters
|
2100 |
|
|
C_BAUDRATE : integer := 9600;
|
2101 |
|
|
C_DATA_BITS : integer range 5 to 8 := 8;
|
2102 |
|
|
C_USE_PARITY : integer range 0 to 1 := 0;
|
2103 |
|
|
C_ODD_PARITY : integer range 0 to 1 := 0
|
2104 |
|
|
);
|
2105 |
|
|
port
|
2106 |
|
|
(
|
2107 |
|
|
|
2108 |
|
|
-- System signals
|
2109 |
|
|
s_axi_aclk : in std_logic;
|
2110 |
|
|
s_axi_aresetn : in std_logic;
|
2111 |
|
|
interrupt : out std_logic;
|
2112 |
|
|
|
2113 |
|
|
-- AXI signals
|
2114 |
|
|
s_axi_awaddr : in std_logic_vector
|
2115 |
|
|
(3 downto 0);
|
2116 |
|
|
s_axi_awvalid : in std_logic;
|
2117 |
|
|
s_axi_awready : out std_logic;
|
2118 |
|
|
s_axi_wdata : in std_logic_vector
|
2119 |
|
|
(31 downto 0);
|
2120 |
|
|
s_axi_wstrb : in std_logic_vector
|
2121 |
|
|
(3 downto 0);
|
2122 |
|
|
s_axi_wvalid : in std_logic;
|
2123 |
|
|
s_axi_wready : out std_logic;
|
2124 |
|
|
s_axi_bresp : out std_logic_vector(1 downto 0);
|
2125 |
|
|
s_axi_bvalid : out std_logic;
|
2126 |
|
|
s_axi_bready : in std_logic;
|
2127 |
|
|
s_axi_araddr : in std_logic_vector
|
2128 |
|
|
(3 downto 0);
|
2129 |
|
|
s_axi_arvalid : in std_logic;
|
2130 |
|
|
s_axi_arready : out std_logic;
|
2131 |
|
|
s_axi_rdata : out std_logic_vector
|
2132 |
|
|
(31 downto 0);
|
2133 |
|
|
s_axi_rresp : out std_logic_vector(1 downto 0);
|
2134 |
|
|
s_axi_rvalid : out std_logic;
|
2135 |
|
|
s_axi_rready : in std_logic;
|
2136 |
|
|
|
2137 |
|
|
-- UARTLite Interface Signals
|
2138 |
|
|
rx : in std_logic;
|
2139 |
|
|
tx : out std_logic
|
2140 |
|
|
);
|
2141 |
|
|
|
2142 |
|
|
-------------------------------------------------------------------------------
|
2143 |
|
|
-- Attributes
|
2144 |
|
|
-------------------------------------------------------------------------------
|
2145 |
|
|
|
2146 |
|
|
-------------------------------------------------------------------------------
|
2147 |
|
|
-- Fan-Out attributes for XST
|
2148 |
|
|
-------------------------------------------------------------------------------
|
2149 |
|
|
|
2150 |
|
|
ATTRIBUTE MAX_FANOUT : string;
|
2151 |
|
|
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
|
2152 |
|
|
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
|
2153 |
|
|
|
2154 |
|
|
end entity axi_uartlite;
|
2155 |
|
|
|
2156 |
|
|
-------------------------------------------------------------------------------
|
2157 |
|
|
-- Architecture Section
|
2158 |
|
|
-------------------------------------------------------------------------------
|
2159 |
|
|
|
2160 |
|
|
architecture RTL of axi_uartlite is
|
2161 |
|
|
-- Pragma Added to supress synth warnings
|
2162 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
2163 |
|
|
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
|
2164 |
|
|
|
2165 |
|
|
|
2166 |
|
|
--------------------------------------------------------------------------
|
2167 |
|
|
-- Constant declarations
|
2168 |
|
|
--------------------------------------------------------------------------
|
2169 |
|
|
|
2170 |
|
|
constant ZEROES : std_logic_vector(31 downto 0)
|
2171 |
|
|
:= X"00000000";
|
2172 |
|
|
|
2173 |
|
|
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
|
2174 |
|
|
(
|
2175 |
|
|
-- UARTLite registers Base Address
|
2176 |
|
|
ZEROES & X"00000000",
|
2177 |
|
|
ZEROES & (X"00000000" or X"0000000F")
|
2178 |
|
|
);
|
2179 |
|
|
|
2180 |
|
|
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
|
2181 |
|
|
(
|
2182 |
|
|
|
2183 |
|
|
);
|
2184 |
|
|
|
2185 |
|
|
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
|
2186 |
|
|
:= X"0000000F";
|
2187 |
|
|
|
2188 |
|
|
constant C_USE_WSTRB : integer := 0;
|
2189 |
|
|
|
2190 |
|
|
constant C_DPHASE_TIMEOUT : integer := 0;
|
2191 |
|
|
|
2192 |
|
|
--------------------------------------------------------------------------
|
2193 |
|
|
-- Signal declarations
|
2194 |
|
|
--------------------------------------------------------------------------
|
2195 |
|
|
signal bus2ip_clk : std_logic;
|
2196 |
|
|
signal bus2ip_reset : std_logic;
|
2197 |
|
|
signal bus2ip_resetn : std_logic;
|
2198 |
|
|
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0)
|
2199 |
|
|
:= (others => '0');
|
2200 |
|
|
signal ip2bus_error : std_logic := '0';
|
2201 |
|
|
signal ip2bus_wrack : std_logic := '0';
|
2202 |
|
|
signal ip2bus_rdack : std_logic := '0';
|
2203 |
|
|
signal bus2ip_data : std_logic_vector
|
2204 |
|
|
(C_S_AXI_DATA_WIDTH - 1 downto 0);
|
2205 |
|
|
signal bus2ip_cs : std_logic_vector
|
2206 |
|
|
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
|
2207 |
|
|
signal bus2ip_rdce : std_logic_vector
|
2208 |
|
|
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
|
2209 |
|
|
signal bus2ip_wrce : std_logic_vector
|
2210 |
|
|
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
|
2211 |
|
|
|
2212 |
|
|
begin -- architecture IMP
|
2213 |
|
|
|
2214 |
|
|
--------------------------------------------------------------------------
|
2215 |
|
|
-- RESET signal assignment - IPIC RESET is active low
|
2216 |
|
|
--------------------------------------------------------------------------
|
2217 |
|
|
|
2218 |
|
|
bus2ip_reset <= not bus2ip_resetn;
|
2219 |
|
|
|
2220 |
|
|
--------------------------------------------------------------------------
|
2221 |
|
|
-- ip2bus_data assignment - as core is using maximum upto 8 bits
|
2222 |
|
|
--------------------------------------------------------------------------
|
2223 |
|
|
|
2224 |
|
|
ip2bus_data((C_S_AXI_DATA_WIDTH-1) downto 8) <= (others => '0');
|
2225 |
|
|
|
2226 |
|
|
--------------------------------------------------------------------------
|
2227 |
|
|
-- Instansiating the UART core
|
2228 |
|
|
--------------------------------------------------------------------------
|
2229 |
|
|
UARTLITE_CORE_I : entity axi_uartlite_v2_0_19.uartlite_core
|
2230 |
|
|
generic map
|
2231 |
|
|
(
|
2232 |
|
|
C_FAMILY => C_FAMILY,
|
2233 |
|
|
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
|
2234 |
|
|
C_BAUDRATE => C_BAUDRATE,
|
2235 |
|
|
C_DATA_BITS => C_DATA_BITS,
|
2236 |
|
|
C_USE_PARITY => C_USE_PARITY,
|
2237 |
|
|
C_ODD_PARITY => C_ODD_PARITY
|
2238 |
|
|
)
|
2239 |
|
|
port map
|
2240 |
|
|
(
|
2241 |
|
|
Clk => bus2ip_clk,
|
2242 |
|
|
Reset => bus2ip_reset,
|
2243 |
|
|
bus2ip_data => bus2ip_data(7 downto 0),
|
2244 |
|
|
bus2ip_rdce => bus2ip_rdce(3 downto 0),
|
2245 |
|
|
bus2ip_wrce => bus2ip_wrce(3 downto 0),
|
2246 |
|
|
bus2ip_cs => bus2ip_cs(0),
|
2247 |
|
|
ip2bus_rdack => ip2bus_rdack,
|
2248 |
|
|
ip2bus_wrack => ip2bus_wrack,
|
2249 |
|
|
ip2bus_error => ip2bus_error,
|
2250 |
|
|
SIn_DBus => ip2bus_data(7 downto 0),
|
2251 |
|
|
RX => rx,
|
2252 |
|
|
TX => tx,
|
2253 |
|
|
Interrupt => Interrupt
|
2254 |
|
|
);
|
2255 |
|
|
|
2256 |
|
|
--------------------------------------------------------------------------
|
2257 |
|
|
-- Instantiate AXI lite IPIF
|
2258 |
|
|
--------------------------------------------------------------------------
|
2259 |
|
|
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
|
2260 |
|
|
generic map
|
2261 |
|
|
(
|
2262 |
|
|
C_FAMILY => C_FAMILY,
|
2263 |
|
|
C_S_AXI_ADDR_WIDTH => 4,
|
2264 |
|
|
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
|
2265 |
|
|
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
|
2266 |
|
|
C_USE_WSTRB => C_USE_WSTRB,
|
2267 |
|
|
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
|
2268 |
|
|
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
|
2269 |
|
|
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
|
2270 |
|
|
)
|
2271 |
|
|
port map
|
2272 |
|
|
(
|
2273 |
|
|
S_AXI_ACLK => s_axi_aclk,
|
2274 |
|
|
S_AXI_ARESETN => s_axi_aresetn,
|
2275 |
|
|
S_AXI_AWADDR => s_axi_awaddr,
|
2276 |
|
|
S_AXI_AWVALID => s_axi_awvalid,
|
2277 |
|
|
S_AXI_AWREADY => s_axi_awready,
|
2278 |
|
|
S_AXI_WDATA => s_axi_wdata,
|
2279 |
|
|
S_AXI_WSTRB => s_axi_wstrb,
|
2280 |
|
|
S_AXI_WVALID => s_axi_wvalid,
|
2281 |
|
|
S_AXI_WREADY => s_axi_wready,
|
2282 |
|
|
S_AXI_BRESP => s_axi_bresp,
|
2283 |
|
|
S_AXI_BVALID => s_axi_bvalid,
|
2284 |
|
|
S_AXI_BREADY => s_axi_bready,
|
2285 |
|
|
S_AXI_ARADDR => s_axi_araddr,
|
2286 |
|
|
S_AXI_ARVALID => s_axi_arvalid,
|
2287 |
|
|
S_AXI_ARREADY => s_axi_arready,
|
2288 |
|
|
S_AXI_RDATA => s_axi_rdata,
|
2289 |
|
|
S_AXI_RRESP => s_axi_rresp,
|
2290 |
|
|
S_AXI_RVALID => s_axi_rvalid,
|
2291 |
|
|
S_AXI_RREADY => s_axi_rready,
|
2292 |
|
|
|
2293 |
|
|
-- IP Interconnect (IPIC) port signals
|
2294 |
|
|
Bus2IP_Clk => bus2ip_clk,
|
2295 |
|
|
Bus2IP_Resetn => bus2ip_resetn,
|
2296 |
|
|
IP2Bus_Data => ip2bus_data,
|
2297 |
|
|
IP2Bus_WrAck => ip2bus_wrack,
|
2298 |
|
|
IP2Bus_RdAck => ip2bus_rdack,
|
2299 |
|
|
IP2Bus_Error => ip2bus_error,
|
2300 |
|
|
Bus2IP_Addr => open,
|
2301 |
|
|
Bus2IP_Data => bus2ip_data,
|
2302 |
|
|
Bus2IP_RNW => open,
|
2303 |
|
|
Bus2IP_BE => open,
|
2304 |
|
|
Bus2IP_CS => bus2ip_cs,
|
2305 |
|
|
Bus2IP_RdCE => bus2ip_rdce,
|
2306 |
|
|
Bus2IP_WrCE => bus2ip_wrce
|
2307 |
|
|
);
|
2308 |
|
|
|
2309 |
|
|
end architecture RTL;
|
2310 |
|
|
|
2311 |
|
|
|