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Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.ip_user_files/] [sim_scripts/] [axi_uartlite_module/] [modelsim/] [compile.do] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev
vlib modelsim_lib/work
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vlib modelsim_lib/msim
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vlib modelsim_lib/msim/xil_defaultlib
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vlib modelsim_lib/msim/xpm
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vlib modelsim_lib/msim/axi_lite_ipif_v3_0_4
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vlib modelsim_lib/msim/lib_pkg_v1_0_2
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vlib modelsim_lib/msim/lib_srl_fifo_v1_0_2
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vlib modelsim_lib/msim/lib_cdc_v1_0_2
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vlib modelsim_lib/msim/axi_uartlite_v2_0_19
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vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
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vmap xpm modelsim_lib/msim/xpm
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vmap axi_lite_ipif_v3_0_4 modelsim_lib/msim/axi_lite_ipif_v3_0_4
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vmap lib_pkg_v1_0_2 modelsim_lib/msim/lib_pkg_v1_0_2
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vmap lib_srl_fifo_v1_0_2 modelsim_lib/msim/lib_srl_fifo_v1_0_2
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vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2
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vmap axi_uartlite_v2_0_19 modelsim_lib/msim/axi_uartlite_v2_0_19
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vlog -work xil_defaultlib -64 -incr -sv -L xil_defaultlib "+incdir+/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" "+incdir+/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" \
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"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
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vcom -work xpm -64 -93 \
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"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \
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vcom -work axi_lite_ipif_v3_0_4 -64 -93 \
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"../../../ipstatic/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \
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vcom -work lib_pkg_v1_0_2 -64 -93 \
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"../../../ipstatic/hdl/lib_pkg_v1_0_rfs.vhd" \
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vcom -work lib_srl_fifo_v1_0_2 -64 -93 \
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"../../../ipstatic/hdl/lib_srl_fifo_v1_0_rfs.vhd" \
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vcom -work lib_cdc_v1_0_2 -64 -93 \
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"../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
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vcom -work axi_uartlite_v2_0_19 -64 -93 \
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"../../../ipstatic/hdl/axi_uartlite_v2_0_vh_rfs.vhd" \
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vcom -work xil_defaultlib -64 -93 \
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"../../../../aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/sim/axi_uartlite_module.vhd" \
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vlog -work xil_defaultlib \
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"glbl.v"
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