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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.ip_user_files/] [sim_scripts/] [axi_uartlite_module/] [vcs/] [file_info.txt] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../../opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
2
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../../opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,
3
axi_lite_ipif_v3_0_vh_rfs.vhd,vhdl,axi_lite_ipif_v3_0_4,../../../ipstatic/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd,
4
lib_pkg_v1_0_rfs.vhd,vhdl,lib_pkg_v1_0_2,../../../ipstatic/hdl/lib_pkg_v1_0_rfs.vhd,
5
lib_srl_fifo_v1_0_rfs.vhd,vhdl,lib_srl_fifo_v1_0_2,../../../ipstatic/hdl/lib_srl_fifo_v1_0_rfs.vhd,
6
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd,
7
axi_uartlite_v2_0_vh_rfs.vhd,vhdl,axi_uartlite_v2_0_19,../../../ipstatic/hdl/axi_uartlite_v2_0_vh_rfs.vhd,
8
axi_uartlite_module.vhd,vhdl,xil_defaultlib,../../../../aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/sim/axi_uartlite_module.vhd,
9
glbl.v,Verilog,xil_defaultlib,glbl.v

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