URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.ip_user_files/] [sim_scripts/] [axi_uartlite_module_sim/] [riviera/] [simulate.do] - Blame information for rev 2

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onbreak {quit -force}
onerror {quit -force}
 
asim -t 1ps +access +r +m+axi_uartlite_module_sim -L xil_defaultlib -L xpm -L axi_lite_ipif_v3_0_4 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_cdc_v1_0_2 -L axi_uartlite_v2_0_19 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.axi_uartlite_module_sim xil_defaultlib.glbl
 
do {wave.do}
 
view wave
view structure
 
do {axi_uartlite_module_sim.udo}
 
run -all
 
endsim
 
quit -force

Line No.	Rev	Author	Line
1	2	vv_gulyaev	`onbreak {quit -force}`
2			`onerror {quit -force}`
3
4			`asim -t 1ps +access +r +m+axi_uartlite_module_sim -L xil_defaultlib -L xpm -L axi_lite_ipif_v3_0_4 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_cdc_v1_0_2 -L axi_uartlite_v2_0_19 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.axi_uartlite_module_sim xil_defaultlib.glbl`
5
6			`do {wave.do}`
7
8			`view wave`
9			`view structure`
10
11			`do {axi_uartlite_module_sim.udo}`
12
13			`run -all`
14
15			`endsim`
16
17			`quit -force`

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Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.ip_user_files/] [sim_scripts/] [axi_uartlite_module_sim/] [riviera/] [simulate.do] - Blame information for rev 2