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vv_gulyaev |
#!/bin/bash -f
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#*********************************************************************************************************
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# Vivado (TM) v2017.4 (64-bit)
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#
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# Filename : axi_uartlite_module_sim.sh
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# Simulator : Synopsys Verilog Compiler Simulator
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# Description : Simulation script for compiling, elaborating and verifying the project source files.
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# The script will automatically create the design libraries sub-directories in the run
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# directory, add the library logical mappings in the simulator setup file, create default
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# 'do/prj' file, execute compilation, elaboration and simulation steps.
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#
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# Generated by Vivado on Tue Jul 28 11:34:43 MSK 2020
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# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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#
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# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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#
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# usage: axi_uartlite_module_sim.sh [-help]
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# usage: axi_uartlite_module_sim.sh [-lib_map_path]
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# usage: axi_uartlite_module_sim.sh [-noclean_files]
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# usage: axi_uartlite_module_sim.sh [-reset_run]
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#
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# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
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# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
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# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
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# that points to these libraries and rerun export_simulation. For more information about this switch please
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# type 'export_simulation -help' in the Tcl shell.
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#
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# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
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# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
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# executing this script. Please type 'axi_uartlite_module_sim.sh -help' for more information.
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#
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# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
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#
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#*********************************************************************************************************
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# Directory path for design sources and include directories (if any) wrt this path
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ref_dir="."
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# Override directory with 'export_sim_ref_dir' env path value if set in the shell
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if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
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ref_dir="$export_sim_ref_dir"
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fi
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# Command line options
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vlogan_opts="-full64"
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vhdlan_opts="-full64"
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vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
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vcs_sim_opts="-ucli -licqueue -l simulate.log"
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# Design libraries
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design_libs=(xil_defaultlib xpm axi_lite_ipif_v3_0_4 lib_pkg_v1_0_2 lib_srl_fifo_v1_0_2 lib_cdc_v1_0_2 axi_uartlite_v2_0_19)
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# Simulation root library directory
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sim_lib_dir="vcs_lib"
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# Script info
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echo -e "axi_uartlite_module_sim.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n"
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# Main steps
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run()
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{
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check_args $# $1
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setup $1 $2
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compile
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elaborate
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simulate
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}
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# RUN_STEP: <compile>
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compile()
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{
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# Compile design files
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vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/xilinx_vip/include" \
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"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
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2>&1 | tee -a vlogan.log
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vhdlan -work xpm $vhdlan_opts \
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"/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \
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2>&1 | tee -a vhdlan.log
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vhdlan -work axi_lite_ipif_v3_0_4 $vhdlan_opts \
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"$ref_dir/../../../ipstatic/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd" \
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2>&1 | tee -a vhdlan.log
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vhdlan -work lib_pkg_v1_0_2 $vhdlan_opts \
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"$ref_dir/../../../ipstatic/hdl/lib_pkg_v1_0_rfs.vhd" \
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2>&1 | tee -a vhdlan.log
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vhdlan -work lib_srl_fifo_v1_0_2 $vhdlan_opts \
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"$ref_dir/../../../ipstatic/hdl/lib_srl_fifo_v1_0_rfs.vhd" \
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2>&1 | tee -a vhdlan.log
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vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \
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"$ref_dir/../../../ipstatic/hdl/lib_cdc_v1_0_rfs.vhd" \
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2>&1 | tee -a vhdlan.log
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vhdlan -work axi_uartlite_v2_0_19 $vhdlan_opts \
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"$ref_dir/../../../ipstatic/hdl/axi_uartlite_v2_0_vh_rfs.vhd" \
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2>&1 | tee -a vhdlan.log
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vhdlan -work xil_defaultlib $vhdlan_opts \
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"$ref_dir/../../../../aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/sim/axi_uartlite_module_sim.vhd" \
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2>&1 | tee -a vhdlan.log
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vlogan -work xil_defaultlib $vlogan_opts +v2k \
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glbl.v \
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2>&1 | tee -a vlogan.log
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}
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# RUN_STEP: <elaborate>
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elaborate()
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{
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vcs $vcs_elab_opts xil_defaultlib.axi_uartlite_module_sim xil_defaultlib.glbl -o axi_uartlite_module_sim_simv
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}
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# RUN_STEP: <simulate>
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simulate()
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{
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./axi_uartlite_module_sim_simv $vcs_sim_opts -do simulate.do
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}
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# STEP: setup
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setup()
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{
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case $1 in
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"-lib_map_path" )
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if [[ ($2 == "") ]]; then
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echo -e "ERROR: Simulation library directory path not specified (type \"./axi_uartlite_module_sim.sh -help\" for more information)\n"
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exit 1
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fi
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create_lib_mappings $2
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;;
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"-reset_run" )
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reset_run
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echo -e "INFO: Simulation run files deleted.\n"
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exit 0
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;;
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"-noclean_files" )
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# do not remove previous data
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;;
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* )
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create_lib_mappings $2
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esac
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create_lib_dir
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# Add any setup/initialization commands here:-
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# <user specific commands>
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}
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# Define design library mappings
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create_lib_mappings()
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{
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file="synopsys_sim.setup"
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if [[ -e $file ]]; then
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if [[ ($1 == "") ]]; then
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return
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else
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rm -rf $file
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fi
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fi
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touch $file
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if [[ ($1 != "") ]]; then
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lib_map_path="$1"
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else
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lib_map_path="/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/vcs"
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fi
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for (( i=0; i<${#design_libs[*]}; i++ )); do
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lib="${design_libs[i]}"
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mapping="$lib:$sim_lib_dir/$lib"
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echo $mapping >> $file
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done
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if [[ ($lib_map_path != "") ]]; then
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incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
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echo $incl_ref >> $file
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fi
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}
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# Create design library directory paths
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create_lib_dir()
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{
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if [[ -e $sim_lib_dir ]]; then
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rm -rf $sim_lib_dir
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fi
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for (( i=0; i<${#design_libs[*]}; i++ )); do
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lib="${design_libs[i]}"
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lib_dir="$sim_lib_dir/$lib"
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if [[ ! -e $lib_dir ]]; then
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mkdir -p $lib_dir
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fi
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done
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}
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# Delete generated data from the previous run
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reset_run()
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{
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files_to_remove=(ucli.key axi_uartlite_module_sim_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc axi_uartlite_module_sim_simv.daidir)
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for (( i=0; i<${#files_to_remove[*]}; i++ )); do
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file="${files_to_remove[i]}"
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if [[ -e $file ]]; then
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rm -rf $file
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fi
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done
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create_lib_dir
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}
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# Check command line arguments
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check_args()
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{
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if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
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echo -e "ERROR: Unknown option specified '$2' (type \"./axi_uartlite_module_sim.sh -help\" for more information)\n"
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exit 1
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fi
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if [[ ($2 == "-help" || $2 == "-h") ]]; then
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usage
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fi
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}
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# Script usage
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usage()
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{
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msg="Usage: axi_uartlite_module_sim.sh [-help]\n\
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Usage: axi_uartlite_module_sim.sh [-lib_map_path]\n\
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Usage: axi_uartlite_module_sim.sh [-reset_run]\n\
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Usage: axi_uartlite_module_sim.sh [-noclean_files]\n\n\
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[-help] -- Print help information for this script\n\n\
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[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
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using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
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[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
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from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
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-noclean_files switch.\n\n\
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[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
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echo -e $msg
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exit 1
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}
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# Launch script
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run $1 $2
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