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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [axi_uartlite_module_synth_1/] [axi_uartlite_module.vds] - Blame information for rev 2

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1 2 vv_gulyaev 
#-----------------------------------------------------------
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# Vivado v2017.4 (64-bit)
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# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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# Start of session at: Thu Jul 30 13:01:29 2020
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# Process ID: 6017
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# Current directory: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1
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# Command line: vivado -log axi_uartlite_module.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source axi_uartlite_module.tcl
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# Log file: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/axi_uartlite_module.vds
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# Journal file: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/vivado.jou
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#-----------------------------------------------------------
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source axi_uartlite_module.tcl -notrace
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Command: synth_design -top axi_uartlite_module -part xc7k325tffg900-2 -mode out_of_context
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 6067
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1279.148 ; gain = 87.000 ; free physical = 1593 ; free virtual = 7772
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---------------------------------------------------------------------------------
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INFO: [Synth 8-638] synthesizing module 'axi_uartlite_module' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:86]
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        Parameter C_FAMILY bound to: kintex7 - type: string
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        Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
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        Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
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        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_BAUDRATE bound to: 38400 - type: integer
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        Parameter C_DATA_BITS bound to: 8 - type: integer
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        Parameter C_USE_PARITY bound to: 0 - type: integer
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        Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-3491] module 'axi_uartlite' declared at '/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2090' bound to instance 'U0' of component 'axi_uartlite' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:161]
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INFO: [Synth 8-638] synthesizing module 'axi_uartlite' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2160]
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        Parameter C_FAMILY bound to: kintex7 - type: string
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        Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
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        Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
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        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_BAUDRATE bound to: 38400 - type: integer
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        Parameter C_DATA_BITS bound to: 8 - type: integer
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        Parameter C_USE_PARITY bound to: 0 - type: integer
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        Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2109]
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INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2110]
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INFO: [Synth 8-638] synthesizing module 'uartlite_core' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1615]
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        Parameter C_FAMILY bound to: kintex7 - type: string
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        Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
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        Parameter C_BAUDRATE bound to: 38400 - type: integer
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        Parameter C_DATA_BITS bound to: 8 - type: integer
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        Parameter C_USE_PARITY bound to: 0 - type: integer
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        Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-638] synthesizing module 'baudrate' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1418]
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        Parameter C_RATIO bound to: 163 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'baudrate' (1#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1418]
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INFO: [Synth 8-3919] null assignment ignored [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1881]
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INFO: [Synth 8-638] synthesizing module 'uartlite_rx' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:909]
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        Parameter C_FAMILY bound to: kintex7 - type: string
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        Parameter C_DATA_BITS bound to: 8 - type: integer
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        Parameter C_USE_PARITY bound to: 0 - type: integer
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        Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:106]
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        Parameter C_CDC_TYPE bound to: 1 - type: integer
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        Parameter C_RESET_STATE bound to: 0 - type: integer
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        Parameter C_SINGLE_BIT bound to: 1 - type: integer
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        Parameter C_FLOP_INPUT bound to: 0 - type: integer
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        Parameter C_VECTOR_WIDTH bound to: 32 - type: integer
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        Parameter C_MTBF_STAGES bound to: 4 - type: integer
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        Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:514]
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        Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:545]
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        Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:554]
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        Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:564]
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        Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:574]
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        Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:584]
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INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (2#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:106]
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INFO: [Synth 8-638] synthesizing module 'dynshreg_i_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
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        Parameter C_DEPTH bound to: 16 - type: integer
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        Parameter C_DWIDTH bound to: 1 - type: integer
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        Parameter C_INIT_VALUE bound to: 1'b0
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        Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-256] done synthesizing module 'dynshreg_i_f' (3#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
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INFO: [Synth 8-638] synthesizing module 'srl_fifo_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
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        Parameter C_DWIDTH bound to: 8 - type: integer
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        Parameter C_DEPTH bound to: 16 - type: integer
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        Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
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        Parameter C_DWIDTH bound to: 8 - type: integer
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        Parameter C_DEPTH bound to: 16 - type: integer
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        Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
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        Parameter C_SIZE bound to: 5 - type: integer
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        Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (4#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
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INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
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        Parameter C_DEPTH bound to: 16 - type: integer
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        Parameter C_DWIDTH bound to: 8 - type: integer
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        Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (5#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
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INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (6#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
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INFO: [Synth 8-256] done synthesizing module 'srl_fifo_f' (7#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
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INFO: [Synth 8-256] done synthesizing module 'uartlite_rx' (8#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:909]
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INFO: [Synth 8-638] synthesizing module 'uartlite_tx' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
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        Parameter C_FAMILY bound to: kintex7 - type: string
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        Parameter C_DATA_BITS bound to: 8 - type: integer
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        Parameter C_USE_PARITY bound to: 0 - type: integer
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        Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-638] synthesizing module 'dynshreg_i_f__parameterized0' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
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        Parameter C_DEPTH bound to: 16 - type: integer
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        Parameter C_DWIDTH bound to: 1 - type: integer
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        Parameter C_INIT_VALUE bound to: 16'b1000000000000000
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        Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-256] done synthesizing module 'dynshreg_i_f__parameterized0' (8#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
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INFO: [Synth 8-256] done synthesizing module 'uartlite_tx' (9#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
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INFO: [Synth 8-256] done synthesizing module 'uartlite_core' (10#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1615]
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INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
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        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
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        Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
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        Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000000001111
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        Parameter C_USE_WSTRB bound to: 0 - type: integer
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        Parameter C_DPHASE_TIMEOUT bound to: 0 - type: integer
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        Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
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        Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
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        Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
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        Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
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        Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
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        Parameter C_IPIF_ABUS_WIDTH bound to: 4 - type: integer
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        Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
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        Parameter C_S_AXI_MIN_SIZE bound to: 15 - type: integer
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        Parameter C_USE_WSTRB bound to: 0 - type: integer
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        Parameter C_DPHASE_TIMEOUT bound to: 0 - type: integer
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        Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
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        Parameter C_BUS_AWIDTH bound to: 4 - type: integer
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        Parameter C_S_AXI_MIN_SIZE bound to: 15 - type: integer
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        Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
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        Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
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        Parameter C_FAMILY bound to: nofamily - type: string
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INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
143 
        Parameter C_AB bound to: 2 - type: integer
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        Parameter C_AW bound to: 2 - type: integer
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        Parameter C_BAR bound to: 2'b00
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        Parameter C_FAMILY bound to: nofamily - type: string
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INFO: [Synth 8-256] done synthesizing module 'pselect_f' (11#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
148 
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
149 
        Parameter C_AB bound to: 2 - type: integer
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        Parameter C_AW bound to: 2 - type: integer
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        Parameter C_BAR bound to: 2'b01
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        Parameter C_FAMILY bound to: nofamily - type: string
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INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (11#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
154 
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
155 
        Parameter C_AB bound to: 2 - type: integer
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        Parameter C_AW bound to: 2 - type: integer
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        Parameter C_BAR bound to: 2'b10
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        Parameter C_FAMILY bound to: nofamily - type: string
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INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (11#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
160 
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
161 
        Parameter C_AB bound to: 2 - type: integer
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        Parameter C_AW bound to: 2 - type: integer
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        Parameter C_BAR bound to: 2'b11
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        Parameter C_FAMILY bound to: nofamily - type: string
165 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (11#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
166 
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (12#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
167 
INFO: [Synth 8-226] default block is never used [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
168 
WARNING: [Synth 8-6014] Unused sequential element is_read_reg was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2447]
169 
WARNING: [Synth 8-6014] Unused sequential element is_write_reg was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2448]
170 
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (13#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
171 
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (14#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
172 
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite' (15#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2160]
173 
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite_module' (16#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:86]
174 
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[2]
175 
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[3]
176 
WARNING: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW
177 
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3]
178 
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2]
179 
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1]
180 
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0]
181 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk
182 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn
183 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[31]
184 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[30]
185 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[29]
186 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[28]
187 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[27]
188 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[26]
189 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[25]
190 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[24]
191 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[23]
192 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[22]
193 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[21]
194 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[20]
195 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[19]
196 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[18]
197 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[17]
198 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[16]
199 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[15]
200 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[14]
201 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[13]
202 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[12]
203 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[11]
204 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[10]
205 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[9]
206 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[8]
207 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[7]
208 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[6]
209 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[5]
210 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[4]
211 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[3]
212 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[2]
213 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[1]
214 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[0]
215 
WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn
216 
WARNING: [Synth 8-3331] design uartlite_core has unconnected port bus2ip_cs
217 
---------------------------------------------------------------------------------
218 
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1321.680 ; gain = 129.531 ; free physical = 1601 ; free virtual = 7782
219 
---------------------------------------------------------------------------------
220 
 
221 
Report Check Netlist:
222 
+------+------------------+-------+---------+-------+------------------+
223 
|      |Item              |Errors |Warnings |Status |Description       |
224 
+------+------------------+-------+---------+-------+------------------+
225 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
226 
+------+------------------+-------+---------+-------+------------------+
227 
---------------------------------------------------------------------------------
228 
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1321.680 ; gain = 129.531 ; free physical = 1591 ; free virtual = 7773
229 
---------------------------------------------------------------------------------
230 
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
231 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
232 
INFO: [Device 21-403] Loading part xc7k325tffg900-2
233 
INFO: [Project 1-570] Preparing netlist for logic optimization
234 
 
235 
Processing XDC Constraints
236 
Initializing timing engine
237 
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc] for cell 'U0'
238 
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc] for cell 'U0'
239 
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'U0'
240 
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'U0'
241 
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'U0'
242 
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'U0'
243 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc]
244 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc]
245 
Completed Processing XDC Constraints
246 
 
247 
INFO: [Project 1-111] Unisim Transformation Summary:
248 
  A total of 6 instances were transformed.
249 
  FDR => FDRE: 6 instances
250 
 
251 
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1697.844 ; gain = 0.000 ; free physical = 981 ; free virtual = 7202
252 
---------------------------------------------------------------------------------
253 
Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1140 ; free virtual = 7362
254 
---------------------------------------------------------------------------------
255 
---------------------------------------------------------------------------------
256 
Start Loading Part and Timing Information
257 
---------------------------------------------------------------------------------
258 
Loading part: xc7k325tffg900-2
259 
---------------------------------------------------------------------------------
260 
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1140 ; free virtual = 7362
261 
---------------------------------------------------------------------------------
262 
---------------------------------------------------------------------------------
263 
Start Applying 'set_property' XDC Constraints
264 
---------------------------------------------------------------------------------
265 
Applied set_property DONT_TOUCH = true for U0. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc, line 9).
266 
---------------------------------------------------------------------------------
267 
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1144 ; free virtual = 7366
268 
---------------------------------------------------------------------------------
269 
INFO: [Synth 8-5546] ROM "EN_16x_Baud" won't be mapped to RAM because it is too sparse
270 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
271 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
272 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
273 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
274 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
275 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
276 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
277 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
278 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
279 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
280 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
281 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
282 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
283 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
284 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
285 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
286 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
287 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
288 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
289 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
290 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
291 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
292 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
293 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
294 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
295 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
296 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
297 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
298 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
299 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
300 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
301 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
302 
INFO: [Synth 8-5546] ROM "fifo_full_p1" won't be mapped to RAM because it is too sparse
303 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
304 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
305 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
306 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
307 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
308 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
309 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
310 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
311 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
312 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
313 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
314 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
315 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
316 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
317 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
318 
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
319 
INFO: [Synth 8-5544] ROM "mux_sel_is_zero" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
320 
INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
321 
INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
322 
INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
323 
INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
324 
---------------------------------------------------------------------------------
325 
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:25 ; elapsed = 00:00:37 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1127 ; free virtual = 7356
326 
---------------------------------------------------------------------------------
327 
 
328 
Report RTL Partitions:
329 
+-+--------------+------------+----------+
330 
| |RTL Partition |Replication |Instances |
331 
+-+--------------+------------+----------+
332 
+-+--------------+------------+----------+
333 
---------------------------------------------------------------------------------
334 
Start RTL Component Statistics
335 
---------------------------------------------------------------------------------
336 
Detailed RTL Component Info :
337 
+---Adders :
338 
           2 Input      8 Bit       Adders := 1
339 
           3 Input      5 Bit       Adders := 2
340 
           2 Input      3 Bit       Adders := 1
341 
+---Registers :
342 
                       32 Bit    Registers := 1
343 
                        8 Bit    Registers := 1
344 
                        5 Bit    Registers := 2
345 
                        4 Bit    Registers := 1
346 
                        3 Bit    Registers := 1
347 
                        2 Bit    Registers := 3
348 
                        1 Bit    Registers := 46
349 
+---Muxes :
350 
           2 Input      8 Bit        Muxes := 3
351 
           2 Input      4 Bit        Muxes := 1
352 
           2 Input      3 Bit        Muxes := 1
353 
           7 Input      2 Bit        Muxes := 1
354 
           2 Input      2 Bit        Muxes := 2
355 
           2 Input      1 Bit        Muxes := 43
356 
---------------------------------------------------------------------------------
357 
Finished RTL Component Statistics
358 
---------------------------------------------------------------------------------
359 
---------------------------------------------------------------------------------
360 
Start RTL Hierarchical Component Statistics
361 
---------------------------------------------------------------------------------
362 
Hierarchical RTL Component report
363 
Module baudrate
364 
Detailed RTL Component Info :
365 
+---Adders :
366 
           2 Input      8 Bit       Adders := 1
367 
+---Registers :
368 
                        8 Bit    Registers := 1
369 
                        1 Bit    Registers := 1
370 
+---Muxes :
371 
           2 Input      8 Bit        Muxes := 1
372 
           2 Input      1 Bit        Muxes := 1
373 
Module cntr_incr_decr_addn_f
374 
Detailed RTL Component Info :
375 
+---Adders :
376 
           3 Input      5 Bit       Adders := 1
377 
+---Registers :
378 
                        5 Bit    Registers := 1
379 
Module srl_fifo_rbu_f
380 
Detailed RTL Component Info :
381 
+---Registers :
382 
                        1 Bit    Registers := 3
383 
+---Muxes :
384 
           2 Input      1 Bit        Muxes := 3
385 
Module uartlite_rx
386 
Detailed RTL Component Info :
387 
+---Registers :
388 
                        1 Bit    Registers := 15
389 
+---Muxes :
390 
           2 Input      1 Bit        Muxes := 12
391 
Module uartlite_tx
392 
Detailed RTL Component Info :
393 
+---Adders :
394 
           2 Input      3 Bit       Adders := 1
395 
+---Registers :
396 
                        3 Bit    Registers := 1
397 
                        1 Bit    Registers := 6
398 
+---Muxes :
399 
           2 Input      3 Bit        Muxes := 1
400 
           2 Input      1 Bit        Muxes := 10
401 
Module uartlite_core
402 
Detailed RTL Component Info :
403 
+---Registers :
404 
                        1 Bit    Registers := 7
405 
+---Muxes :
406 
           2 Input      8 Bit        Muxes := 2
407 
           2 Input      1 Bit        Muxes := 2
408 
Module pselect_f
409 
Detailed RTL Component Info :
410 
+---Muxes :
411 
           2 Input      1 Bit        Muxes := 1
412 
Module pselect_f__parameterized0
413 
Detailed RTL Component Info :
414 
+---Muxes :
415 
           2 Input      1 Bit        Muxes := 1
416 
Module pselect_f__parameterized1
417 
Detailed RTL Component Info :
418 
+---Muxes :
419 
           2 Input      1 Bit        Muxes := 1
420 
Module pselect_f__parameterized2
421 
Detailed RTL Component Info :
422 
+---Muxes :
423 
           2 Input      1 Bit        Muxes := 1
424 
Module address_decoder
425 
Detailed RTL Component Info :
426 
+---Registers :
427 
                        1 Bit    Registers := 6
428 
Module slave_attachment
429 
Detailed RTL Component Info :
430 
+---Registers :
431 
                       32 Bit    Registers := 1
432 
                        4 Bit    Registers := 1
433 
                        2 Bit    Registers := 3
434 
                        1 Bit    Registers := 5
435 
+---Muxes :
436 
           2 Input      4 Bit        Muxes := 1
437 
           7 Input      2 Bit        Muxes := 1
438 
           2 Input      2 Bit        Muxes := 2
439 
           2 Input      1 Bit        Muxes := 8
440 
---------------------------------------------------------------------------------
441 
Finished RTL Hierarchical Component Statistics
442 
---------------------------------------------------------------------------------
443 
---------------------------------------------------------------------------------
444 
Start Part Resource Summary
445 
---------------------------------------------------------------------------------
446 
Part Resources:
447 
DSPs: 840 (col length:140)
448 
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
449 
---------------------------------------------------------------------------------
450 
Finished Part Resource Summary
451 
---------------------------------------------------------------------------------
452 
---------------------------------------------------------------------------------
453 
Start Cross Boundary and Area Optimization
454 
---------------------------------------------------------------------------------
455 
WARNING: [Synth 8-6014] Unused sequential element AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN[0].cs_out_i_reg was removed.  [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2004]
456 
INFO: [Synth 8-5546] ROM "UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud" won't be mapped to RAM because it is too sparse
457 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[31]
458 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[30]
459 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[29]
460 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[28]
461 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[27]
462 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[26]
463 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[25]
464 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[24]
465 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[23]
466 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[22]
467 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[21]
468 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[20]
469 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[19]
470 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[18]
471 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[17]
472 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[16]
473 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[15]
474 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[14]
475 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[13]
476 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[12]
477 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[11]
478 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[10]
479 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[9]
480 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[8]
481 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[3]
482 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[2]
483 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[1]
484 
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[0]
485 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_uartlite.
486 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_uartlite.
487 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/underflow_i_reg) is unused and will be removed from module axi_uartlite.
488 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/overflow_i_reg) is unused and will be removed from module axi_uartlite.
489 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/underflow_i_reg) is unused and will be removed from module axi_uartlite.
490 
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/overflow_i_reg) is unused and will be removed from module axi_uartlite.
491 
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[1]) is unused and will be removed from module axi_uartlite.
492 
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[0]) is unused and will be removed from module axi_uartlite.
493 
---------------------------------------------------------------------------------
494 
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:38 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1107 ; free virtual = 7338
495 
---------------------------------------------------------------------------------
496 
 
497 
Report RTL Partitions:
498 
+-+--------------+------------+----------+
499 
| |RTL Partition |Replication |Instances |
500 
+-+--------------+------------+----------+
501 
+-+--------------+------------+----------+
502 
---------------------------------------------------------------------------------
503 
Start Applying XDC Timing Constraints
504 
---------------------------------------------------------------------------------
505 
---------------------------------------------------------------------------------
506 
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 893 ; free virtual = 7124
507 
---------------------------------------------------------------------------------
508 
---------------------------------------------------------------------------------
509 
Start Timing Optimization
510 
---------------------------------------------------------------------------------
511 
---------------------------------------------------------------------------------
512 
Finished Timing Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 858 ; free virtual = 7089
513 
---------------------------------------------------------------------------------
514 
 
515 
Report RTL Partitions:
516 
+-+--------------+------------+----------+
517 
| |RTL Partition |Replication |Instances |
518 
+-+--------------+------------+----------+
519 
+-+--------------+------------+----------+
520 
---------------------------------------------------------------------------------
521 
Start Technology Mapping
522 
---------------------------------------------------------------------------------
523 
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0]) is unused and will be removed from module axi_uartlite.
524 
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0]) is unused and will be removed from module axi_uartlite.
525 
---------------------------------------------------------------------------------
526 
Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 850 ; free virtual = 7081
527 
---------------------------------------------------------------------------------
528 
 
529 
Report RTL Partitions:
530 
+-+--------------+------------+----------+
531 
| |RTL Partition |Replication |Instances |
532 
+-+--------------+------------+----------+
533 
+-+--------------+------------+----------+
534 
---------------------------------------------------------------------------------
535 
Start IO Insertion
536 
---------------------------------------------------------------------------------
537 
---------------------------------------------------------------------------------
538 
Start Flattening Before IO Insertion
539 
---------------------------------------------------------------------------------
540 
---------------------------------------------------------------------------------
541 
Finished Flattening Before IO Insertion
542 
---------------------------------------------------------------------------------
543 
---------------------------------------------------------------------------------
544 
Start Final Netlist Cleanup
545 
---------------------------------------------------------------------------------
546 
---------------------------------------------------------------------------------
547 
Finished Final Netlist Cleanup
548 
---------------------------------------------------------------------------------
549 
---------------------------------------------------------------------------------
550 
Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 879 ; free virtual = 7111
551 
---------------------------------------------------------------------------------
552 
 
553 
Report Check Netlist:
554 
+------+------------------+-------+---------+-------+------------------+
555 
|      |Item              |Errors |Warnings |Status |Description       |
556 
+------+------------------+-------+---------+-------+------------------+
557 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
558 
+------+------------------+-------+---------+-------+------------------+
559 
---------------------------------------------------------------------------------
560 
Start Renaming Generated Instances
561 
---------------------------------------------------------------------------------
562 
---------------------------------------------------------------------------------
563 
Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 879 ; free virtual = 7111
564 
---------------------------------------------------------------------------------
565 
 
566 
Report RTL Partitions:
567 
+-+--------------+------------+----------+
568 
| |RTL Partition |Replication |Instances |
569 
+-+--------------+------------+----------+
570 
+-+--------------+------------+----------+
571 
---------------------------------------------------------------------------------
572 
Start Rebuilding User Hierarchy
573 
---------------------------------------------------------------------------------
574 
---------------------------------------------------------------------------------
575 
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 877 ; free virtual = 7109
576 
---------------------------------------------------------------------------------
577 
---------------------------------------------------------------------------------
578 
Start Renaming Generated Ports
579 
---------------------------------------------------------------------------------
580 
---------------------------------------------------------------------------------
581 
Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 877 ; free virtual = 7109
582 
---------------------------------------------------------------------------------
583 
---------------------------------------------------------------------------------
584 
Start Handling Custom Attributes
585 
---------------------------------------------------------------------------------
586 
---------------------------------------------------------------------------------
587 
Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 876 ; free virtual = 7108
588 
---------------------------------------------------------------------------------
589 
---------------------------------------------------------------------------------
590 
Start Renaming Generated Nets
591 
---------------------------------------------------------------------------------
592 
---------------------------------------------------------------------------------
593 
Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 876 ; free virtual = 7107
594 
---------------------------------------------------------------------------------
595 
---------------------------------------------------------------------------------
596 
Start ROM, RAM, DSP and Shift Register Reporting
597 
---------------------------------------------------------------------------------
598 
 
599 
Static Shift Register Report:
600 
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
601 
|Module Name  | RTL Name                                                                         | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
602 
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
603 
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[15][0]            | 16     | 1     | NO           | NO                 | YES               | 1      | 0       |
604 
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[15][0] | 16     | 1     | NO           | NO                 | YES               | 1      | 0       |
605 
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
606 
 
607 
 
608 
Dynamic Shift Register Report:
609 
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
610 
|Module Name | RTL Name                  | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
611 
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
612 
|dsrl        | INFERRED_GEN.data_reg[15] | 16     | 1          | 1      | 0       | 0      | 0      | 0      |
613 
|dsrl__1     | INFERRED_GEN.data_reg[15] | 16     | 8          | 8      | 0       | 0      | 0      | 0      |
614 
|dsrl__2     | INFERRED_GEN.data_reg[15] | 16     | 1          | 1      | 0       | 0      | 0      | 0      |
615 
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
616 
 
617 
---------------------------------------------------------------------------------
618 
Finished ROM, RAM, DSP and Shift Register Reporting
619 
---------------------------------------------------------------------------------
620 
---------------------------------------------------------------------------------
621 
Start Writing Synthesis Report
622 
---------------------------------------------------------------------------------
623 
 
624 
Report BlackBoxes:
625 
+-+--------------+----------+
626 
| |BlackBox name |Instances |
627 
+-+--------------+----------+
628 
+-+--------------+----------+
629 
 
630 
Report Cell Usage:
631 
+------+-------+------+
632 
|      |Cell   |Count |
633 
+------+-------+------+
634 
|1     |LUT1   |     1|
635 
|2     |LUT2   |    14|
636 
|3     |LUT3   |    19|
637 
|4     |LUT4   |    17|
638 
|5     |LUT5   |    44|
639 
|6     |LUT6   |    17|
640 
|7     |SRL16E |    18|
641 
|8     |FDR    |     4|
642 
|9     |FDRE   |    72|
643 
|10    |FDSE   |    16|
644 
+------+-------+------+
645 
 
646 
Report Instance Areas:
647 
+------+--------------------------------------------------------------------------+-----------------------------+------+
648 
|      |Instance                                                                  |Module                       |Cells |
649 
+------+--------------------------------------------------------------------------+-----------------------------+------+
650 
|1     |top                                                                       |                             |   222|
651 
|2     |  U0                                                                      |axi_uartlite                 |   222|
652 
|3     |    AXI_LITE_IPIF_I                                                       |axi_lite_ipif                |    65|
653 
|4     |      I_SLAVE_ATTACHMENT                                                  |slave_attachment             |    65|
654 
|5     |        I_DECODER                                                         |address_decoder              |    37|
655 
|6     |          \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I  |pselect_f                    |     1|
656 
|7     |          \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I  |pselect_f__parameterized1    |     1|
657 
|8     |    UARTLITE_CORE_I                                                       |uartlite_core                |   157|
658 
|9     |      BAUD_RATE_I                                                         |baudrate                     |    22|
659 
|10    |      UARTLITE_RX_I                                                       |uartlite_rx                  |    77|
660 
|11    |        DELAY_16_I                                                        |dynshreg_i_f                 |    17|
661 
|12    |        INPUT_DOUBLE_REGS3                                                |cdc_sync                     |     5|
662 
|13    |        SRL_FIFO_I                                                        |srl_fifo_f_0                 |    28|
663 
|14    |          I_SRL_FIFO_RBU_F                                                |srl_fifo_rbu_f_1             |    28|
664 
|15    |            CNTR_INCR_DECR_ADDN_F_I                                       |cntr_incr_decr_addn_f_2      |    17|
665 
|16    |            DYNSHREG_F_I                                                  |dynshreg_f_3                 |     9|
666 
|17    |      UARTLITE_TX_I                                                       |uartlite_tx                  |    49|
667 
|18    |        MID_START_BIT_SRL16_I                                             |dynshreg_i_f__parameterized0 |     3|
668 
|19    |        SRL_FIFO_I                                                        |srl_fifo_f                   |    31|
669 
|20    |          I_SRL_FIFO_RBU_F                                                |srl_fifo_rbu_f               |    31|
670 
|21    |            CNTR_INCR_DECR_ADDN_F_I                                       |cntr_incr_decr_addn_f        |    17|
671 
|22    |            DYNSHREG_F_I                                                  |dynshreg_f                   |    13|
672 
+------+--------------------------------------------------------------------------+-----------------------------+------+
673 
---------------------------------------------------------------------------------
674 
Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 875 ; free virtual = 7107
675 
---------------------------------------------------------------------------------
676 
Synthesis finished with 0 errors, 0 critical warnings and 77 warnings.
677 
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1697.844 ; gain = 129.531 ; free physical = 933 ; free virtual = 7165
678 
Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.852 ; gain = 505.695 ; free physical = 933 ; free virtual = 7165
679 
INFO: [Project 1-571] Translating synthesized netlist
680 
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
681 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
682 
INFO: [Project 1-570] Preparing netlist for logic optimization
683 
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
684 
INFO: [Project 1-111] Unisim Transformation Summary:
685 
  A total of 4 instances were transformed.
686 
  FDR => FDRE: 4 instances
687 
 
688 
INFO: [Common 17-83] Releasing license: Synthesis
689 
82 Infos, 122 Warnings, 0 Critical Warnings and 0 Errors encountered.
690 
synth_design completed successfully
691 
synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:47 . Memory (MB): peak = 1697.852 ; gain = 532.805 ; free physical = 936 ; free virtual = 7171
692 
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/axi_uartlite_module.dcp' has been generated.
693 
INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xci
694 
INFO: [Coretcl 2-1174] Renamed 21 cell refs.
695 
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/axi_uartlite_module.dcp' has been generated.
696 
INFO: [runtcl-4] Executing : report_utilization -file axi_uartlite_module_utilization_synth.rpt -pb axi_uartlite_module_utilization_synth.pb
697 
report_utilization: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1721.855 ; gain = 0.000 ; free physical = 1500 ; free virtual = 7737
698 
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:02:26 2020...

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