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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [axi_uartlite_module_synth_1/] [axi_uartlite_module_utilization_synth.rpt] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev 
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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---------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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| Date         : Thu Jul 30 13:02:26 2020
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| Host         : orme22 running 64-bit Ubuntu 18.04.4 LTS
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| Command      : report_utilization -file axi_uartlite_module_utilization_synth.rpt -pb axi_uartlite_module_utilization_synth.pb
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| Design       : axi_uartlite_module
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| Device       : 7k325tffg900-2
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| Design State : Synthesized
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---------------------------------------------------------------------------------------------------------------------------------
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+----------------------------+------+-------+-----------+-------+
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|          Site Type         | Used | Fixed | Available | Util% |
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+----------------------------+------+-------+-----------+-------+
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| Slice LUTs*                |  108 |     0 |    203800 |  0.05 |
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|   LUT as Logic             |   90 |     0 |    203800 |  0.04 |
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|   LUT as Memory            |   18 |     0 |     64000 |  0.03 |
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|     LUT as Distributed RAM |    0 |     0 |           |       |
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|     LUT as Shift Register  |   18 |     0 |           |       |
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| Slice Registers            |   92 |     0 |    407600 |  0.02 |
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|   Register as Flip Flop    |   92 |     0 |    407600 |  0.02 |
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|   Register as Latch        |    0 |     0 |    407600 |  0.00 |
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| F7 Muxes                   |    0 |     0 |    101900 |  0.00 |
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| F8 Muxes                   |    0 |     0 |     50950 |  0.00 |
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+----------------------------+------+-------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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46 
 
47 
1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0     |            _ |           - |            - |
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| 0     |            _ |           - |          Set |
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| 0     |            _ |           - |        Reset |
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| 0     |            _ |         Set |            - |
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| 0     |            _ |       Reset |            - |
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| 0     |          Yes |           - |            - |
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| 0     |          Yes |           - |          Set |
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| 0     |          Yes |           - |        Reset |
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| 16    |          Yes |         Set |            - |
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| 76    |          Yes |       Reset |            - |
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+-------+--------------+-------------+--------------+
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65 
 
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2. Memory
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---------
68 
 
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+----------------+------+-------+-----------+-------+
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|    Site Type   | Used | Fixed | Available | Util% |
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+----------------+------+-------+-----------+-------+
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| Block RAM Tile |    0 |     0 |       445 |  0.00 |
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|   RAMB36/FIFO* |    0 |     0 |       445 |  0.00 |
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|   RAMB18       |    0 |     0 |       890 |  0.00 |
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+----------------+------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
81 
 
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+-----------+------+-------+-----------+-------+
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| Site Type | Used | Fixed | Available | Util% |
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+-----------+------+-------+-----------+-------+
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| DSPs      |    0 |     0 |       840 |  0.00 |
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+-----------+------+-------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+-----------+-------+
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|          Site Type          | Used | Fixed | Available | Util% |
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+-----------------------------+------+-------+-----------+-------+
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| Bonded IOB                  |    0 |     0 |       500 |  0.00 |
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| Bonded IPADs                |    0 |     0 |        50 |  0.00 |
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| Bonded OPADs                |    0 |     0 |        32 |  0.00 |
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| PHY_CONTROL                 |    0 |     0 |        10 |  0.00 |
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| PHASER_REF                  |    0 |     0 |        10 |  0.00 |
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| OUT_FIFO                    |    0 |     0 |        40 |  0.00 |
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| IN_FIFO                     |    0 |     0 |        40 |  0.00 |
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| IDELAYCTRL                  |    0 |     0 |        10 |  0.00 |
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| IBUFDS                      |    0 |     0 |       480 |  0.00 |
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| GTXE2_COMMON                |    0 |     0 |         4 |  0.00 |
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| GTXE2_CHANNEL               |    0 |     0 |        16 |  0.00 |
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| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        40 |  0.00 |
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| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        40 |  0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       500 |  0.00 |
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| ODELAYE2/ODELAYE2_FINEDELAY |    0 |     0 |       150 |  0.00 |
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| IBUFDS_GTE2                 |    0 |     0 |         8 |  0.00 |
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| ILOGIC                      |    0 |     0 |       500 |  0.00 |
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| OLOGIC                      |    0 |     0 |       500 |  0.00 |
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+-----------------------------+------+-------+-----------+-------+
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5. Clocking
117 
-----------
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+------------+------+-------+-----------+-------+
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|  Site Type | Used | Fixed | Available | Util% |
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+------------+------+-------+-----------+-------+
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| BUFGCTRL   |    0 |     0 |        32 |  0.00 |
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| BUFIO      |    0 |     0 |        40 |  0.00 |
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| MMCME2_ADV |    0 |     0 |        10 |  0.00 |
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| PLLE2_ADV  |    0 |     0 |        10 |  0.00 |
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| BUFMRCE    |    0 |     0 |        20 |  0.00 |
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| BUFHCE     |    0 |     0 |       168 |  0.00 |
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| BUFR       |    0 |     0 |        40 |  0.00 |
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+------------+------+-------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+-----------+-------+
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|  Site Type  | Used | Fixed | Available | Util% |
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+-------------+------+-------+-----------+-------+
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| BSCANE2     |    0 |     0 |         4 |  0.00 |
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| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
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| DNA_PORT    |    0 |     0 |         1 |  0.00 |
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| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
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| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
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| ICAPE2      |    0 |     0 |         2 |  0.00 |
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| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
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| STARTUPE2   |    0 |     0 |         1 |  0.00 |
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| XADC        |    0 |     0 |         1 |  0.00 |
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+-------------+------+-------+-----------+-------+
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7. Primitives
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-------------
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+----------+------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+------+---------------------+
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| FDRE     |   76 |        Flop & Latch |
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| LUT5     |   44 |                 LUT |
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| LUT3     |   19 |                 LUT |
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| SRL16E   |   18 |  Distributed Memory |
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| LUT6     |   17 |                 LUT |
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| LUT4     |   17 |                 LUT |
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| FDSE     |   16 |        Flop & Latch |
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| LUT2     |   14 |                 LUT |
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| LUT1     |    1 |                 LUT |
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+----------+------+---------------------+
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8. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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