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# This file is automatically generated.
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# It contains project source information necessary for synthesis and implementation.
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# IP: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xci
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# IP: The module: 'axi_uartlite_module' is the root of the design. Do not add the DONT_TOUCH constraint.
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# XDC: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc
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# XDC: The top module name and the constraint reference have the same name: 'axi_uartlite_module'. Do not add the DONT_TOUCH constraint.
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set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
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# XDC: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc
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# XDC: The top module name and the constraint reference have the same name: 'axi_uartlite_module'. Do not add the DONT_TOUCH constraint.
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#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
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# XDC: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc
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# XDC: The top module name and the constraint reference have the same name: 'axi_uartlite_module'. Do not add the DONT_TOUCH constraint.
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#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
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# IP: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xci
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# IP: The module: 'axi_uartlite_module' is the root of the design. Do not add the DONT_TOUCH constraint.
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# XDC: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc
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# XDC: The top module name and the constraint reference have the same name: 'axi_uartlite_module'. Do not add the DONT_TOUCH constraint.
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#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
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# XDC: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc
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# XDC: The top module name and the constraint reference have the same name: 'axi_uartlite_module'. Do not add the DONT_TOUCH constraint.
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#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
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# XDC: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc
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# XDC: The top module name and the constraint reference have the same name: 'axi_uartlite_module'. Do not add the DONT_TOUCH constraint.
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#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
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