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vv_gulyaev |
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*** Running vivado
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with args -log axi_uartlite_module.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source axi_uartlite_module.tcl
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****** Vivado v2017.4 (64-bit)
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**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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source axi_uartlite_module.tcl -notrace
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INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP axi_uartlite_module, cache-ID = 077a94985ac208e4.
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INFO: [Common 17-206] Exiting Vivado at Wed Jul 29 15:22:05 2020...
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*** Running vivado
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with args -log axi_uartlite_module.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source axi_uartlite_module.tcl
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****** Vivado v2017.4 (64-bit)
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**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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source axi_uartlite_module.tcl -notrace
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Command: synth_design -top axi_uartlite_module -part xc7k325tffg900-2 -mode out_of_context
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 6067
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1279.148 ; gain = 87.000 ; free physical = 1593 ; free virtual = 7772
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---------------------------------------------------------------------------------
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INFO: [Synth 8-638] synthesizing module 'axi_uartlite_module' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:86]
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Parameter C_FAMILY bound to: kintex7 - type: string
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Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
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Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
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Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
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Parameter C_BAUDRATE bound to: 38400 - type: integer
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Parameter C_DATA_BITS bound to: 8 - type: integer
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Parameter C_USE_PARITY bound to: 0 - type: integer
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Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-3491] module 'axi_uartlite' declared at '/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2090' bound to instance 'U0' of component 'axi_uartlite' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:161]
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INFO: [Synth 8-638] synthesizing module 'axi_uartlite' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2160]
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Parameter C_FAMILY bound to: kintex7 - type: string
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Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
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Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
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Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
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Parameter C_BAUDRATE bound to: 38400 - type: integer
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Parameter C_DATA_BITS bound to: 8 - type: integer
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Parameter C_USE_PARITY bound to: 0 - type: integer
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Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2109]
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INFO: [Synth 8-5534] Detected attribute (* max_fanout = "10000" *) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2110]
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INFO: [Synth 8-638] synthesizing module 'uartlite_core' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1615]
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Parameter C_FAMILY bound to: kintex7 - type: string
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Parameter C_S_AXI_ACLK_FREQ_HZ bound to: 100000000 - type: integer
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Parameter C_BAUDRATE bound to: 38400 - type: integer
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Parameter C_DATA_BITS bound to: 8 - type: integer
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Parameter C_USE_PARITY bound to: 0 - type: integer
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Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-638] synthesizing module 'baudrate' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1418]
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Parameter C_RATIO bound to: 163 - type: integer
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INFO: [Synth 8-256] done synthesizing module 'baudrate' (1#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1418]
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INFO: [Synth 8-3919] null assignment ignored [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1881]
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INFO: [Synth 8-638] synthesizing module 'uartlite_rx' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:909]
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Parameter C_FAMILY bound to: kintex7 - type: string
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Parameter C_DATA_BITS bound to: 8 - type: integer
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Parameter C_USE_PARITY bound to: 0 - type: integer
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Parameter C_ODD_PARITY bound to: 0 - type: integer
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INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:106]
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Parameter C_CDC_TYPE bound to: 1 - type: integer
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Parameter C_RESET_STATE bound to: 0 - type: integer
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Parameter C_SINGLE_BIT bound to: 1 - type: integer
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Parameter C_FLOP_INPUT bound to: 0 - type: integer
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Parameter C_VECTOR_WIDTH bound to: 32 - type: integer
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Parameter C_MTBF_STAGES bound to: 4 - type: integer
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Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:514]
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Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:545]
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Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:554]
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Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:564]
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Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:574]
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Parameter INIT bound to: 1'b0
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INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:584]
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INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (2#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_cdc_v1_0_rfs.vhd:106]
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INFO: [Synth 8-638] synthesizing module 'dynshreg_i_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
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Parameter C_DEPTH bound to: 16 - type: integer
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Parameter C_DWIDTH bound to: 1 - type: integer
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Parameter C_INIT_VALUE bound to: 1'b0
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Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-256] done synthesizing module 'dynshreg_i_f' (3#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
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INFO: [Synth 8-638] synthesizing module 'srl_fifo_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
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Parameter C_DWIDTH bound to: 8 - type: integer
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Parameter C_DEPTH bound to: 16 - type: integer
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Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-638] synthesizing module 'srl_fifo_rbu_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
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| 102 |
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Parameter C_DWIDTH bound to: 8 - type: integer
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| 103 |
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Parameter C_DEPTH bound to: 16 - type: integer
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| 104 |
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Parameter C_FAMILY bound to: kintex7 - type: string
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| 105 |
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INFO: [Synth 8-638] synthesizing module 'cntr_incr_decr_addn_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
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| 106 |
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Parameter C_SIZE bound to: 5 - type: integer
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| 107 |
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Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-256] done synthesizing module 'cntr_incr_decr_addn_f' (4#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:143]
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INFO: [Synth 8-638] synthesizing module 'dynshreg_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
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| 110 |
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Parameter C_DEPTH bound to: 16 - type: integer
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| 111 |
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Parameter C_DWIDTH bound to: 8 - type: integer
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| 112 |
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Parameter C_FAMILY bound to: kintex7 - type: string
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INFO: [Synth 8-256] done synthesizing module 'dynshreg_f' (5#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:397]
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INFO: [Synth 8-256] done synthesizing module 'srl_fifo_rbu_f' (6#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:697]
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INFO: [Synth 8-256] done synthesizing module 'srl_fifo_f' (7#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:1000]
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INFO: [Synth 8-256] done synthesizing module 'uartlite_rx' (8#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:909]
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INFO: [Synth 8-638] synthesizing module 'uartlite_tx' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
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| 118 |
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Parameter C_FAMILY bound to: kintex7 - type: string
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| 119 |
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Parameter C_DATA_BITS bound to: 8 - type: integer
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| 120 |
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Parameter C_USE_PARITY bound to: 0 - type: integer
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| 121 |
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Parameter C_ODD_PARITY bound to: 0 - type: integer
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| 122 |
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INFO: [Synth 8-638] synthesizing module 'dynshreg_i_f__parameterized0' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
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| 123 |
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Parameter C_DEPTH bound to: 16 - type: integer
|
| 124 |
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Parameter C_DWIDTH bound to: 1 - type: integer
|
| 125 |
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Parameter C_INIT_VALUE bound to: 16'b1000000000000000
|
| 126 |
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Parameter C_FAMILY bound to: kintex7 - type: string
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| 127 |
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INFO: [Synth 8-256] done synthesizing module 'dynshreg_i_f__parameterized0' (8#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:168]
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| 128 |
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INFO: [Synth 8-256] done synthesizing module 'uartlite_tx' (9#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:408]
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| 129 |
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INFO: [Synth 8-256] done synthesizing module 'uartlite_core' (10#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:1615]
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| 130 |
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INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
|
| 131 |
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Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
| 132 |
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Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
|
| 133 |
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Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000000001111
|
| 134 |
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Parameter C_USE_WSTRB bound to: 0 - type: integer
|
| 135 |
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Parameter C_DPHASE_TIMEOUT bound to: 0 - type: integer
|
| 136 |
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Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
|
| 137 |
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Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
|
| 138 |
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Parameter C_FAMILY bound to: kintex7 - type: string
|
| 139 |
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INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
|
| 140 |
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Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
|
| 141 |
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Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
|
| 142 |
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Parameter C_IPIF_ABUS_WIDTH bound to: 4 - type: integer
|
| 143 |
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Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer
|
| 144 |
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Parameter C_S_AXI_MIN_SIZE bound to: 15 - type: integer
|
| 145 |
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Parameter C_USE_WSTRB bound to: 0 - type: integer
|
| 146 |
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Parameter C_DPHASE_TIMEOUT bound to: 0 - type: integer
|
| 147 |
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Parameter C_FAMILY bound to: kintex7 - type: string
|
| 148 |
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INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
|
| 149 |
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Parameter C_BUS_AWIDTH bound to: 4 - type: integer
|
| 150 |
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Parameter C_S_AXI_MIN_SIZE bound to: 15 - type: integer
|
| 151 |
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Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111
|
| 152 |
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Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100
|
| 153 |
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Parameter C_FAMILY bound to: nofamily - type: string
|
| 154 |
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INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
|
| 155 |
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Parameter C_AB bound to: 2 - type: integer
|
| 156 |
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Parameter C_AW bound to: 2 - type: integer
|
| 157 |
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Parameter C_BAR bound to: 2'b00
|
| 158 |
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Parameter C_FAMILY bound to: nofamily - type: string
|
| 159 |
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INFO: [Synth 8-256] done synthesizing module 'pselect_f' (11#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
|
| 160 |
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INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
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| 161 |
|
|
Parameter C_AB bound to: 2 - type: integer
|
| 162 |
|
|
Parameter C_AW bound to: 2 - type: integer
|
| 163 |
|
|
Parameter C_BAR bound to: 2'b01
|
| 164 |
|
|
Parameter C_FAMILY bound to: nofamily - type: string
|
| 165 |
|
|
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (11#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
|
| 166 |
|
|
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
|
| 167 |
|
|
Parameter C_AB bound to: 2 - type: integer
|
| 168 |
|
|
Parameter C_AW bound to: 2 - type: integer
|
| 169 |
|
|
Parameter C_BAR bound to: 2'b10
|
| 170 |
|
|
Parameter C_FAMILY bound to: nofamily - type: string
|
| 171 |
|
|
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (11#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
|
| 172 |
|
|
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
|
| 173 |
|
|
Parameter C_AB bound to: 2 - type: integer
|
| 174 |
|
|
Parameter C_AW bound to: 2 - type: integer
|
| 175 |
|
|
Parameter C_BAR bound to: 2'b11
|
| 176 |
|
|
Parameter C_FAMILY bound to: nofamily - type: string
|
| 177 |
|
|
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (11#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
|
| 178 |
|
|
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (12#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
|
| 179 |
|
|
INFO: [Synth 8-226] default block is never used [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
|
| 180 |
|
|
WARNING: [Synth 8-6014] Unused sequential element is_read_reg was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2447]
|
| 181 |
|
|
WARNING: [Synth 8-6014] Unused sequential element is_write_reg was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2448]
|
| 182 |
|
|
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (13#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
|
| 183 |
|
|
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (14#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
|
| 184 |
|
|
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite' (15#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:2160]
|
| 185 |
|
|
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite_module' (16#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/synth/axi_uartlite_module.vhd:86]
|
| 186 |
|
|
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[2]
|
| 187 |
|
|
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[3]
|
| 188 |
|
|
WARNING: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW
|
| 189 |
|
|
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3]
|
| 190 |
|
|
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2]
|
| 191 |
|
|
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1]
|
| 192 |
|
|
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0]
|
| 193 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk
|
| 194 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn
|
| 195 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[31]
|
| 196 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[30]
|
| 197 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[29]
|
| 198 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[28]
|
| 199 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[27]
|
| 200 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[26]
|
| 201 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[25]
|
| 202 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[24]
|
| 203 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[23]
|
| 204 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[22]
|
| 205 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[21]
|
| 206 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[20]
|
| 207 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[19]
|
| 208 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[18]
|
| 209 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[17]
|
| 210 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[16]
|
| 211 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[15]
|
| 212 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[14]
|
| 213 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[13]
|
| 214 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[12]
|
| 215 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[11]
|
| 216 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[10]
|
| 217 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[9]
|
| 218 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[8]
|
| 219 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[7]
|
| 220 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[6]
|
| 221 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[5]
|
| 222 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[4]
|
| 223 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[3]
|
| 224 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[2]
|
| 225 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[1]
|
| 226 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[0]
|
| 227 |
|
|
WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn
|
| 228 |
|
|
WARNING: [Synth 8-3331] design uartlite_core has unconnected port bus2ip_cs
|
| 229 |
|
|
---------------------------------------------------------------------------------
|
| 230 |
|
|
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1321.680 ; gain = 129.531 ; free physical = 1601 ; free virtual = 7782
|
| 231 |
|
|
---------------------------------------------------------------------------------
|
| 232 |
|
|
|
| 233 |
|
|
Report Check Netlist:
|
| 234 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 235 |
|
|
| |Item |Errors |Warnings |Status |Description |
|
| 236 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 237 |
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
| 238 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 239 |
|
|
---------------------------------------------------------------------------------
|
| 240 |
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1321.680 ; gain = 129.531 ; free physical = 1591 ; free virtual = 7773
|
| 241 |
|
|
---------------------------------------------------------------------------------
|
| 242 |
|
|
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
|
| 243 |
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
| 244 |
|
|
INFO: [Device 21-403] Loading part xc7k325tffg900-2
|
| 245 |
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
| 246 |
|
|
|
| 247 |
|
|
Processing XDC Constraints
|
| 248 |
|
|
Initializing timing engine
|
| 249 |
|
|
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc] for cell 'U0'
|
| 250 |
|
|
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc] for cell 'U0'
|
| 251 |
|
|
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'U0'
|
| 252 |
|
|
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'U0'
|
| 253 |
|
|
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'U0'
|
| 254 |
|
|
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'U0'
|
| 255 |
|
|
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc]
|
| 256 |
|
|
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc]
|
| 257 |
|
|
Completed Processing XDC Constraints
|
| 258 |
|
|
|
| 259 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
| 260 |
|
|
A total of 6 instances were transformed.
|
| 261 |
|
|
FDR => FDRE: 6 instances
|
| 262 |
|
|
|
| 263 |
|
|
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1697.844 ; gain = 0.000 ; free physical = 981 ; free virtual = 7202
|
| 264 |
|
|
---------------------------------------------------------------------------------
|
| 265 |
|
|
Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1140 ; free virtual = 7362
|
| 266 |
|
|
---------------------------------------------------------------------------------
|
| 267 |
|
|
---------------------------------------------------------------------------------
|
| 268 |
|
|
Start Loading Part and Timing Information
|
| 269 |
|
|
---------------------------------------------------------------------------------
|
| 270 |
|
|
Loading part: xc7k325tffg900-2
|
| 271 |
|
|
---------------------------------------------------------------------------------
|
| 272 |
|
|
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1140 ; free virtual = 7362
|
| 273 |
|
|
---------------------------------------------------------------------------------
|
| 274 |
|
|
---------------------------------------------------------------------------------
|
| 275 |
|
|
Start Applying 'set_property' XDC Constraints
|
| 276 |
|
|
---------------------------------------------------------------------------------
|
| 277 |
|
|
Applied set_property DONT_TOUCH = true for U0. (constraint file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/dont_touch.xdc, line 9).
|
| 278 |
|
|
---------------------------------------------------------------------------------
|
| 279 |
|
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1144 ; free virtual = 7366
|
| 280 |
|
|
---------------------------------------------------------------------------------
|
| 281 |
|
|
INFO: [Synth 8-5546] ROM "EN_16x_Baud" won't be mapped to RAM because it is too sparse
|
| 282 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 283 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 284 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 285 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 286 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 287 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 288 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 289 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 290 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 291 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 292 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 293 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 294 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 295 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 296 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 297 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 298 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 299 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 300 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 301 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 302 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 303 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 304 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 305 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 306 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 307 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 308 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 309 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 310 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 311 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 312 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 313 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/lib_srl_fifo_v1_0_rfs.vhd:490]
|
| 314 |
|
|
INFO: [Synth 8-5546] ROM "fifo_full_p1" won't be mapped to RAM because it is too sparse
|
| 315 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[0] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 316 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[1] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 317 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[2] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 318 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[3] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 319 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[4] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 320 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[5] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 321 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[6] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 322 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[7] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 323 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[8] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 324 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[9] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 325 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[10] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 326 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[11] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 327 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[12] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 328 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[13] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 329 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[14] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 330 |
|
|
WARNING: [Synth 8-6014] Unused sequential element INFERRED_GEN.data_reg[15] was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_uartlite_v2_0_vh_rfs.vhd:243]
|
| 331 |
|
|
INFO: [Synth 8-5544] ROM "mux_sel_is_zero" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
| 332 |
|
|
INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
| 333 |
|
|
INFO: [Synth 8-5544] ROM "s_axi_rresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
| 334 |
|
|
INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
| 335 |
|
|
INFO: [Synth 8-5544] ROM "s_axi_bresp_i" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
|
| 336 |
|
|
---------------------------------------------------------------------------------
|
| 337 |
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:25 ; elapsed = 00:00:37 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1127 ; free virtual = 7356
|
| 338 |
|
|
---------------------------------------------------------------------------------
|
| 339 |
|
|
|
| 340 |
|
|
Report RTL Partitions:
|
| 341 |
|
|
+-+--------------+------------+----------+
|
| 342 |
|
|
| |RTL Partition |Replication |Instances |
|
| 343 |
|
|
+-+--------------+------------+----------+
|
| 344 |
|
|
+-+--------------+------------+----------+
|
| 345 |
|
|
---------------------------------------------------------------------------------
|
| 346 |
|
|
Start RTL Component Statistics
|
| 347 |
|
|
---------------------------------------------------------------------------------
|
| 348 |
|
|
Detailed RTL Component Info :
|
| 349 |
|
|
+---Adders :
|
| 350 |
|
|
2 Input 8 Bit Adders := 1
|
| 351 |
|
|
3 Input 5 Bit Adders := 2
|
| 352 |
|
|
2 Input 3 Bit Adders := 1
|
| 353 |
|
|
+---Registers :
|
| 354 |
|
|
32 Bit Registers := 1
|
| 355 |
|
|
8 Bit Registers := 1
|
| 356 |
|
|
5 Bit Registers := 2
|
| 357 |
|
|
4 Bit Registers := 1
|
| 358 |
|
|
3 Bit Registers := 1
|
| 359 |
|
|
2 Bit Registers := 3
|
| 360 |
|
|
1 Bit Registers := 46
|
| 361 |
|
|
+---Muxes :
|
| 362 |
|
|
2 Input 8 Bit Muxes := 3
|
| 363 |
|
|
2 Input 4 Bit Muxes := 1
|
| 364 |
|
|
2 Input 3 Bit Muxes := 1
|
| 365 |
|
|
7 Input 2 Bit Muxes := 1
|
| 366 |
|
|
2 Input 2 Bit Muxes := 2
|
| 367 |
|
|
2 Input 1 Bit Muxes := 43
|
| 368 |
|
|
---------------------------------------------------------------------------------
|
| 369 |
|
|
Finished RTL Component Statistics
|
| 370 |
|
|
---------------------------------------------------------------------------------
|
| 371 |
|
|
---------------------------------------------------------------------------------
|
| 372 |
|
|
Start RTL Hierarchical Component Statistics
|
| 373 |
|
|
---------------------------------------------------------------------------------
|
| 374 |
|
|
Hierarchical RTL Component report
|
| 375 |
|
|
Module baudrate
|
| 376 |
|
|
Detailed RTL Component Info :
|
| 377 |
|
|
+---Adders :
|
| 378 |
|
|
2 Input 8 Bit Adders := 1
|
| 379 |
|
|
+---Registers :
|
| 380 |
|
|
8 Bit Registers := 1
|
| 381 |
|
|
1 Bit Registers := 1
|
| 382 |
|
|
+---Muxes :
|
| 383 |
|
|
2 Input 8 Bit Muxes := 1
|
| 384 |
|
|
2 Input 1 Bit Muxes := 1
|
| 385 |
|
|
Module cntr_incr_decr_addn_f
|
| 386 |
|
|
Detailed RTL Component Info :
|
| 387 |
|
|
+---Adders :
|
| 388 |
|
|
3 Input 5 Bit Adders := 1
|
| 389 |
|
|
+---Registers :
|
| 390 |
|
|
5 Bit Registers := 1
|
| 391 |
|
|
Module srl_fifo_rbu_f
|
| 392 |
|
|
Detailed RTL Component Info :
|
| 393 |
|
|
+---Registers :
|
| 394 |
|
|
1 Bit Registers := 3
|
| 395 |
|
|
+---Muxes :
|
| 396 |
|
|
2 Input 1 Bit Muxes := 3
|
| 397 |
|
|
Module uartlite_rx
|
| 398 |
|
|
Detailed RTL Component Info :
|
| 399 |
|
|
+---Registers :
|
| 400 |
|
|
1 Bit Registers := 15
|
| 401 |
|
|
+---Muxes :
|
| 402 |
|
|
2 Input 1 Bit Muxes := 12
|
| 403 |
|
|
Module uartlite_tx
|
| 404 |
|
|
Detailed RTL Component Info :
|
| 405 |
|
|
+---Adders :
|
| 406 |
|
|
2 Input 3 Bit Adders := 1
|
| 407 |
|
|
+---Registers :
|
| 408 |
|
|
3 Bit Registers := 1
|
| 409 |
|
|
1 Bit Registers := 6
|
| 410 |
|
|
+---Muxes :
|
| 411 |
|
|
2 Input 3 Bit Muxes := 1
|
| 412 |
|
|
2 Input 1 Bit Muxes := 10
|
| 413 |
|
|
Module uartlite_core
|
| 414 |
|
|
Detailed RTL Component Info :
|
| 415 |
|
|
+---Registers :
|
| 416 |
|
|
1 Bit Registers := 7
|
| 417 |
|
|
+---Muxes :
|
| 418 |
|
|
2 Input 8 Bit Muxes := 2
|
| 419 |
|
|
2 Input 1 Bit Muxes := 2
|
| 420 |
|
|
Module pselect_f
|
| 421 |
|
|
Detailed RTL Component Info :
|
| 422 |
|
|
+---Muxes :
|
| 423 |
|
|
2 Input 1 Bit Muxes := 1
|
| 424 |
|
|
Module pselect_f__parameterized0
|
| 425 |
|
|
Detailed RTL Component Info :
|
| 426 |
|
|
+---Muxes :
|
| 427 |
|
|
2 Input 1 Bit Muxes := 1
|
| 428 |
|
|
Module pselect_f__parameterized1
|
| 429 |
|
|
Detailed RTL Component Info :
|
| 430 |
|
|
+---Muxes :
|
| 431 |
|
|
2 Input 1 Bit Muxes := 1
|
| 432 |
|
|
Module pselect_f__parameterized2
|
| 433 |
|
|
Detailed RTL Component Info :
|
| 434 |
|
|
+---Muxes :
|
| 435 |
|
|
2 Input 1 Bit Muxes := 1
|
| 436 |
|
|
Module address_decoder
|
| 437 |
|
|
Detailed RTL Component Info :
|
| 438 |
|
|
+---Registers :
|
| 439 |
|
|
1 Bit Registers := 6
|
| 440 |
|
|
Module slave_attachment
|
| 441 |
|
|
Detailed RTL Component Info :
|
| 442 |
|
|
+---Registers :
|
| 443 |
|
|
32 Bit Registers := 1
|
| 444 |
|
|
4 Bit Registers := 1
|
| 445 |
|
|
2 Bit Registers := 3
|
| 446 |
|
|
1 Bit Registers := 5
|
| 447 |
|
|
+---Muxes :
|
| 448 |
|
|
2 Input 4 Bit Muxes := 1
|
| 449 |
|
|
7 Input 2 Bit Muxes := 1
|
| 450 |
|
|
2 Input 2 Bit Muxes := 2
|
| 451 |
|
|
2 Input 1 Bit Muxes := 8
|
| 452 |
|
|
---------------------------------------------------------------------------------
|
| 453 |
|
|
Finished RTL Hierarchical Component Statistics
|
| 454 |
|
|
---------------------------------------------------------------------------------
|
| 455 |
|
|
---------------------------------------------------------------------------------
|
| 456 |
|
|
Start Part Resource Summary
|
| 457 |
|
|
---------------------------------------------------------------------------------
|
| 458 |
|
|
Part Resources:
|
| 459 |
|
|
DSPs: 840 (col length:140)
|
| 460 |
|
|
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
|
| 461 |
|
|
---------------------------------------------------------------------------------
|
| 462 |
|
|
Finished Part Resource Summary
|
| 463 |
|
|
---------------------------------------------------------------------------------
|
| 464 |
|
|
---------------------------------------------------------------------------------
|
| 465 |
|
|
Start Cross Boundary and Area Optimization
|
| 466 |
|
|
---------------------------------------------------------------------------------
|
| 467 |
|
|
WARNING: [Synth 8-6014] Unused sequential element AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/MEM_DECODE_GEN[0].cs_out_i_reg was removed. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2004]
|
| 468 |
|
|
INFO: [Synth 8-5546] ROM "UARTLITE_CORE_I/BAUD_RATE_I/EN_16x_Baud" won't be mapped to RAM because it is too sparse
|
| 469 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[31]
|
| 470 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[30]
|
| 471 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[29]
|
| 472 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[28]
|
| 473 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[27]
|
| 474 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[26]
|
| 475 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[25]
|
| 476 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[24]
|
| 477 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[23]
|
| 478 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[22]
|
| 479 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[21]
|
| 480 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[20]
|
| 481 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[19]
|
| 482 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[18]
|
| 483 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[17]
|
| 484 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[16]
|
| 485 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[15]
|
| 486 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[14]
|
| 487 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[13]
|
| 488 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[12]
|
| 489 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[11]
|
| 490 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[10]
|
| 491 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[9]
|
| 492 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wdata[8]
|
| 493 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[3]
|
| 494 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[2]
|
| 495 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[1]
|
| 496 |
|
|
WARNING: [Synth 8-3331] design axi_uartlite has unconnected port s_axi_wstrb[0]
|
| 497 |
|
|
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_uartlite.
|
| 498 |
|
|
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_uartlite.
|
| 499 |
|
|
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/underflow_i_reg) is unused and will be removed from module axi_uartlite.
|
| 500 |
|
|
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/overflow_i_reg) is unused and will be removed from module axi_uartlite.
|
| 501 |
|
|
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/underflow_i_reg) is unused and will be removed from module axi_uartlite.
|
| 502 |
|
|
INFO: [Synth 8-3332] Sequential element (UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/overflow_i_reg) is unused and will be removed from module axi_uartlite.
|
| 503 |
|
|
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[1]) is unused and will be removed from module axi_uartlite.
|
| 504 |
|
|
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[0]) is unused and will be removed from module axi_uartlite.
|
| 505 |
|
|
---------------------------------------------------------------------------------
|
| 506 |
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:38 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 1107 ; free virtual = 7338
|
| 507 |
|
|
---------------------------------------------------------------------------------
|
| 508 |
|
|
|
| 509 |
|
|
Report RTL Partitions:
|
| 510 |
|
|
+-+--------------+------------+----------+
|
| 511 |
|
|
| |RTL Partition |Replication |Instances |
|
| 512 |
|
|
+-+--------------+------------+----------+
|
| 513 |
|
|
+-+--------------+------------+----------+
|
| 514 |
|
|
---------------------------------------------------------------------------------
|
| 515 |
|
|
Start Applying XDC Timing Constraints
|
| 516 |
|
|
---------------------------------------------------------------------------------
|
| 517 |
|
|
---------------------------------------------------------------------------------
|
| 518 |
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 893 ; free virtual = 7124
|
| 519 |
|
|
---------------------------------------------------------------------------------
|
| 520 |
|
|
---------------------------------------------------------------------------------
|
| 521 |
|
|
Start Timing Optimization
|
| 522 |
|
|
---------------------------------------------------------------------------------
|
| 523 |
|
|
---------------------------------------------------------------------------------
|
| 524 |
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 858 ; free virtual = 7089
|
| 525 |
|
|
---------------------------------------------------------------------------------
|
| 526 |
|
|
|
| 527 |
|
|
Report RTL Partitions:
|
| 528 |
|
|
+-+--------------+------------+----------+
|
| 529 |
|
|
| |RTL Partition |Replication |Instances |
|
| 530 |
|
|
+-+--------------+------------+----------+
|
| 531 |
|
|
+-+--------------+------------+----------+
|
| 532 |
|
|
---------------------------------------------------------------------------------
|
| 533 |
|
|
Start Technology Mapping
|
| 534 |
|
|
---------------------------------------------------------------------------------
|
| 535 |
|
|
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0]) is unused and will be removed from module axi_uartlite.
|
| 536 |
|
|
INFO: [Synth 8-3332] Sequential element (AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0]) is unused and will be removed from module axi_uartlite.
|
| 537 |
|
|
---------------------------------------------------------------------------------
|
| 538 |
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 850 ; free virtual = 7081
|
| 539 |
|
|
---------------------------------------------------------------------------------
|
| 540 |
|
|
|
| 541 |
|
|
Report RTL Partitions:
|
| 542 |
|
|
+-+--------------+------------+----------+
|
| 543 |
|
|
| |RTL Partition |Replication |Instances |
|
| 544 |
|
|
+-+--------------+------------+----------+
|
| 545 |
|
|
+-+--------------+------------+----------+
|
| 546 |
|
|
---------------------------------------------------------------------------------
|
| 547 |
|
|
Start IO Insertion
|
| 548 |
|
|
---------------------------------------------------------------------------------
|
| 549 |
|
|
---------------------------------------------------------------------------------
|
| 550 |
|
|
Start Flattening Before IO Insertion
|
| 551 |
|
|
---------------------------------------------------------------------------------
|
| 552 |
|
|
---------------------------------------------------------------------------------
|
| 553 |
|
|
Finished Flattening Before IO Insertion
|
| 554 |
|
|
---------------------------------------------------------------------------------
|
| 555 |
|
|
---------------------------------------------------------------------------------
|
| 556 |
|
|
Start Final Netlist Cleanup
|
| 557 |
|
|
---------------------------------------------------------------------------------
|
| 558 |
|
|
---------------------------------------------------------------------------------
|
| 559 |
|
|
Finished Final Netlist Cleanup
|
| 560 |
|
|
---------------------------------------------------------------------------------
|
| 561 |
|
|
---------------------------------------------------------------------------------
|
| 562 |
|
|
Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 879 ; free virtual = 7111
|
| 563 |
|
|
---------------------------------------------------------------------------------
|
| 564 |
|
|
|
| 565 |
|
|
Report Check Netlist:
|
| 566 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 567 |
|
|
| |Item |Errors |Warnings |Status |Description |
|
| 568 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 569 |
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
| 570 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 571 |
|
|
---------------------------------------------------------------------------------
|
| 572 |
|
|
Start Renaming Generated Instances
|
| 573 |
|
|
---------------------------------------------------------------------------------
|
| 574 |
|
|
---------------------------------------------------------------------------------
|
| 575 |
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 879 ; free virtual = 7111
|
| 576 |
|
|
---------------------------------------------------------------------------------
|
| 577 |
|
|
|
| 578 |
|
|
Report RTL Partitions:
|
| 579 |
|
|
+-+--------------+------------+----------+
|
| 580 |
|
|
| |RTL Partition |Replication |Instances |
|
| 581 |
|
|
+-+--------------+------------+----------+
|
| 582 |
|
|
+-+--------------+------------+----------+
|
| 583 |
|
|
---------------------------------------------------------------------------------
|
| 584 |
|
|
Start Rebuilding User Hierarchy
|
| 585 |
|
|
---------------------------------------------------------------------------------
|
| 586 |
|
|
---------------------------------------------------------------------------------
|
| 587 |
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 877 ; free virtual = 7109
|
| 588 |
|
|
---------------------------------------------------------------------------------
|
| 589 |
|
|
---------------------------------------------------------------------------------
|
| 590 |
|
|
Start Renaming Generated Ports
|
| 591 |
|
|
---------------------------------------------------------------------------------
|
| 592 |
|
|
---------------------------------------------------------------------------------
|
| 593 |
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 877 ; free virtual = 7109
|
| 594 |
|
|
---------------------------------------------------------------------------------
|
| 595 |
|
|
---------------------------------------------------------------------------------
|
| 596 |
|
|
Start Handling Custom Attributes
|
| 597 |
|
|
---------------------------------------------------------------------------------
|
| 598 |
|
|
---------------------------------------------------------------------------------
|
| 599 |
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 876 ; free virtual = 7108
|
| 600 |
|
|
---------------------------------------------------------------------------------
|
| 601 |
|
|
---------------------------------------------------------------------------------
|
| 602 |
|
|
Start Renaming Generated Nets
|
| 603 |
|
|
---------------------------------------------------------------------------------
|
| 604 |
|
|
---------------------------------------------------------------------------------
|
| 605 |
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 876 ; free virtual = 7107
|
| 606 |
|
|
---------------------------------------------------------------------------------
|
| 607 |
|
|
---------------------------------------------------------------------------------
|
| 608 |
|
|
Start ROM, RAM, DSP and Shift Register Reporting
|
| 609 |
|
|
---------------------------------------------------------------------------------
|
| 610 |
|
|
|
| 611 |
|
|
Static Shift Register Report:
|
| 612 |
|
|
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|
| 613 |
|
|
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
|
| 614 |
|
|
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|
| 615 |
|
|
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[15][0] | 16 | 1 | NO | NO | YES | 1 | 0 |
|
| 616 |
|
|
|axi_uartlite | UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[15][0] | 16 | 1 | NO | NO | YES | 1 | 0 |
|
| 617 |
|
|
+-------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|
| 618 |
|
|
|
| 619 |
|
|
|
| 620 |
|
|
Dynamic Shift Register Report:
|
| 621 |
|
|
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
|
| 622 |
|
|
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
|
| 623 |
|
|
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
|
| 624 |
|
|
|dsrl | INFERRED_GEN.data_reg[15] | 16 | 1 | 1 | 0 | 0 | 0 | 0 |
|
| 625 |
|
|
|dsrl__1 | INFERRED_GEN.data_reg[15] | 16 | 8 | 8 | 0 | 0 | 0 | 0 |
|
| 626 |
|
|
|dsrl__2 | INFERRED_GEN.data_reg[15] | 16 | 1 | 1 | 0 | 0 | 0 | 0 |
|
| 627 |
|
|
+------------+---------------------------+--------+------------+--------+---------+--------+--------+--------+
|
| 628 |
|
|
|
| 629 |
|
|
---------------------------------------------------------------------------------
|
| 630 |
|
|
Finished ROM, RAM, DSP and Shift Register Reporting
|
| 631 |
|
|
---------------------------------------------------------------------------------
|
| 632 |
|
|
---------------------------------------------------------------------------------
|
| 633 |
|
|
Start Writing Synthesis Report
|
| 634 |
|
|
---------------------------------------------------------------------------------
|
| 635 |
|
|
|
| 636 |
|
|
Report BlackBoxes:
|
| 637 |
|
|
+-+--------------+----------+
|
| 638 |
|
|
| |BlackBox name |Instances |
|
| 639 |
|
|
+-+--------------+----------+
|
| 640 |
|
|
+-+--------------+----------+
|
| 641 |
|
|
|
| 642 |
|
|
Report Cell Usage:
|
| 643 |
|
|
+------+-------+------+
|
| 644 |
|
|
| |Cell |Count |
|
| 645 |
|
|
+------+-------+------+
|
| 646 |
|
|
|1 |LUT1 | 1|
|
| 647 |
|
|
|2 |LUT2 | 14|
|
| 648 |
|
|
|3 |LUT3 | 19|
|
| 649 |
|
|
|4 |LUT4 | 17|
|
| 650 |
|
|
|5 |LUT5 | 44|
|
| 651 |
|
|
|6 |LUT6 | 17|
|
| 652 |
|
|
|7 |SRL16E | 18|
|
| 653 |
|
|
|8 |FDR | 4|
|
| 654 |
|
|
|9 |FDRE | 72|
|
| 655 |
|
|
|10 |FDSE | 16|
|
| 656 |
|
|
+------+-------+------+
|
| 657 |
|
|
|
| 658 |
|
|
Report Instance Areas:
|
| 659 |
|
|
+------+--------------------------------------------------------------------------+-----------------------------+------+
|
| 660 |
|
|
| |Instance |Module |Cells |
|
| 661 |
|
|
+------+--------------------------------------------------------------------------+-----------------------------+------+
|
| 662 |
|
|
|1 |top | | 222|
|
| 663 |
|
|
|2 | U0 |axi_uartlite | 222|
|
| 664 |
|
|
|3 | AXI_LITE_IPIF_I |axi_lite_ipif | 65|
|
| 665 |
|
|
|4 | I_SLAVE_ATTACHMENT |slave_attachment | 65|
|
| 666 |
|
|
|5 | I_DECODER |address_decoder | 37|
|
| 667 |
|
|
|6 | \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I |pselect_f | 1|
|
| 668 |
|
|
|7 | \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I |pselect_f__parameterized1 | 1|
|
| 669 |
|
|
|8 | UARTLITE_CORE_I |uartlite_core | 157|
|
| 670 |
|
|
|9 | BAUD_RATE_I |baudrate | 22|
|
| 671 |
|
|
|10 | UARTLITE_RX_I |uartlite_rx | 77|
|
| 672 |
|
|
|11 | DELAY_16_I |dynshreg_i_f | 17|
|
| 673 |
|
|
|12 | INPUT_DOUBLE_REGS3 |cdc_sync | 5|
|
| 674 |
|
|
|13 | SRL_FIFO_I |srl_fifo_f_0 | 28|
|
| 675 |
|
|
|14 | I_SRL_FIFO_RBU_F |srl_fifo_rbu_f_1 | 28|
|
| 676 |
|
|
|15 | CNTR_INCR_DECR_ADDN_F_I |cntr_incr_decr_addn_f_2 | 17|
|
| 677 |
|
|
|16 | DYNSHREG_F_I |dynshreg_f_3 | 9|
|
| 678 |
|
|
|17 | UARTLITE_TX_I |uartlite_tx | 49|
|
| 679 |
|
|
|18 | MID_START_BIT_SRL16_I |dynshreg_i_f__parameterized0 | 3|
|
| 680 |
|
|
|19 | SRL_FIFO_I |srl_fifo_f | 31|
|
| 681 |
|
|
|20 | I_SRL_FIFO_RBU_F |srl_fifo_rbu_f | 31|
|
| 682 |
|
|
|21 | CNTR_INCR_DECR_ADDN_F_I |cntr_incr_decr_addn_f | 17|
|
| 683 |
|
|
|22 | DYNSHREG_F_I |dynshreg_f | 13|
|
| 684 |
|
|
+------+--------------------------------------------------------------------------+-----------------------------+------+
|
| 685 |
|
|
---------------------------------------------------------------------------------
|
| 686 |
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.844 ; gain = 505.695 ; free physical = 875 ; free virtual = 7107
|
| 687 |
|
|
---------------------------------------------------------------------------------
|
| 688 |
|
|
Synthesis finished with 0 errors, 0 critical warnings and 77 warnings.
|
| 689 |
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1697.844 ; gain = 129.531 ; free physical = 933 ; free virtual = 7165
|
| 690 |
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 1697.852 ; gain = 505.695 ; free physical = 933 ; free virtual = 7165
|
| 691 |
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
| 692 |
|
|
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
|
| 693 |
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
| 694 |
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
| 695 |
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
| 696 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
| 697 |
|
|
A total of 4 instances were transformed.
|
| 698 |
|
|
FDR => FDRE: 4 instances
|
| 699 |
|
|
|
| 700 |
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
| 701 |
|
|
82 Infos, 122 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
| 702 |
|
|
synth_design completed successfully
|
| 703 |
|
|
synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:47 . Memory (MB): peak = 1697.852 ; gain = 532.805 ; free physical = 936 ; free virtual = 7171
|
| 704 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/axi_uartlite_module.dcp' has been generated.
|
| 705 |
|
|
INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xci
|
| 706 |
|
|
INFO: [Coretcl 2-1174] Renamed 21 cell refs.
|
| 707 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/axi_uartlite_module_synth_1/axi_uartlite_module.dcp' has been generated.
|
| 708 |
|
|
INFO: [runtcl-4] Executing : report_utilization -file axi_uartlite_module_utilization_synth.rpt -pb axi_uartlite_module_utilization_synth.pb
|
| 709 |
|
|
report_utilization: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1721.855 ; gain = 0.000 ; free physical = 1500 ; free virtual = 7737
|
| 710 |
|
|
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:02:26 2020...
|
