URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [clk_gen_synth_1/] [.Xil/] [clk_gen_propImpl.xdc] - Blame information for rev 2

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Line No.	Rev	Author	Line
1	2	vv_gulyaev	`set_property SRC_FILE_INFO {cfile:/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc rfile:../../../../../../aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc id:1 order:EARLY scoped_inst:inst} [current_design]`
2			`set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design]`
3			`set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05`

vv_gulyaev

set_property SRC_FILE_INFO {cfile:/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc rfile:../../../../../../aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc id:1 order:EARLY scoped_inst:inst} [current_design]

set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design]

set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05

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Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [clk_gen_synth_1/] [.Xil/] [clk_gen_propImpl.xdc] - Blame information for rev 2