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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [clk_gen_synth_1/] [clk_gen.tcl] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev 
#
2 
# Synthesis run script generated by Vivado
3 
#
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proc create_report { reportName command } {
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  set status "."
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  append status $reportName ".fail"
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  if { [file exists $status] } {
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    eval file delete [glob $status]
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  }
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  send_msg_id runtcl-4 info "Executing : $command"
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  set retval [eval catch { $command } msg]
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  if { $retval != 0 } {
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    set fp [open $status w]
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    close $fp
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    send_msg_id runtcl-5 warning "$msg"
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  }
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}
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set_param project.vivado.isBlockSynthRun true
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set_msg_config -msgmgr_mode ooc_run
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create_project -in_memory -part xc7k325tffg900-2
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set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
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set_property webtalk.parent_dir /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.cache/wt [current_project]
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set_property parent.project_path /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.xpr [current_project]
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set_property XPM_LIBRARIES XPM_CDC [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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set_property board_part xilinx.com:kc705:part0:1.5 [current_project]
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set_property ip_output_repo /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.cache/ip [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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read_ip -quiet /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xci
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set_property used_in_implementation false [get_files -all /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc]
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set_property used_in_implementation false [get_files -all /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc]
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set_property used_in_implementation false [get_files -all /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc]
39 
 
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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# design are intentionally left as such for best results. Dcp files will be
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# stitched into the design at a later time, either when this synthesis run is
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# opened, or when it is stitched into a dependent implementation run.
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foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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  set_property used_in_implementation false $dcp
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}
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read_xdc dont_touch.xdc
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set_property used_in_implementation false [get_files dont_touch.xdc]
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set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1 -new_name clk_gen -ip [get_ips clk_gen]]
52 
 
53 
if { $cached_ip eq {} } {
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55 
synth_design -top clk_gen -part xc7k325tffg900-2 -mode out_of_context
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#---------------------------------------------------------
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# Generate Checkpoint/Stub/Simulation Files For IP Cache
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#---------------------------------------------------------
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# disable binary constraint mode for IPCache checkpoints
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set_param constraints.enableBinaryConstraints false
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63 
catch {
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 write_checkpoint -force -noxdef -rename_prefix clk_gen_ clk_gen.dcp
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 set ipCachedFiles {}
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 write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_gen_stub.v
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 lappend ipCachedFiles clk_gen_stub.v
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 write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_gen_stub.vhdl
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 lappend ipCachedFiles clk_gen_stub.vhdl
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73 
 write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_gen_sim_netlist.v
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 lappend ipCachedFiles clk_gen_sim_netlist.v
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 write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_gen_sim_netlist.vhdl
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 lappend ipCachedFiles clk_gen_sim_netlist.vhdl
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79 
 config_ip_cache -add -dcp clk_gen.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips clk_gen]
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}
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82 
rename_ref -prefix_all clk_gen_
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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write_checkpoint -force -noxdef clk_gen.dcp
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create_report "clk_gen_synth_1_synth_report_utilization_0" "report_utilization -file clk_gen_utilization_synth.rpt -pb clk_gen_utilization_synth.pb"
88 
 
89 
if { [catch {
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  file copy -force /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen.dcp /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp
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} _RESULT ] } {
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  send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
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  error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
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}
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96 
if { [catch {
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  write_verilog -force -mode synth_stub /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_stub.v
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} _RESULT ] } {
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  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
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}
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102 
if { [catch {
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  write_vhdl -force -mode synth_stub /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_stub.vhdl
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} _RESULT ] } {
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  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
106 
}
107 
 
108 
if { [catch {
109 
  write_verilog -force -mode funcsim /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_sim_netlist.v
110 
} _RESULT ] } {
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  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
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}
113 
 
114 
if { [catch {
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  write_vhdl -force -mode funcsim /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_sim_netlist.vhdl
116 
} _RESULT ] } {
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  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
118 
}
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120 
 
121 
} else {
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123 
 
124 
if { [catch {
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  file copy -force /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen.dcp /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp
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} _RESULT ] } {
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  send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
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  error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
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}
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131 
if { [catch {
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  file rename -force /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen_stub.v /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_stub.v
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} _RESULT ] } {
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  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
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}
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137 
if { [catch {
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  file rename -force /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen_stub.vhdl /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_stub.vhdl
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} _RESULT ] } {
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  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
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}
142 
 
143 
if { [catch {
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  file rename -force /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen_sim_netlist.v /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_sim_netlist.v
145 
} _RESULT ] } {
146 
  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
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}
148 
 
149 
if { [catch {
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  file rename -force /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen_sim_netlist.vhdl /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_sim_netlist.vhdl
151 
} _RESULT ] } {
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  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
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}
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155 
}; # end if cached_ip
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157 
if {[file isdir /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.ip_user_files/ip/clk_gen]} {
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  catch {
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    file copy -force /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_stub.v /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.ip_user_files/ip/clk_gen
160 
  }
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}
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163 
if {[file isdir /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.ip_user_files/ip/clk_gen]} {
164 
  catch {
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    file copy -force /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_stub.vhdl /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.ip_user_files/ip/clk_gen
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  }
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}

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