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vv_gulyaev |
#-----------------------------------------------------------
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# Vivado v2017.4 (64-bit)
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# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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# Start of session at: Thu Jul 30 13:01:29 2020
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# Process ID: 6007
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# Current directory: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1
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# Command line: vivado -log clk_gen.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_gen.tcl
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# Log file: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen.vds
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# Journal file: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/vivado.jou
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#-----------------------------------------------------------
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source clk_gen.tcl -notrace
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Command: synth_design -top clk_gen -part xc7k325tffg900-2 -mode out_of_context
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 6028
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1275.145 ; gain = 83.000 ; free physical = 1593 ; free virtual = 7772
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---------------------------------------------------------------------------------
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INFO: [Synth 8-638] synthesizing module 'clk_gen' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v:70]
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INFO: [Synth 8-638] synthesizing module 'clk_gen_clk_wiz' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v:68]
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INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483]
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Parameter CAPACITANCE bound to: DONT_CARE - type: string
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Parameter DIFF_TERM bound to: FALSE - type: string
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Parameter DQS_BIAS bound to: FALSE - type: string
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Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
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Parameter IBUF_LOW_PWR bound to: TRUE - type: string
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Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
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Parameter IOSTANDARD bound to: DEFAULT - type: string
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INFO: [Synth 8-256] done synthesizing module 'IBUFDS' (1#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483]
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INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
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Parameter BANDWIDTH bound to: OPTIMIZED - type: string
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Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float
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Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
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Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
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Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float
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Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
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Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float
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Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
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Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
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Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
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Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
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Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
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Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
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Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
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Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
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Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
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Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
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Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
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Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
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Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
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Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
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Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
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Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
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Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
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Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
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Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
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Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
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Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
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Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
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Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
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Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
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Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
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Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
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Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
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Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
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Parameter COMPENSATION bound to: ZHOLD - type: string
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Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
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Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
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Parameter IS_PSEN_INVERTED bound to: 1'b0
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Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
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Parameter IS_PWRDWN_INVERTED bound to: 1'b0
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Parameter IS_RST_INVERTED bound to: 1'b0
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Parameter REF_JITTER1 bound to: 0.010000 - type: float
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Parameter REF_JITTER2 bound to: 0.010000 - type: float
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Parameter SS_EN bound to: FALSE - type: string
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Parameter SS_MODE bound to: CENTER_HIGH - type: string
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Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
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Parameter STARTUP_WAIT bound to: FALSE - type: string
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INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
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INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
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INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
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INFO: [Synth 8-256] done synthesizing module 'clk_gen_clk_wiz' (4#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v:68]
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INFO: [Synth 8-256] done synthesizing module 'clk_gen' (5#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v:70]
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---------------------------------------------------------------------------------
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Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1316.676 ; gain = 124.531 ; free physical = 1563 ; free virtual = 7744
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| |Item |Errors |Warnings |Status |Description |
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+------+------------------+-------+---------+-------+------------------+
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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+------+------------------+-------+---------+-------+------------------+
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1316.676 ; gain = 124.531 ; free physical = 1561 ; free virtual = 7742
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---------------------------------------------------------------------------------
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INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Device 21-403] Loading part xc7k325tffg900-2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Processing XDC Constraints
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Initializing timing engine
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Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc] for cell 'inst'
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Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc] for cell 'inst'
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Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'inst'
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Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'inst'
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Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'inst'
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Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'inst'
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_gen_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/clk_gen_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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INFO: [Timing 38-2] Deriving generated clocks
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc]
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc]
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Completed Processing XDC Constraints
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1604.902 ; gain = 0.000 ; free physical = 1018 ; free virtual = 7240
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1139 ; free virtual = 7362
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7k325tffg900-2
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1140 ; free virtual = 7362
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
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Applied set_property DONT_TOUCH = true for inst. (constraint file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc, line 9).
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---------------------------------------------------------------------------------
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1144 ; free virtual = 7366
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1143 ; free virtual = 7365
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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---------------------------------------------------------------------------------
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Finished RTL Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
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---------------------------------------------------------------------------------
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Finished RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Part Resource Summary
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---------------------------------------------------------------------------------
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Part Resources:
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DSPs: 840 (col length:140)
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BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
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---------------------------------------------------------------------------------
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Finished Part Resource Summary
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1142 ; free virtual = 7365
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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| 183 |
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+-+--------------+------------+----------+
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| 184 |
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+-+--------------+------------+----------+
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| 185 |
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---------------------------------------------------------------------------------
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Start Applying XDC Timing Constraints
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1634.902 ; gain = 442.758 ; free physical = 909 ; free virtual = 7140
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---------------------------------------------------------------------------------
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| 191 |
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---------------------------------------------------------------------------------
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Start Timing Optimization
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1634.902 ; gain = 442.758 ; free physical = 909 ; free virtual = 7140
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---------------------------------------------------------------------------------
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| 198 |
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| 200 |
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| |RTL Partition |Replication |Instances |
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| 201 |
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+-+--------------+------------+----------+
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| 202 |
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+-+--------------+------------+----------+
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| 203 |
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---------------------------------------------------------------------------------
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Start Technology Mapping
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 909 ; free virtual = 7140
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---------------------------------------------------------------------------------
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| 209 |
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| 210 |
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Report RTL Partitions:
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| 211 |
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+-+--------------+------------+----------+
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| 212 |
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|
| |RTL Partition |Replication |Instances |
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| 213 |
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+-+--------------+------------+----------+
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| 214 |
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+-+--------------+------------+----------+
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| 215 |
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---------------------------------------------------------------------------------
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| 216 |
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Start IO Insertion
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| 217 |
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---------------------------------------------------------------------------------
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| 218 |
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---------------------------------------------------------------------------------
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| 219 |
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Start Flattening Before IO Insertion
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| 220 |
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---------------------------------------------------------------------------------
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| 221 |
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---------------------------------------------------------------------------------
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| 222 |
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Finished Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| 236 |
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| |Item |Errors |Warnings |Status |Description |
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| 237 |
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+------+------------------+-------+---------+-------+------------------+
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| 238 |
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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| 239 |
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+------+------------------+-------+---------+-------+------------------+
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| 240 |
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---------------------------------------------------------------------------------
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Start Renaming Generated Instances
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---------------------------------------------------------------------------------
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| 243 |
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---------------------------------------------------------------------------------
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
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---------------------------------------------------------------------------------
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| 246 |
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| 247 |
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Report RTL Partitions:
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| 248 |
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+-+--------------+------------+----------+
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| 249 |
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|
| |RTL Partition |Replication |Instances |
|
| 250 |
|
|
+-+--------------+------------+----------+
|
| 251 |
|
|
+-+--------------+------------+----------+
|
| 252 |
|
|
---------------------------------------------------------------------------------
|
| 253 |
|
|
Start Rebuilding User Hierarchy
|
| 254 |
|
|
---------------------------------------------------------------------------------
|
| 255 |
|
|
---------------------------------------------------------------------------------
|
| 256 |
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 257 |
|
|
---------------------------------------------------------------------------------
|
| 258 |
|
|
---------------------------------------------------------------------------------
|
| 259 |
|
|
Start Renaming Generated Ports
|
| 260 |
|
|
---------------------------------------------------------------------------------
|
| 261 |
|
|
---------------------------------------------------------------------------------
|
| 262 |
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 263 |
|
|
---------------------------------------------------------------------------------
|
| 264 |
|
|
---------------------------------------------------------------------------------
|
| 265 |
|
|
Start Handling Custom Attributes
|
| 266 |
|
|
---------------------------------------------------------------------------------
|
| 267 |
|
|
---------------------------------------------------------------------------------
|
| 268 |
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 269 |
|
|
---------------------------------------------------------------------------------
|
| 270 |
|
|
---------------------------------------------------------------------------------
|
| 271 |
|
|
Start Renaming Generated Nets
|
| 272 |
|
|
---------------------------------------------------------------------------------
|
| 273 |
|
|
---------------------------------------------------------------------------------
|
| 274 |
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 275 |
|
|
---------------------------------------------------------------------------------
|
| 276 |
|
|
---------------------------------------------------------------------------------
|
| 277 |
|
|
Start Writing Synthesis Report
|
| 278 |
|
|
---------------------------------------------------------------------------------
|
| 279 |
|
|
|
| 280 |
|
|
Report BlackBoxes:
|
| 281 |
|
|
+-+--------------+----------+
|
| 282 |
|
|
| |BlackBox name |Instances |
|
| 283 |
|
|
+-+--------------+----------+
|
| 284 |
|
|
+-+--------------+----------+
|
| 285 |
|
|
|
| 286 |
|
|
Report Cell Usage:
|
| 287 |
|
|
+------+-----------+------+
|
| 288 |
|
|
| |Cell |Count |
|
| 289 |
|
|
+------+-----------+------+
|
| 290 |
|
|
|1 |BUFG | 2|
|
| 291 |
|
|
|2 |MMCME2_ADV | 1|
|
| 292 |
|
|
|3 |IBUFDS | 1|
|
| 293 |
|
|
+------+-----------+------+
|
| 294 |
|
|
|
| 295 |
|
|
Report Instance Areas:
|
| 296 |
|
|
+------+---------+----------------+------+
|
| 297 |
|
|
| |Instance |Module |Cells |
|
| 298 |
|
|
+------+---------+----------------+------+
|
| 299 |
|
|
|1 |top | | 4|
|
| 300 |
|
|
|2 | inst |clk_gen_clk_wiz | 4|
|
| 301 |
|
|
+------+---------+----------------+------+
|
| 302 |
|
|
---------------------------------------------------------------------------------
|
| 303 |
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 304 |
|
|
---------------------------------------------------------------------------------
|
| 305 |
|
|
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
| 306 |
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1644.918 ; gain = 164.547 ; free physical = 919 ; free virtual = 7150
|
| 307 |
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.926 ; gain = 452.773 ; free physical = 918 ; free virtual = 7150
|
| 308 |
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
| 309 |
|
|
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
| 310 |
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
| 311 |
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
| 312 |
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
| 313 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
| 314 |
|
|
No Unisim elements were transformed.
|
| 315 |
|
|
|
| 316 |
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
| 317 |
|
|
25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
| 318 |
|
|
synth_design completed successfully
|
| 319 |
|
|
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:46 . Memory (MB): peak = 1654.918 ; gain = 489.875 ; free physical = 879 ; free virtual = 7111
|
| 320 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen.dcp' has been generated.
|
| 321 |
|
|
INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xci
|
| 322 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen.dcp' has been generated.
|
| 323 |
|
|
INFO: [runtcl-4] Executing : report_utilization -file clk_gen_utilization_synth.rpt -pb clk_gen_utilization_synth.pb
|
| 324 |
|
|
report_utilization: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1658.918 ; gain = 0.000 ; free physical = 926 ; free virtual = 7158
|
| 325 |
|
|
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:02:25 2020...
|
