| 1 |
2 |
vv_gulyaev |
|
| 2 |
|
|
*** Running vivado
|
| 3 |
|
|
with args -log clk_gen.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_gen.tcl
|
| 4 |
|
|
|
| 5 |
|
|
|
| 6 |
|
|
****** Vivado v2017.4 (64-bit)
|
| 7 |
|
|
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
|
| 8 |
|
|
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
| 9 |
|
|
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
| 10 |
|
|
|
| 11 |
|
|
source clk_gen.tcl -notrace
|
| 12 |
|
|
INFO: [IP_Flow 19-4838] Using cached IP synthesis design for IP clk_gen, cache-ID = bd4a7ee8a4ca1bdd.
|
| 13 |
|
|
INFO: [Common 17-206] Exiting Vivado at Wed Jul 29 15:22:05 2020...
|
| 14 |
|
|
|
| 15 |
|
|
*** Running vivado
|
| 16 |
|
|
with args -log clk_gen.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_gen.tcl
|
| 17 |
|
|
|
| 18 |
|
|
|
| 19 |
|
|
****** Vivado v2017.4 (64-bit)
|
| 20 |
|
|
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
|
| 21 |
|
|
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
| 22 |
|
|
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
| 23 |
|
|
|
| 24 |
|
|
source clk_gen.tcl -notrace
|
| 25 |
|
|
Command: synth_design -top clk_gen -part xc7k325tffg900-2 -mode out_of_context
|
| 26 |
|
|
Starting synth_design
|
| 27 |
|
|
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
|
| 28 |
|
|
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
|
| 29 |
|
|
INFO: Launching helper process for spawning children vivado processes
|
| 30 |
|
|
INFO: Helper process launched with PID 6028
|
| 31 |
|
|
---------------------------------------------------------------------------------
|
| 32 |
|
|
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1275.145 ; gain = 83.000 ; free physical = 1593 ; free virtual = 7772
|
| 33 |
|
|
---------------------------------------------------------------------------------
|
| 34 |
|
|
INFO: [Synth 8-638] synthesizing module 'clk_gen' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v:70]
|
| 35 |
|
|
INFO: [Synth 8-638] synthesizing module 'clk_gen_clk_wiz' [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v:68]
|
| 36 |
|
|
INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483]
|
| 37 |
|
|
Parameter CAPACITANCE bound to: DONT_CARE - type: string
|
| 38 |
|
|
Parameter DIFF_TERM bound to: FALSE - type: string
|
| 39 |
|
|
Parameter DQS_BIAS bound to: FALSE - type: string
|
| 40 |
|
|
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
|
| 41 |
|
|
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
|
| 42 |
|
|
Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
|
| 43 |
|
|
Parameter IOSTANDARD bound to: DEFAULT - type: string
|
| 44 |
|
|
INFO: [Synth 8-256] done synthesizing module 'IBUFDS' (1#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483]
|
| 45 |
|
|
INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
|
| 46 |
|
|
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
|
| 47 |
|
|
Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: float
|
| 48 |
|
|
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
|
| 49 |
|
|
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
|
| 50 |
|
|
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float
|
| 51 |
|
|
Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
|
| 52 |
|
|
Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float
|
| 53 |
|
|
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
|
| 54 |
|
|
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
|
| 55 |
|
|
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
|
| 56 |
|
|
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
|
| 57 |
|
|
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
|
| 58 |
|
|
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
|
| 59 |
|
|
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
|
| 60 |
|
|
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
|
| 61 |
|
|
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
|
| 62 |
|
|
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
|
| 63 |
|
|
Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
|
| 64 |
|
|
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
|
| 65 |
|
|
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
|
| 66 |
|
|
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
|
| 67 |
|
|
Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
|
| 68 |
|
|
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
|
| 69 |
|
|
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
|
| 70 |
|
|
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
|
| 71 |
|
|
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
|
| 72 |
|
|
Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
|
| 73 |
|
|
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
|
| 74 |
|
|
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
|
| 75 |
|
|
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
|
| 76 |
|
|
Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
|
| 77 |
|
|
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
|
| 78 |
|
|
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
|
| 79 |
|
|
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
|
| 80 |
|
|
Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
|
| 81 |
|
|
Parameter COMPENSATION bound to: ZHOLD - type: string
|
| 82 |
|
|
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
|
| 83 |
|
|
Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
|
| 84 |
|
|
Parameter IS_PSEN_INVERTED bound to: 1'b0
|
| 85 |
|
|
Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
|
| 86 |
|
|
Parameter IS_PWRDWN_INVERTED bound to: 1'b0
|
| 87 |
|
|
Parameter IS_RST_INVERTED bound to: 1'b0
|
| 88 |
|
|
Parameter REF_JITTER1 bound to: 0.010000 - type: float
|
| 89 |
|
|
Parameter REF_JITTER2 bound to: 0.010000 - type: float
|
| 90 |
|
|
Parameter SS_EN bound to: FALSE - type: string
|
| 91 |
|
|
Parameter SS_MODE bound to: CENTER_HIGH - type: string
|
| 92 |
|
|
Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
|
| 93 |
|
|
Parameter STARTUP_WAIT bound to: FALSE - type: string
|
| 94 |
|
|
INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
|
| 95 |
|
|
INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
|
| 96 |
|
|
INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
|
| 97 |
|
|
INFO: [Synth 8-256] done synthesizing module 'clk_gen_clk_wiz' (4#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v:68]
|
| 98 |
|
|
INFO: [Synth 8-256] done synthesizing module 'clk_gen' (5#1) [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.v:70]
|
| 99 |
|
|
---------------------------------------------------------------------------------
|
| 100 |
|
|
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1316.676 ; gain = 124.531 ; free physical = 1563 ; free virtual = 7744
|
| 101 |
|
|
---------------------------------------------------------------------------------
|
| 102 |
|
|
|
| 103 |
|
|
Report Check Netlist:
|
| 104 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 105 |
|
|
| |Item |Errors |Warnings |Status |Description |
|
| 106 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 107 |
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
| 108 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 109 |
|
|
---------------------------------------------------------------------------------
|
| 110 |
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1316.676 ; gain = 124.531 ; free physical = 1561 ; free virtual = 7742
|
| 111 |
|
|
---------------------------------------------------------------------------------
|
| 112 |
|
|
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
| 113 |
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
| 114 |
|
|
INFO: [Device 21-403] Loading part xc7k325tffg900-2
|
| 115 |
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
| 116 |
|
|
|
| 117 |
|
|
Processing XDC Constraints
|
| 118 |
|
|
Initializing timing engine
|
| 119 |
|
|
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc] for cell 'inst'
|
| 120 |
|
|
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc] for cell 'inst'
|
| 121 |
|
|
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'inst'
|
| 122 |
|
|
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'inst'
|
| 123 |
|
|
Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'inst'
|
| 124 |
|
|
Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'inst'
|
| 125 |
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_gen_propImpl.xdc].
|
| 126 |
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/clk_gen_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
| 127 |
|
|
INFO: [Timing 38-2] Deriving generated clocks
|
| 128 |
|
|
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc]
|
| 129 |
|
|
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc]
|
| 130 |
|
|
Completed Processing XDC Constraints
|
| 131 |
|
|
|
| 132 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
| 133 |
|
|
No Unisim elements were transformed.
|
| 134 |
|
|
|
| 135 |
|
|
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1604.902 ; gain = 0.000 ; free physical = 1018 ; free virtual = 7240
|
| 136 |
|
|
---------------------------------------------------------------------------------
|
| 137 |
|
|
Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1139 ; free virtual = 7362
|
| 138 |
|
|
---------------------------------------------------------------------------------
|
| 139 |
|
|
---------------------------------------------------------------------------------
|
| 140 |
|
|
Start Loading Part and Timing Information
|
| 141 |
|
|
---------------------------------------------------------------------------------
|
| 142 |
|
|
Loading part: xc7k325tffg900-2
|
| 143 |
|
|
---------------------------------------------------------------------------------
|
| 144 |
|
|
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1140 ; free virtual = 7362
|
| 145 |
|
|
---------------------------------------------------------------------------------
|
| 146 |
|
|
---------------------------------------------------------------------------------
|
| 147 |
|
|
Start Applying 'set_property' XDC Constraints
|
| 148 |
|
|
---------------------------------------------------------------------------------
|
| 149 |
|
|
Applied set_property DONT_TOUCH = true for inst. (constraint file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/dont_touch.xdc, line 9).
|
| 150 |
|
|
---------------------------------------------------------------------------------
|
| 151 |
|
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1144 ; free virtual = 7366
|
| 152 |
|
|
---------------------------------------------------------------------------------
|
| 153 |
|
|
---------------------------------------------------------------------------------
|
| 154 |
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1143 ; free virtual = 7365
|
| 155 |
|
|
---------------------------------------------------------------------------------
|
| 156 |
|
|
|
| 157 |
|
|
Report RTL Partitions:
|
| 158 |
|
|
+-+--------------+------------+----------+
|
| 159 |
|
|
| |RTL Partition |Replication |Instances |
|
| 160 |
|
|
+-+--------------+------------+----------+
|
| 161 |
|
|
+-+--------------+------------+----------+
|
| 162 |
|
|
---------------------------------------------------------------------------------
|
| 163 |
|
|
Start RTL Component Statistics
|
| 164 |
|
|
---------------------------------------------------------------------------------
|
| 165 |
|
|
Detailed RTL Component Info :
|
| 166 |
|
|
---------------------------------------------------------------------------------
|
| 167 |
|
|
Finished RTL Component Statistics
|
| 168 |
|
|
---------------------------------------------------------------------------------
|
| 169 |
|
|
---------------------------------------------------------------------------------
|
| 170 |
|
|
Start RTL Hierarchical Component Statistics
|
| 171 |
|
|
---------------------------------------------------------------------------------
|
| 172 |
|
|
Hierarchical RTL Component report
|
| 173 |
|
|
---------------------------------------------------------------------------------
|
| 174 |
|
|
Finished RTL Hierarchical Component Statistics
|
| 175 |
|
|
---------------------------------------------------------------------------------
|
| 176 |
|
|
---------------------------------------------------------------------------------
|
| 177 |
|
|
Start Part Resource Summary
|
| 178 |
|
|
---------------------------------------------------------------------------------
|
| 179 |
|
|
Part Resources:
|
| 180 |
|
|
DSPs: 840 (col length:140)
|
| 181 |
|
|
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
|
| 182 |
|
|
---------------------------------------------------------------------------------
|
| 183 |
|
|
Finished Part Resource Summary
|
| 184 |
|
|
---------------------------------------------------------------------------------
|
| 185 |
|
|
---------------------------------------------------------------------------------
|
| 186 |
|
|
Start Cross Boundary and Area Optimization
|
| 187 |
|
|
---------------------------------------------------------------------------------
|
| 188 |
|
|
---------------------------------------------------------------------------------
|
| 189 |
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1604.902 ; gain = 412.758 ; free physical = 1142 ; free virtual = 7365
|
| 190 |
|
|
---------------------------------------------------------------------------------
|
| 191 |
|
|
|
| 192 |
|
|
Report RTL Partitions:
|
| 193 |
|
|
+-+--------------+------------+----------+
|
| 194 |
|
|
| |RTL Partition |Replication |Instances |
|
| 195 |
|
|
+-+--------------+------------+----------+
|
| 196 |
|
|
+-+--------------+------------+----------+
|
| 197 |
|
|
---------------------------------------------------------------------------------
|
| 198 |
|
|
Start Applying XDC Timing Constraints
|
| 199 |
|
|
---------------------------------------------------------------------------------
|
| 200 |
|
|
---------------------------------------------------------------------------------
|
| 201 |
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1634.902 ; gain = 442.758 ; free physical = 909 ; free virtual = 7140
|
| 202 |
|
|
---------------------------------------------------------------------------------
|
| 203 |
|
|
---------------------------------------------------------------------------------
|
| 204 |
|
|
Start Timing Optimization
|
| 205 |
|
|
---------------------------------------------------------------------------------
|
| 206 |
|
|
---------------------------------------------------------------------------------
|
| 207 |
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1634.902 ; gain = 442.758 ; free physical = 909 ; free virtual = 7140
|
| 208 |
|
|
---------------------------------------------------------------------------------
|
| 209 |
|
|
|
| 210 |
|
|
Report RTL Partitions:
|
| 211 |
|
|
+-+--------------+------------+----------+
|
| 212 |
|
|
| |RTL Partition |Replication |Instances |
|
| 213 |
|
|
+-+--------------+------------+----------+
|
| 214 |
|
|
+-+--------------+------------+----------+
|
| 215 |
|
|
---------------------------------------------------------------------------------
|
| 216 |
|
|
Start Technology Mapping
|
| 217 |
|
|
---------------------------------------------------------------------------------
|
| 218 |
|
|
---------------------------------------------------------------------------------
|
| 219 |
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 909 ; free virtual = 7140
|
| 220 |
|
|
---------------------------------------------------------------------------------
|
| 221 |
|
|
|
| 222 |
|
|
Report RTL Partitions:
|
| 223 |
|
|
+-+--------------+------------+----------+
|
| 224 |
|
|
| |RTL Partition |Replication |Instances |
|
| 225 |
|
|
+-+--------------+------------+----------+
|
| 226 |
|
|
+-+--------------+------------+----------+
|
| 227 |
|
|
---------------------------------------------------------------------------------
|
| 228 |
|
|
Start IO Insertion
|
| 229 |
|
|
---------------------------------------------------------------------------------
|
| 230 |
|
|
---------------------------------------------------------------------------------
|
| 231 |
|
|
Start Flattening Before IO Insertion
|
| 232 |
|
|
---------------------------------------------------------------------------------
|
| 233 |
|
|
---------------------------------------------------------------------------------
|
| 234 |
|
|
Finished Flattening Before IO Insertion
|
| 235 |
|
|
---------------------------------------------------------------------------------
|
| 236 |
|
|
---------------------------------------------------------------------------------
|
| 237 |
|
|
Start Final Netlist Cleanup
|
| 238 |
|
|
---------------------------------------------------------------------------------
|
| 239 |
|
|
---------------------------------------------------------------------------------
|
| 240 |
|
|
Finished Final Netlist Cleanup
|
| 241 |
|
|
---------------------------------------------------------------------------------
|
| 242 |
|
|
---------------------------------------------------------------------------------
|
| 243 |
|
|
Finished IO Insertion : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 244 |
|
|
---------------------------------------------------------------------------------
|
| 245 |
|
|
|
| 246 |
|
|
Report Check Netlist:
|
| 247 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 248 |
|
|
| |Item |Errors |Warnings |Status |Description |
|
| 249 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 250 |
|
|
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
| 251 |
|
|
+------+------------------+-------+---------+-------+------------------+
|
| 252 |
|
|
---------------------------------------------------------------------------------
|
| 253 |
|
|
Start Renaming Generated Instances
|
| 254 |
|
|
---------------------------------------------------------------------------------
|
| 255 |
|
|
---------------------------------------------------------------------------------
|
| 256 |
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 257 |
|
|
---------------------------------------------------------------------------------
|
| 258 |
|
|
|
| 259 |
|
|
Report RTL Partitions:
|
| 260 |
|
|
+-+--------------+------------+----------+
|
| 261 |
|
|
| |RTL Partition |Replication |Instances |
|
| 262 |
|
|
+-+--------------+------------+----------+
|
| 263 |
|
|
+-+--------------+------------+----------+
|
| 264 |
|
|
---------------------------------------------------------------------------------
|
| 265 |
|
|
Start Rebuilding User Hierarchy
|
| 266 |
|
|
---------------------------------------------------------------------------------
|
| 267 |
|
|
---------------------------------------------------------------------------------
|
| 268 |
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 269 |
|
|
---------------------------------------------------------------------------------
|
| 270 |
|
|
---------------------------------------------------------------------------------
|
| 271 |
|
|
Start Renaming Generated Ports
|
| 272 |
|
|
---------------------------------------------------------------------------------
|
| 273 |
|
|
---------------------------------------------------------------------------------
|
| 274 |
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 275 |
|
|
---------------------------------------------------------------------------------
|
| 276 |
|
|
---------------------------------------------------------------------------------
|
| 277 |
|
|
Start Handling Custom Attributes
|
| 278 |
|
|
---------------------------------------------------------------------------------
|
| 279 |
|
|
---------------------------------------------------------------------------------
|
| 280 |
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 281 |
|
|
---------------------------------------------------------------------------------
|
| 282 |
|
|
---------------------------------------------------------------------------------
|
| 283 |
|
|
Start Renaming Generated Nets
|
| 284 |
|
|
---------------------------------------------------------------------------------
|
| 285 |
|
|
---------------------------------------------------------------------------------
|
| 286 |
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 287 |
|
|
---------------------------------------------------------------------------------
|
| 288 |
|
|
---------------------------------------------------------------------------------
|
| 289 |
|
|
Start Writing Synthesis Report
|
| 290 |
|
|
---------------------------------------------------------------------------------
|
| 291 |
|
|
|
| 292 |
|
|
Report BlackBoxes:
|
| 293 |
|
|
+-+--------------+----------+
|
| 294 |
|
|
| |BlackBox name |Instances |
|
| 295 |
|
|
+-+--------------+----------+
|
| 296 |
|
|
+-+--------------+----------+
|
| 297 |
|
|
|
| 298 |
|
|
Report Cell Usage:
|
| 299 |
|
|
+------+-----------+------+
|
| 300 |
|
|
| |Cell |Count |
|
| 301 |
|
|
+------+-----------+------+
|
| 302 |
|
|
|1 |BUFG | 2|
|
| 303 |
|
|
|2 |MMCME2_ADV | 1|
|
| 304 |
|
|
|3 |IBUFDS | 1|
|
| 305 |
|
|
+------+-----------+------+
|
| 306 |
|
|
|
| 307 |
|
|
Report Instance Areas:
|
| 308 |
|
|
+------+---------+----------------+------+
|
| 309 |
|
|
| |Instance |Module |Cells |
|
| 310 |
|
|
+------+---------+----------------+------+
|
| 311 |
|
|
|1 |top | | 4|
|
| 312 |
|
|
|2 | inst |clk_gen_clk_wiz | 4|
|
| 313 |
|
|
+------+---------+----------------+------+
|
| 314 |
|
|
---------------------------------------------------------------------------------
|
| 315 |
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.918 ; gain = 452.773 ; free physical = 871 ; free virtual = 7103
|
| 316 |
|
|
---------------------------------------------------------------------------------
|
| 317 |
|
|
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
| 318 |
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1644.918 ; gain = 164.547 ; free physical = 919 ; free virtual = 7150
|
| 319 |
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1644.926 ; gain = 452.773 ; free physical = 918 ; free virtual = 7150
|
| 320 |
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
| 321 |
|
|
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
| 322 |
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
| 323 |
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
| 324 |
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
| 325 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
| 326 |
|
|
No Unisim elements were transformed.
|
| 327 |
|
|
|
| 328 |
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
| 329 |
|
|
25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
| 330 |
|
|
synth_design completed successfully
|
| 331 |
|
|
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:46 . Memory (MB): peak = 1654.918 ; gain = 489.875 ; free physical = 879 ; free virtual = 7111
|
| 332 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen.dcp' has been generated.
|
| 333 |
|
|
INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xci
|
| 334 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/clk_gen_synth_1/clk_gen.dcp' has been generated.
|
| 335 |
|
|
INFO: [runtcl-4] Executing : report_utilization -file clk_gen_utilization_synth.rpt -pb clk_gen_utilization_synth.pb
|
| 336 |
|
|
report_utilization: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1658.918 ; gain = 0.000 ; free physical = 926 ; free virtual = 7158
|
| 337 |
|
|
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:02:25 2020...
|
