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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [impl_1/] [aes128_ecb_fpga_wrap_clock_utilization_routed.rpt] - Blame information for rev 2

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1 2 vv_gulyaev 
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
2 
--------------------------------------------------------------------------------------------------
3 
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
4 
| Date         : Thu Jul 30 13:56:20 2020
5 
| Host         : orme22 running 64-bit Ubuntu 18.04.4 LTS
6 
| Command      : report_clock_utilization -file aes128_ecb_fpga_wrap_clock_utilization_routed.rpt
7 
| Design       : aes128_ecb_fpga_wrap
8 
| Device       : 7k325t-ffg900
9 
| Speed File   : -2  PRODUCTION 1.12 2017-02-17
10 
--------------------------------------------------------------------------------------------------
11 
 
12 
Clock Utilization Report
13 
 
14 
Table of Contents
15 
-----------------
16 
1. Clock Primitive Utilization
17 
2. Global Clock Resources
18 
3. Global Clock Source Details
19 
4. Clock Regions: Key Resource Utilization
20 
5. Clock Regions : Global Clock Summary
21 
6. Device Cell Placement Summary for Global Clock g0
22 
7. Device Cell Placement Summary for Global Clock g1
23 
8. Clock Region Cell Placement per Global Clock: Region X0Y1
24 
9. Clock Region Cell Placement per Global Clock: Region X1Y1
25 
10. Clock Region Cell Placement per Global Clock: Region X0Y4
26 
11. Clock Region Cell Placement per Global Clock: Region X0Y5
27 
 
28 
1. Clock Primitive Utilization
29 
------------------------------
30 
 
31 
+----------+------+-----------+-----+--------------+--------+
32 
| Type     | Used | Available | LOC | Clock Region | Pblock |
33 
+----------+------+-----------+-----+--------------+--------+
34 
| BUFGCTRL |    2 |        32 |   0 |            0 |      0 |
35 
| BUFH     |    0 |       168 |   0 |            0 |      0 |
36 
| BUFIO    |    0 |        40 |   0 |            0 |      0 |
37 
| BUFMR    |    0 |        20 |   0 |            0 |      0 |
38 
| BUFR     |    0 |        40 |   0 |            0 |      0 |
39 
| MMCM     |    1 |        10 |   0 |            0 |      0 |
40 
| PLL      |    0 |        10 |   0 |            0 |      0 |
41 
+----------+------+-----------+-----+--------------+--------+
42 
 
43 
 
44 
2. Global Clock Resources
45 
-------------------------
46 
 
47 
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+---------------------------+----------------------------------+
48 
| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock            | Driver Pin                | Net                              |
49 
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+---------------------------+----------------------------------+
50 
| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |                 3 |         982 |               0 |       10.000 | clk_out1_clk_gen | clkgen/inst/clkout1_buf/O | clkgen/inst/clk_out1             |
51 
| g1        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y1 | n/a          |                 1 |           1 |               0 |        5.000 | clkfbout_clk_gen | clkgen/inst/clkf_buf/O    | clkgen/inst/clkfbout_buf_clk_gen |
52 
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+---------------------------+----------------------------------+
53 
* Clock Loads column represents the clock pin loads (pin count)
54 
** Non-Clock Loads column represents the non-clock pin loads (pin count)
55 
 
56 
 
57 
3. Global Clock Source Details
58 
------------------------------
59 
 
60 
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------------------+------------------------------+
61 
| Source Id | Global Id | Driver Type/Pin     | Constraint | Site            | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock     | Driver Pin                         | Net                          |
62 
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------------------+------------------------------+
63 
| src0      | g0        | MMCME2_ADV/CLKOUT0  | None       | MMCME2_ADV_X1Y1 | X1Y1         |           1 |               0 |              10.000 | clk_out1_clk_gen | clkgen/inst/mmcm_adv_inst/CLKOUT0  | clkgen/inst/clk_out1_clk_gen |
64 
| src0      | g1        | MMCME2_ADV/CLKFBOUT | None       | MMCME2_ADV_X1Y1 | X1Y1         |           1 |               0 |               5.000 | clkfbout_clk_gen | clkgen/inst/mmcm_adv_inst/CLKFBOUT | clkgen/inst/clkfbout_clk_gen |
65 
+-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------------------+------------------------------+
66 
* Clock Loads column represents the clock pin loads (pin count)
67 
** Non-Clock Loads column represents the non-clock pin loads (pin count)
68 
 
69 
 
70 
4. Clock Regions: Key Resource Utilization
71 
------------------------------------------
72 
 
73 
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
74 
|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
75 
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
76 
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
77 
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
78 
| X0Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4000 |    0 |  1150 |    0 |    60 |    0 |    30 |    0 |    60 |
79 
| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  3700 |    0 |  1200 |    0 |    80 |    0 |    40 |    0 |    60 |
80 
| X0Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    2 |  4000 |    0 |  1150 |    0 |    60 |    0 |    30 |    0 |    60 |
81 
| X1Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  3700 |    0 |  1200 |    0 |    80 |    0 |    40 |    0 |    60 |
82 
| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  3400 |    0 |  1150 |    0 |    60 |    0 |    30 |    0 |    60 |
83 
| X1Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  3700 |    0 |  1200 |    0 |    80 |    0 |    40 |    0 |    60 |
84 
| X0Y3              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  3400 |    0 |  1150 |    0 |    60 |    0 |    30 |    0 |    60 |
85 
| X1Y3              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |  3150 |    0 |  1050 |    0 |    50 |    0 |    25 |    0 |    60 |
86 
| X0Y4              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  614 |  4000 |   80 |  1150 |    0 |    60 |    0 |    30 |    0 |    60 |
87 
| X1Y4              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |  3300 |    0 |  1100 |    0 |    60 |    0 |    30 |    0 |    60 |
88 
| X0Y5              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  348 |  4000 |   43 |  1150 |    0 |    60 |    0 |    30 |    0 |    60 |
89 
| X1Y5              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |  3300 |    0 |  1100 |    0 |    60 |    0 |    30 |    0 |    60 |
90 
| X0Y6              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4000 |    0 |  1150 |    0 |    60 |    0 |    30 |    0 |    60 |
91 
| X1Y6              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |  3300 |    0 |  1100 |    0 |    60 |    0 |    30 |    0 |    60 |
92 
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
93 
* Global Clock column represents track count; while other columns represents cell counts
94 
 
95 
 
96 
5. Clock Regions : Global Clock Summary
97 
---------------------------------------
98 
 
99 
All Modules
100 
+----+----+----+
101 
|    | X0 | X1 |
102 
+----+----+----+
103 
| Y6 |  0 |  0 |
104 
| Y5 |  1 |  0 |
105 
| Y4 |  1 |  0 |
106 
| Y3 |  0 |  0 |
107 
| Y2 |  0 |  0 |
108 
| Y1 |  1 |  1 |
109 
| Y0 |  0 |  0 |
110 
+----+----+----+
111 
 
112 
 
113 
6. Device Cell Placement Summary for Global Clock g0
114 
----------------------------------------------------
115 
 
116 
+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
117 
| Global Id | Driver Type/Pin | Driver Region (D) | Clock            | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                  |
118 
+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
119 
| g0        | BUFG/O          | n/a               | clk_out1_clk_gen |      10.000 | {0.000 5.000} |         982 |        0 |              0 |        0 | clkgen/inst/clk_out1 |
120 
+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------+
121 
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
122 
** IO Loads column represents load cell count of IO types
123 
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
124 
**** GT Loads column represents load cell count of GT types
125 
 
126 
 
127 
+----+------+----+
128 
|    | X0   | X1 |
129 
+----+------+----+
130 
| Y6 |    0 |  0 |
131 
| Y5 |  348 |  0 |
132 
| Y4 |  632 |  0 |
133 
| Y3 |    0 |  0 |
134 
| Y2 |    0 |  0 |
135 
| Y1 |    2 |  0 |
136 
| Y0 |    0 |  0 |
137 
+----+------+----+
138 
 
139 
 
140 
7. Device Cell Placement Summary for Global Clock g1
141 
----------------------------------------------------
142 
 
143 
+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------+
144 
| Global Id | Driver Type/Pin | Driver Region (D) | Clock            | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                              |
145 
+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------+
146 
| g1        | BUFG/O          | n/a               | clkfbout_clk_gen |       5.000 | {0.000 2.500} |           0 |        0 |              1 |        0 | clkgen/inst/clkfbout_buf_clk_gen |
147 
+-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------+
148 
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
149 
** IO Loads column represents load cell count of IO types
150 
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
151 
**** GT Loads column represents load cell count of GT types
152 
 
153 
 
154 
+----+----+----+
155 
|    | X0 | X1 |
156 
+----+----+----+
157 
| Y6 |  0 |  0 |
158 
| Y5 |  0 |  0 |
159 
| Y4 |  0 |  0 |
160 
| Y3 |  0 |  0 |
161 
| Y2 |  0 |  0 |
162 
| Y1 |  0 |  1 |
163 
| Y0 |  0 |  0 |
164 
+----+----+----+
165 
 
166 
 
167 
8. Clock Region Cell Placement per Global Clock: Region X0Y1
168 
------------------------------------------------------------
169 
 
170 
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+
171 
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                  |
172 
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+
173 
| g0        | n/a   | BUFG/O          | None       |           2 |               0 |  2 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | clkgen/inst/clk_out1 |
174 
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------+
175 
* Clock Loads column represents the clock pin loads (pin count)
176 
** Non-Clock Loads column represents the non-clock pin loads (pin count)
177 
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
178 
 
179 
 
180 
9. Clock Region Cell Placement per Global Clock: Region X1Y1
181 
------------------------------------------------------------
182 
 
183 
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------+
184 
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                              |
185 
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------+
186 
| g1        | n/a   | BUFG/O          | None       |           1 |               0 |  0 |      0 |    0 |   0 |  0 |    1 |   0 |       0 | clkgen/inst/clkfbout_buf_clk_gen |
187 
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------+
188 
* Clock Loads column represents the clock pin loads (pin count)
189 
** Non-Clock Loads column represents the non-clock pin loads (pin count)
190 
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
191 
 
192 
 
193 
10. Clock Region Cell Placement per Global Clock: Region X0Y4
194 
-------------------------------------------------------------
195 
 
196 
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+
197 
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                  |
198 
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+
199 
| g0        | n/a   | BUFG/O          | None       |         632 |               0 | 614 |     18 |    0 |   0 |  0 |    0 |   0 |       0 | clkgen/inst/clk_out1 |
200 
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+
201 
* Clock Loads column represents the clock pin loads (pin count)
202 
** Non-Clock Loads column represents the non-clock pin loads (pin count)
203 
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
204 
 
205 
 
206 
11. Clock Region Cell Placement per Global Clock: Region X0Y5
207 
-------------------------------------------------------------
208 
 
209 
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+
210 
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                  |
211 
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+
212 
| g0        | n/a   | BUFG/O          | None       |         348 |               0 | 348 |      0 |    0 |   0 |  0 |    0 |   0 |       0 | clkgen/inst/clk_out1 |
213 
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------+
214 
* Clock Loads column represents the clock pin loads (pin count)
215 
** Non-Clock Loads column represents the non-clock pin loads (pin count)
216 
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
217 
 
218 
 
219 
 
220 
# Location of BUFG Primitives
221 
set_property LOC BUFGCTRL_X0Y1 [get_cells clkgen/inst/clkf_buf]
222 
set_property LOC BUFGCTRL_X0Y0 [get_cells clkgen/inst/clkout1_buf]
223 
 
224 
# Location of IO Primitives which is load of clock spine
225 
 
226 
# Location of clock ports
227 
set_property LOC IOB_X1Y75 [get_ports CLK_IN_N]
228 
set_property LOC IOB_X1Y76 [get_ports CLK_IN_P]
229 
 
230 
# Clock net "clkgen/inst/clk_out1" driven by instance "clkgen/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0"
231 
#startgroup
232 
create_pblock {CLKAG_clkgen/inst/clk_out1}
233 
add_cells_to_pblock [get_pblocks  {CLKAG_clkgen/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkgen/inst/clk_out1"}]]]
234 
resize_pblock [get_pblocks {CLKAG_clkgen/inst/clk_out1}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5}
235 
#endgroup

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