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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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| Date : Thu Jul 30 13:56:10 2020
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| Host : orme22 running 64-bit Ubuntu 18.04.4 LTS
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| Command : report_drc -file aes128_ecb_fpga_wrap_drc_routed.rpt -pb aes128_ecb_fpga_wrap_drc_routed.pb -rpx aes128_ecb_fpga_wrap_drc_routed.rpx
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| Design : aes128_ecb_fpga_wrap
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| Device : xc7k325tffg900-2
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| Speed File : -2
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| Design State : Routed
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits:
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Ruledeck: default
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Max violations:
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Violations found: 6
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+------------+----------+--------------------+------------+
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| Rule | Severity | Description | Violations |
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+------------+----------+--------------------+------------+
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| PDRC-153 | Warning | Gated clock check | 4 |
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| PORTPROP-2 | Warning | selectio_diff_term | 2 |
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+------------+----------+--------------------+------------+
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2. REPORT DETAILS
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-----------------
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PDRC-153#1 Warning
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Gated clock check
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Net sys_mngr/axi_state[0]_P_i_3_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[0]_P_i_3/O, cell sys_mngr/axi_state[0]_P_i_3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
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Related violations:
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PDRC-153#2 Warning
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Gated clock check
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Net sys_mngr/axi_state[10]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[10]_P_i_2/O, cell sys_mngr/axi_state[10]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
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Related violations:
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PDRC-153#3 Warning
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Gated clock check
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Net sys_mngr/axi_state[1]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[1]_P_i_2/O, cell sys_mngr/axi_state[1]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
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Related violations:
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PDRC-153#4 Warning
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Gated clock check
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Net sys_mngr/axi_state[2]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[2]_P_i_2/O, cell sys_mngr/axi_state[2]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
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Related violations:
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PORTPROP-2#1 Warning
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selectio_diff_term
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The port CLK_IN_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
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Related violations:
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PORTPROP-2#2 Warning
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selectio_diff_term
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The port CLK_IN_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
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Related violations:
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