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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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| Date : Thu Jul 30 13:56:11 2020
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| Host : orme22 running 64-bit Ubuntu 18.04.4 LTS
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| Command : report_methodology -file aes128_ecb_fpga_wrap_methodology_drc_routed.rpt -pb aes128_ecb_fpga_wrap_methodology_drc_routed.pb -rpx aes128_ecb_fpga_wrap_methodology_drc_routed.rpx
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| Design : aes128_ecb_fpga_wrap
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| Device : xc7k325tffg900-2
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| Speed File : -2
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| Design State : Routed
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Report Methodology
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits:
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Max violations:
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Violations found: 7
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+-----------+----------+-------------------------------------------------------------+------------+
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| Rule | Severity | Description | Violations |
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+-----------+----------+-------------------------------------------------------------+------------+
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| TIMING-20 | Warning | Non-clocked latch | 4 |
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| TIMING-30 | Warning | Sub-optimal master source pin selection for generated clock | 1 |
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| XDCH-2 | Warning | Same min and max delay values on IO port | 2 |
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+-----------+----------+-------------------------------------------------------------+------------+
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2. REPORT DETAILS
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-----------------
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TIMING-20#1 Warning
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Non-clocked latch
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The latch sys_mngr/axi_state_reg[0]_LDC cannot be properly analyzed as its control pin sys_mngr/axi_state_reg[0]_LDC/G is not reached by a timing clock
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Related violations:
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TIMING-20#2 Warning
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Non-clocked latch
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The latch sys_mngr/axi_state_reg[10]_LDC cannot be properly analyzed as its control pin sys_mngr/axi_state_reg[10]_LDC/G is not reached by a timing clock
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Related violations:
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TIMING-20#3 Warning
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Non-clocked latch
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The latch sys_mngr/axi_state_reg[1]_LDC cannot be properly analyzed as its control pin sys_mngr/axi_state_reg[1]_LDC/G is not reached by a timing clock
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Related violations:
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TIMING-20#4 Warning
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Non-clocked latch
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The latch sys_mngr/axi_state_reg[2]_LDC cannot be properly analyzed as its control pin sys_mngr/axi_state_reg[2]_LDC/G is not reached by a timing clock
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Related violations:
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TIMING-30#1 Warning
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Sub-optimal master source pin selection for generated clock
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The generated clock clk_gen has a sub-optimal master source pin selection, timing can be pessimistic
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Related violations:
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XDCH-2#1 Warning
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Same min and max delay values on IO port
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The same input delay of 1.000 ns has been defined on port 'uart_rx' relative to clock clk_gen for both max and min. Make sure this reflects the design intent.
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set_input_delay -clock [get_clocks clk_gen] 1.000 [get_ports uart_rx]
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/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc (Line: 13)
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Related violations:
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XDCH-2#2 Warning
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Same min and max delay values on IO port
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The same output delay of 1.000 ns has been defined on port 'uart_tx' relative to clock clk_gen for both max and min. Make sure this reflects the design intent.
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set_output_delay -clock [get_clocks clk_gen] 1.000 [get_ports uart_tx]
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/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc (Line: 14)
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Related violations:
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