| 1 |
2 |
vv_gulyaev |
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
| 2 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 3 |
|
|
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
|
| 4 |
|
|
| Date : Thu Jul 30 13:56:15 2020
|
| 5 |
|
|
| Host : orme22 running 64-bit Ubuntu 18.04.4 LTS
|
| 6 |
|
|
| Command : report_power -file aes128_ecb_fpga_wrap_power_routed.rpt -pb aes128_ecb_fpga_wrap_power_summary_routed.pb -rpx aes128_ecb_fpga_wrap_power_routed.rpx
|
| 7 |
|
|
| Design : aes128_ecb_fpga_wrap
|
| 8 |
|
|
| Device : xc7k325tffg900-2
|
| 9 |
|
|
| Design State : routed
|
| 10 |
|
|
| Grade : commercial
|
| 11 |
|
|
| Process : typical
|
| 12 |
|
|
| Characterization : Production
|
| 13 |
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 14 |
|
|
|
| 15 |
|
|
Power Report
|
| 16 |
|
|
|
| 17 |
|
|
Table of Contents
|
| 18 |
|
|
-----------------
|
| 19 |
|
|
1. Summary
|
| 20 |
|
|
1.1 On-Chip Components
|
| 21 |
|
|
1.2 Power Supply Summary
|
| 22 |
|
|
1.3 Confidence Level
|
| 23 |
|
|
2. Settings
|
| 24 |
|
|
2.1 Environment
|
| 25 |
|
|
2.2 Clock Constraints
|
| 26 |
|
|
3. Detailed Reports
|
| 27 |
|
|
3.1 By Hierarchy
|
| 28 |
|
|
|
| 29 |
|
|
1. Summary
|
| 30 |
|
|
----------
|
| 31 |
|
|
|
| 32 |
|
|
+--------------------------+--------------+
|
| 33 |
|
|
| Total On-Chip Power (W) | 0.319 |
|
| 34 |
|
|
| Design Power Budget (W) | Unspecified* |
|
| 35 |
|
|
| Power Budget Margin (W) | NA |
|
| 36 |
|
|
| Dynamic (W) | 0.158 |
|
| 37 |
|
|
| Device Static (W) | 0.161 |
|
| 38 |
|
|
| Effective TJA (C/W) | 1.8 |
|
| 39 |
|
|
| Max Ambient (C) | 84.4 |
|
| 40 |
|
|
| Junction Temperature (C) | 25.6 |
|
| 41 |
|
|
| Confidence Level | Medium |
|
| 42 |
|
|
| Setting File | --- |
|
| 43 |
|
|
| Simulation Activity File | --- |
|
| 44 |
|
|
| Design Nets Matched | NA |
|
| 45 |
|
|
+--------------------------+--------------+
|
| 46 |
|
|
* Specify Design Power Budget using, set_operating_conditions -design_power_budget
|
| 47 |
|
|
|
| 48 |
|
|
|
| 49 |
|
|
1.1 On-Chip Components
|
| 50 |
|
|
----------------------
|
| 51 |
|
|
|
| 52 |
|
|
+-------------------------+-----------+----------+-----------+-----------------+
|
| 53 |
|
|
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
| 54 |
|
|
+-------------------------+-----------+----------+-----------+-----------------+
|
| 55 |
|
|
| Clocks | 0.010 | 6 | --- | --- |
|
| 56 |
|
|
| Slice Logic | 0.018 | 5086 | --- | --- |
|
| 57 |
|
|
| LUT as Logic | 0.017 | 2820 | 203800 | 1.38 |
|
| 58 |
|
|
| F7/F8 Muxes | <0.001 | 907 | 203800 | 0.45 |
|
| 59 |
|
|
| Register | <0.001 | 968 | 407600 | 0.24 |
|
| 60 |
|
|
| CARRY4 | <0.001 | 8 | 50950 | 0.02 |
|
| 61 |
|
|
| LUT as Shift Register | <0.001 | 10 | 64000 | 0.02 |
|
| 62 |
|
|
| Others | 0.000 | 27 | --- | --- |
|
| 63 |
|
|
| Signals | 0.018 | 2485 | --- | --- |
|
| 64 |
|
|
| MMCM | 0.107 | 1 | 10 | 10.00 |
|
| 65 |
|
|
| I/O | 0.006 | 9 | 500 | 1.80 |
|
| 66 |
|
|
| Static Power | 0.161 | | | |
|
| 67 |
|
|
| Total | 0.319 | | | |
|
| 68 |
|
|
+-------------------------+-----------+----------+-----------+-----------------+
|
| 69 |
|
|
|
| 70 |
|
|
|
| 71 |
|
|
1.2 Power Supply Summary
|
| 72 |
|
|
------------------------
|
| 73 |
|
|
|
| 74 |
|
|
+-----------+-------------+-----------+-------------+------------+
|
| 75 |
|
|
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
|
| 76 |
|
|
+-----------+-------------+-----------+-------------+------------+
|
| 77 |
|
|
| Vccint | 1.000 | 0.116 | 0.047 | 0.069 |
|
| 78 |
|
|
| Vccaux | 1.800 | 0.089 | 0.061 | 0.028 |
|
| 79 |
|
|
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
|
| 80 |
|
|
| Vcco25 | 2.500 | 0.002 | 0.001 | 0.001 |
|
| 81 |
|
|
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
|
| 82 |
|
|
| Vcco15 | 1.500 | 0.001 | 0.000 | 0.001 |
|
| 83 |
|
|
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
|
| 84 |
|
|
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
|
| 85 |
|
|
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 |
|
| 86 |
|
|
| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 |
|
| 87 |
|
|
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 |
|
| 88 |
|
|
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
|
| 89 |
|
|
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
|
| 90 |
|
|
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 |
|
| 91 |
|
|
+-----------+-------------+-----------+-------------+------------+
|
| 92 |
|
|
|
| 93 |
|
|
|
| 94 |
|
|
1.3 Confidence Level
|
| 95 |
|
|
--------------------
|
| 96 |
|
|
|
| 97 |
|
|
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
| 98 |
|
|
| User Input Data | Confidence | Details | Action |
|
| 99 |
|
|
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
| 100 |
|
|
| Design implementation state | High | Design is routed | |
|
| 101 |
|
|
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
| 102 |
|
|
| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
| 103 |
|
|
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
| 104 |
|
|
| Device models | High | Device models are Production | |
|
| 105 |
|
|
| | | | |
|
| 106 |
|
|
| Overall confidence level | Medium | | |
|
| 107 |
|
|
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
| 108 |
|
|
|
| 109 |
|
|
|
| 110 |
|
|
2. Settings
|
| 111 |
|
|
-----------
|
| 112 |
|
|
|
| 113 |
|
|
2.1 Environment
|
| 114 |
|
|
---------------
|
| 115 |
|
|
|
| 116 |
|
|
+-----------------------+--------------------------+
|
| 117 |
|
|
| Ambient Temp (C) | 25.0 |
|
| 118 |
|
|
| ThetaJA (C/W) | 1.8 |
|
| 119 |
|
|
| Airflow (LFM) | 250 |
|
| 120 |
|
|
| Heat Sink | medium (Medium Profile) |
|
| 121 |
|
|
| ThetaSA (C/W) | 3.3 |
|
| 122 |
|
|
| Board Selection | medium (10"x10") |
|
| 123 |
|
|
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
| 124 |
|
|
| Board Temperature (C) | 25.0 |
|
| 125 |
|
|
+-----------------------+--------------------------+
|
| 126 |
|
|
|
| 127 |
|
|
|
| 128 |
|
|
2.2 Clock Constraints
|
| 129 |
|
|
---------------------
|
| 130 |
|
|
|
| 131 |
|
|
+------------------+------------------------------+-----------------+
|
| 132 |
|
|
| Clock | Domain | Constraint (ns) |
|
| 133 |
|
|
+------------------+------------------------------+-----------------+
|
| 134 |
|
|
| CLK_IN_P | CLK_IN_P | 5.0 |
|
| 135 |
|
|
| clk_out1_clk_gen | clkgen/inst/clk_out1 | 10.0 |
|
| 136 |
|
|
| clk_out1_clk_gen | clkgen/inst/clk_out1_clk_gen | 10.0 |
|
| 137 |
|
|
| clkfbout_clk_gen | clkgen/inst/clkfbout_clk_gen | 5.0 |
|
| 138 |
|
|
+------------------+------------------------------+-----------------+
|
| 139 |
|
|
|
| 140 |
|
|
|
| 141 |
|
|
3. Detailed Reports
|
| 142 |
|
|
-------------------
|
| 143 |
|
|
|
| 144 |
|
|
3.1 By Hierarchy
|
| 145 |
|
|
----------------
|
| 146 |
|
|
|
| 147 |
|
|
+---------------------------------------------------------------------------+-----------+
|
| 148 |
|
|
| Name | Power (W) |
|
| 149 |
|
|
+---------------------------------------------------------------------------+-----------+
|
| 150 |
|
|
| aes128_ecb_fpga_wrap | 0.158 |
|
| 151 |
|
|
| clkgen | 0.113 |
|
| 152 |
|
|
| inst | 0.113 |
|
| 153 |
|
|
| enc | 0.036 |
|
| 154 |
|
|
| sys_mngr | 0.007 |
|
| 155 |
|
|
| uartlite | 0.001 |
|
| 156 |
|
|
| U0 | 0.001 |
|
| 157 |
|
|
| AXI_LITE_IPIF_I | <0.001 |
|
| 158 |
|
|
| I_SLAVE_ATTACHMENT | <0.001 |
|
| 159 |
|
|
| I_DECODER | <0.001 |
|
| 160 |
|
|
| MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I | <0.001 |
|
| 161 |
|
|
| MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I | <0.001 |
|
| 162 |
|
|
| UARTLITE_CORE_I | <0.001 |
|
| 163 |
|
|
| BAUD_RATE_I | <0.001 |
|
| 164 |
|
|
| UARTLITE_RX_I | <0.001 |
|
| 165 |
|
|
| DELAY_16_I | <0.001 |
|
| 166 |
|
|
| INPUT_DOUBLE_REGS3 | <0.001 |
|
| 167 |
|
|
| SRL_FIFO_I | <0.001 |
|
| 168 |
|
|
| I_SRL_FIFO_RBU_F | <0.001 |
|
| 169 |
|
|
| CNTR_INCR_DECR_ADDN_F_I | <0.001 |
|
| 170 |
|
|
| DYNSHREG_F_I | <0.001 |
|
| 171 |
|
|
| UARTLITE_TX_I | <0.001 |
|
| 172 |
|
|
| MID_START_BIT_SRL16_I | <0.001 |
|
| 173 |
|
|
| SRL_FIFO_I | <0.001 |
|
| 174 |
|
|
| I_SRL_FIFO_RBU_F | <0.001 |
|
| 175 |
|
|
| CNTR_INCR_DECR_ADDN_F_I | <0.001 |
|
| 176 |
|
|
| DYNSHREG_F_I | <0.001 |
|
| 177 |
|
|
+---------------------------------------------------------------------------+-----------+
|
| 178 |
|
|
|
| 179 |
|
|
|
