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vv_gulyaev |
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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| Date : Thu Jul 30 13:56:15 2020
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| Host : orme22 running 64-bit Ubuntu 18.04.4 LTS
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| Command : report_timing_summary -max_paths 10 -file aes128_ecb_fpga_wrap_timing_summary_routed.rpt -rpx aes128_ecb_fpga_wrap_timing_summary_routed.rpx -warn_on_violation
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| Design : aes128_ecb_fpga_wrap
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| Device : 7k325t-ffg900
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| Speed File : -2 PRODUCTION 1.12 2017-02-17
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : false
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock
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2. checking constant_clock
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3. checking pulse_width_clock
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4. checking unconstrained_internal_endpoints
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5. checking no_input_delay
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6. checking no_output_delay
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7. checking multiple_clock
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8. checking generated_clocks
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9. checking loops
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10. checking partial_input_delay
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11. checking partial_output_delay
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12. checking latch_loops
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1. checking no_clock
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--------------------
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There are 4 register/latch pins with no clock driven by root clock pin: rst_i (HIGH)
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There are 4 register/latch pins with no clock driven by root clock pin: clkgen/inst/mmcm_adv_inst/LOCKED (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: sys_mngr/axi_state_reg[0]_C/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: sys_mngr/axi_state_reg[0]_LDC/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: sys_mngr/axi_state_reg[0]_P/Q (HIGH)
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There are 2 register/latch pins with no clock driven by root clock pin: sys_mngr/axi_state_reg[10]_C/Q (HIGH)
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There are 2 register/latch pins with no clock driven by root clock pin: sys_mngr/axi_state_reg[10]_P/Q (HIGH)
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There are 3 register/latch pins with no clock driven by root clock pin: sys_mngr/axi_state_reg[1]_C/Q (HIGH)
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There are 3 register/latch pins with no clock driven by root clock pin: sys_mngr/axi_state_reg[1]_LDC/Q (HIGH)
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There are 3 register/latch pins with no clock driven by root clock pin: sys_mngr/axi_state_reg[1]_P/Q (HIGH)
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There are 2 register/latch pins with no clock driven by root clock pin: sys_mngr/axi_state_reg[2]_C/Q (HIGH)
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There are 2 register/latch pins with no clock driven by root clock pin: sys_mngr/axi_state_reg[2]_LDC/Q (HIGH)
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There are 2 register/latch pins with no clock driven by root clock pin: sys_mngr/axi_state_reg[2]_P/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]/Q (HIGH)
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There is 1 register/latch pin with no clock driven by root clock pin: uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]/Q (HIGH)
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2. checking constant_clock
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--------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock
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-----------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints
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--------------------------------------------
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There are 4 pins that are not constrained for maximum delay. (HIGH)
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There are 0 pins that are not constrained for maximum delay due to constant clock.
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5. checking no_input_delay
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--------------------------
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There is 1 input port with no input delay specified. (HIGH)
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay
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---------------------------
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There are 3 ports with no output delay specified. (HIGH)
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There are 0 ports with no output delay but user has a false path constraint
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock
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--------------------------
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There are 0 register/latch pins with multiple clocks.
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8. checking generated_clocks
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----------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops
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-----------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay
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--------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay
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---------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops
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------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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2.331 0.000 0 1518 0.108 0.000 0 1518 1.100 0.000 0 988
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All user specified timing constraints are met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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CLK_IN_P {0.000 2.500} 5.000 200.000
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clk_gen {0.000 5.000} 10.000 100.000
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clk_out1_clk_gen {0.000 5.000} 10.000 100.000
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clkfbout_clk_gen {0.000 2.500} 5.000 200.000
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------------------------------------------------------------------------------------------------
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| Intra Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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CLK_IN_P 1.100 0.000 0 1
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clk_gen 2.331 0.000 0 1511 0.108 0.000 0 1511 4.358 0.000 0 982
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clk_out1_clk_gen 8.592 0.000 0 2
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clkfbout_clk_gen 3.592 0.000 0 3
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------------------------------------------------------------------------------------------------
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| Inter Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| Other Path Groups Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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**async_default** clk_gen clk_gen 7.429 0.000 0 7 0.472 0.000 0 7
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------------------------------------------------------------------------------------------------
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| Timing Details
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| --------------
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------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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From Clock: CLK_IN_P
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To Clock: CLK_IN_P
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Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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PW : 0 Failing Endpoints, Worst Slack 1.100ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: CLK_IN_P
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Waveform(ns): { 0.000 2.500 }
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Period(ns): 5.000
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Sources: { CLK_IN_P }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.071 5.000 3.929 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKIN1
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Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 5.000 95.000 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKIN1
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Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKIN1
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Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKIN1
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High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKIN1
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High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 1.400 2.500 1.100 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKIN1
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---------------------------------------------------------------------------------------------------
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From Clock: clk_gen
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To Clock: clk_gen
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Setup : 0 Failing Endpoints, Worst Slack 2.331ns, Total Violation 0.000ns
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Hold : 0 Failing Endpoints, Worst Slack 0.108ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 4.358ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Max Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 2.331ns (required time - arrival time)
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Source: uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_reg/C
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(rising edge-triggered cell FDSE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: uart_tx
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(output port clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: clk_gen
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Path Type: Max at Slow Process Corner
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Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
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Data Path Delay: 5.335ns (logic 2.896ns (54.289%) route 2.439ns (45.711%))
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Logic Levels: 1 (OBUF=1)
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Output Delay: 1.000ns
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Clock Path Skew: -1.267ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.950ns = ( 7.050 - 10.000 )
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Source Clock Delay (SCD): -2.383ns
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Clock Pessimism Removal (CPR): -0.701ns
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Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.112ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_gen rise edge) 0.000 0.000 r
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AD12 0.000 0.000 r CLK_IN_P (IN)
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net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
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AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
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net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
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MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
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-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
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net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
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BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
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| 290 |
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net (fo=982, routed) 1.267 -2.383 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/s_axi_aclk
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SLICE_X24Y224 FDSE r uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_reg/C
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------------------------------------------------------------------- -------------------
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SLICE_X24Y224 FDSE (Prop_fdse_C_Q) 0.223 -2.160 r uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/TX_reg/Q
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net (fo=1, routed) 2.439 0.278 uart_tx_OBUF
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K24 OBUF (Prop_obuf_I_O) 2.673 2.952 r uart_tx_OBUF_inst/O
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net (fo=0) 0.000 2.952 uart_tx
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K24 r uart_tx (OUT)
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------------------------------------------------------------------- -------------------
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(clock clk_gen rise edge) 10.000 10.000 r
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|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 302 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 303 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 304 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 305 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 306 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 307 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 308 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 309 |
|
|
clock pessimism -0.701 6.350
|
| 310 |
|
|
clock uncertainty -0.066 6.283
|
| 311 |
|
|
output delay -1.000 5.283
|
| 312 |
|
|
-------------------------------------------------------------------
|
| 313 |
|
|
required time 5.283
|
| 314 |
|
|
arrival time -2.952
|
| 315 |
|
|
-------------------------------------------------------------------
|
| 316 |
|
|
slack 2.331
|
| 317 |
|
|
|
| 318 |
|
|
Slack (MET) : 5.376ns (required time - arrival time)
|
| 319 |
|
|
Source: enc/round_reg[3]/C
|
| 320 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 321 |
|
|
Destination: enc/data_o_reg[24]/D
|
| 322 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 323 |
|
|
Path Group: clk_gen
|
| 324 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 325 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 326 |
|
|
Data Path Delay: 4.538ns (logic 0.553ns (12.187%) route 3.985ns (87.813%))
|
| 327 |
|
|
Logic Levels: 4 (LUT3=1 LUT6=3)
|
| 328 |
|
|
Clock Path Skew: -0.054ns (DCD - SCD + CPR)
|
| 329 |
|
|
Destination Clock Delay (DCD): -1.818ns = ( 8.182 - 10.000 )
|
| 330 |
|
|
Source Clock Delay (SCD): -2.371ns
|
| 331 |
|
|
Clock Pessimism Removal (CPR): -0.608ns
|
| 332 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 333 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 334 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 335 |
|
|
Phase Error (PE): 0.000ns
|
| 336 |
|
|
|
| 337 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 338 |
|
|
------------------------------------------------------------------- -------------------
|
| 339 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 340 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 341 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 342 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 343 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 344 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 345 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 346 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 347 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 348 |
|
|
net (fo=982, routed) 1.279 -2.371 enc/clk_out1
|
| 349 |
|
|
SLICE_X35Y239 FDCE r enc/round_reg[3]/C
|
| 350 |
|
|
------------------------------------------------------------------- -------------------
|
| 351 |
|
|
SLICE_X35Y239 FDCE (Prop_fdce_C_Q) 0.204 -2.167 r enc/round_reg[3]/Q
|
| 352 |
|
|
net (fo=160, routed) 1.831 -0.336 enc/round[3]
|
| 353 |
|
|
SLICE_X42Y249 LUT3 (Prop_lut3_I1_O) 0.129 -0.207 r enc/state[0][1][6]_i_10/O
|
| 354 |
|
|
net (fo=8, routed) 1.001 0.793 enc/state[0][1][6]_i_10_n_0
|
| 355 |
|
|
SLICE_X36Y246 LUT6 (Prop_lut6_I2_O) 0.134 0.927 r enc/state[0][1][0]_i_5/O
|
| 356 |
|
|
net (fo=2, routed) 0.448 1.375 enc/key[0][1]_1[0]
|
| 357 |
|
|
SLICE_X38Y246 LUT6 (Prop_lut6_I1_O) 0.043 1.418 r enc/state[0][3][0]_i_3/O
|
| 358 |
|
|
net (fo=2, routed) 0.705 2.123 enc/st[0][3]25_out[0]
|
| 359 |
|
|
SLICE_X45Y236 LUT6 (Prop_lut6_I5_O) 0.043 2.166 r enc/data_o[24]_i_1/O
|
| 360 |
|
|
net (fo=1, routed) 0.000 2.166 enc/data_o[24]_i_1_n_0
|
| 361 |
|
|
SLICE_X45Y236 FDCE r enc/data_o_reg[24]/D
|
| 362 |
|
|
------------------------------------------------------------------- -------------------
|
| 363 |
|
|
|
| 364 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 365 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 366 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 367 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 368 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 369 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 370 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 371 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 372 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 373 |
|
|
net (fo=982, routed) 1.132 8.182 enc/clk_out1
|
| 374 |
|
|
SLICE_X45Y236 FDCE r enc/data_o_reg[24]/C
|
| 375 |
|
|
clock pessimism -0.608 7.575
|
| 376 |
|
|
clock uncertainty -0.066 7.508
|
| 377 |
|
|
SLICE_X45Y236 FDCE (Setup_fdce_C_D) 0.034 7.542 enc/data_o_reg[24]
|
| 378 |
|
|
-------------------------------------------------------------------
|
| 379 |
|
|
required time 7.542
|
| 380 |
|
|
arrival time -2.166
|
| 381 |
|
|
-------------------------------------------------------------------
|
| 382 |
|
|
slack 5.376
|
| 383 |
|
|
|
| 384 |
|
|
Slack (MET) : 5.455ns (required time - arrival time)
|
| 385 |
|
|
Source: enc/round_reg[3]/C
|
| 386 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 387 |
|
|
Destination: enc/state_reg[0][1][0]/D
|
| 388 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 389 |
|
|
Path Group: clk_gen
|
| 390 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 391 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 392 |
|
|
Data Path Delay: 4.490ns (logic 0.553ns (12.316%) route 3.937ns (87.684%))
|
| 393 |
|
|
Logic Levels: 4 (LUT3=1 LUT6=3)
|
| 394 |
|
|
Clock Path Skew: -0.022ns (DCD - SCD + CPR)
|
| 395 |
|
|
Destination Clock Delay (DCD): -1.807ns = ( 8.193 - 10.000 )
|
| 396 |
|
|
Source Clock Delay (SCD): -2.371ns
|
| 397 |
|
|
Clock Pessimism Removal (CPR): -0.587ns
|
| 398 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 399 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 400 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 401 |
|
|
Phase Error (PE): 0.000ns
|
| 402 |
|
|
|
| 403 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 404 |
|
|
------------------------------------------------------------------- -------------------
|
| 405 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 406 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 407 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 408 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 409 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 410 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 411 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 412 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 413 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 414 |
|
|
net (fo=982, routed) 1.279 -2.371 enc/clk_out1
|
| 415 |
|
|
SLICE_X35Y239 FDCE r enc/round_reg[3]/C
|
| 416 |
|
|
------------------------------------------------------------------- -------------------
|
| 417 |
|
|
SLICE_X35Y239 FDCE (Prop_fdce_C_Q) 0.204 -2.167 r enc/round_reg[3]/Q
|
| 418 |
|
|
net (fo=160, routed) 1.831 -0.336 enc/round[3]
|
| 419 |
|
|
SLICE_X42Y249 LUT3 (Prop_lut3_I1_O) 0.129 -0.207 r enc/state[0][1][6]_i_10/O
|
| 420 |
|
|
net (fo=8, routed) 1.001 0.793 enc/state[0][1][6]_i_10_n_0
|
| 421 |
|
|
SLICE_X36Y246 LUT6 (Prop_lut6_I2_O) 0.134 0.927 r enc/state[0][1][0]_i_5/O
|
| 422 |
|
|
net (fo=2, routed) 0.669 1.597 enc/key[0][1]_1[0]
|
| 423 |
|
|
SLICE_X33Y240 LUT6 (Prop_lut6_I0_O) 0.043 1.640 r enc/state[0][1][0]_i_4/O
|
| 424 |
|
|
net (fo=2, routed) 0.436 2.076 sys_mngr/st[0][1]29_out[0]
|
| 425 |
|
|
SLICE_X32Y244 LUT6 (Prop_lut6_I5_O) 0.043 2.119 r sys_mngr/state[0][1][0]_i_1/O
|
| 426 |
|
|
net (fo=1, routed) 0.000 2.119 enc/plain_text_data_valid_o_reg_15[0]
|
| 427 |
|
|
SLICE_X32Y244 FDCE r enc/state_reg[0][1][0]/D
|
| 428 |
|
|
------------------------------------------------------------------- -------------------
|
| 429 |
|
|
|
| 430 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 431 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 432 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 433 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 434 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 435 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 436 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 437 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 438 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 439 |
|
|
net (fo=982, routed) 1.143 8.193 enc/clk_out1
|
| 440 |
|
|
SLICE_X32Y244 FDCE r enc/state_reg[0][1][0]/C
|
| 441 |
|
|
clock pessimism -0.587 7.607
|
| 442 |
|
|
clock uncertainty -0.066 7.540
|
| 443 |
|
|
SLICE_X32Y244 FDCE (Setup_fdce_C_D) 0.034 7.574 enc/state_reg[0][1][0]
|
| 444 |
|
|
-------------------------------------------------------------------
|
| 445 |
|
|
required time 7.574
|
| 446 |
|
|
arrival time -2.119
|
| 447 |
|
|
-------------------------------------------------------------------
|
| 448 |
|
|
slack 5.455
|
| 449 |
|
|
|
| 450 |
|
|
Slack (MET) : 5.463ns (required time - arrival time)
|
| 451 |
|
|
Source: sys_mngr/key_o_reg[47]/C
|
| 452 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 453 |
|
|
Destination: enc/state_reg[3][0][3]/D
|
| 454 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 455 |
|
|
Path Group: clk_gen
|
| 456 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 457 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 458 |
|
|
Data Path Delay: 4.224ns (logic 0.805ns (19.059%) route 3.419ns (80.941%))
|
| 459 |
|
|
Logic Levels: 6 (LUT2=1 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
|
| 460 |
|
|
Clock Path Skew: -0.281ns (DCD - SCD + CPR)
|
| 461 |
|
|
Destination Clock Delay (DCD): -1.806ns = ( 8.194 - 10.000 )
|
| 462 |
|
|
Source Clock Delay (SCD): -2.212ns
|
| 463 |
|
|
Clock Pessimism Removal (CPR): -0.688ns
|
| 464 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 465 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 466 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 467 |
|
|
Phase Error (PE): 0.000ns
|
| 468 |
|
|
|
| 469 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 470 |
|
|
------------------------------------------------------------------- -------------------
|
| 471 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 472 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 473 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 474 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 475 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 476 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 477 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 478 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 479 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 480 |
|
|
net (fo=982, routed) 1.438 -2.212 sys_mngr/clk_out1
|
| 481 |
|
|
SLICE_X37Y256 FDCE r sys_mngr/key_o_reg[47]/C
|
| 482 |
|
|
------------------------------------------------------------------- -------------------
|
| 483 |
|
|
SLICE_X37Y256 FDCE (Prop_fdce_C_Q) 0.204 -2.008 r sys_mngr/key_o_reg[47]/Q
|
| 484 |
|
|
net (fo=6, routed) 0.739 -1.269 sys_mngr/key[47]
|
| 485 |
|
|
SLICE_X28Y259 LUT2 (Prop_lut2_I1_O) 0.130 -1.139 r sys_mngr/state[2][0][7]_i_62/O
|
| 486 |
|
|
net (fo=32, routed) 0.774 -0.366 sys_mngr/state[2][0][7]_i_62_n_0
|
| 487 |
|
|
SLICE_X26Y261 LUT6 (Prop_lut6_I2_O) 0.135 -0.231 r sys_mngr/state[2][0][4]_i_42/O
|
| 488 |
|
|
net (fo=1, routed) 0.000 -0.231 sys_mngr/state[2][0][4]_i_42_n_0
|
| 489 |
|
|
SLICE_X26Y261 MUXF7 (Prop_muxf7_I1_O) 0.122 -0.109 r sys_mngr/state_reg[2][0][4]_i_27/O
|
| 490 |
|
|
net (fo=1, routed) 0.000 -0.109 sys_mngr/state_reg[2][0][4]_i_27_n_0
|
| 491 |
|
|
SLICE_X26Y261 MUXF8 (Prop_muxf8_I0_O) 0.045 -0.064 r sys_mngr/state_reg[2][0][4]_i_11/O
|
| 492 |
|
|
net (fo=5, routed) 1.212 1.149 sys_mngr/enc/p_1_in244_in[4]
|
| 493 |
|
|
SLICE_X21Y248 LUT5 (Prop_lut5_I4_O) 0.126 1.275 r sys_mngr/state[3][0][3]_i_3/O
|
| 494 |
|
|
net (fo=1, routed) 0.694 1.968 sys_mngr/state[3][0][3]_i_3_n_0
|
| 495 |
|
|
SLICE_X27Y243 LUT6 (Prop_lut6_I4_O) 0.043 2.011 r sys_mngr/state[3][0][3]_i_1/O
|
| 496 |
|
|
net (fo=1, routed) 0.000 2.011 enc/plain_text_data_valid_o_reg_28[3]
|
| 497 |
|
|
SLICE_X27Y243 FDCE r enc/state_reg[3][0][3]/D
|
| 498 |
|
|
------------------------------------------------------------------- -------------------
|
| 499 |
|
|
|
| 500 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 501 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 502 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 503 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 504 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 505 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 506 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 507 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 508 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 509 |
|
|
net (fo=982, routed) 1.144 8.194 enc/clk_out1
|
| 510 |
|
|
SLICE_X27Y243 FDCE r enc/state_reg[3][0][3]/C
|
| 511 |
|
|
clock pessimism -0.688 7.507
|
| 512 |
|
|
clock uncertainty -0.066 7.440
|
| 513 |
|
|
SLICE_X27Y243 FDCE (Setup_fdce_C_D) 0.034 7.474 enc/state_reg[3][0][3]
|
| 514 |
|
|
-------------------------------------------------------------------
|
| 515 |
|
|
required time 7.474
|
| 516 |
|
|
arrival time -2.011
|
| 517 |
|
|
-------------------------------------------------------------------
|
| 518 |
|
|
slack 5.463
|
| 519 |
|
|
|
| 520 |
|
|
Slack (MET) : 5.464ns (required time - arrival time)
|
| 521 |
|
|
Source: sys_mngr/key_o_reg[80]/C
|
| 522 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 523 |
|
|
Destination: enc/state_reg[3][0][2]/D
|
| 524 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 525 |
|
|
Path Group: clk_gen
|
| 526 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 527 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 528 |
|
|
Data Path Delay: 4.220ns (logic 0.811ns (19.220%) route 3.409ns (80.780%))
|
| 529 |
|
|
Logic Levels: 6 (LUT2=1 LUT4=1 LUT6=2 MUXF7=1 MUXF8=1)
|
| 530 |
|
|
Clock Path Skew: -0.283ns (DCD - SCD + CPR)
|
| 531 |
|
|
Destination Clock Delay (DCD): -1.807ns = ( 8.193 - 10.000 )
|
| 532 |
|
|
Source Clock Delay (SCD): -2.211ns
|
| 533 |
|
|
Clock Pessimism Removal (CPR): -0.688ns
|
| 534 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 535 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 536 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 537 |
|
|
Phase Error (PE): 0.000ns
|
| 538 |
|
|
|
| 539 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 540 |
|
|
------------------------------------------------------------------- -------------------
|
| 541 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 542 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 543 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 544 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 545 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 546 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 547 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 548 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 549 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 550 |
|
|
net (fo=982, routed) 1.439 -2.211 sys_mngr/clk_out1
|
| 551 |
|
|
SLICE_X36Y255 FDCE r sys_mngr/key_o_reg[80]/C
|
| 552 |
|
|
------------------------------------------------------------------- -------------------
|
| 553 |
|
|
SLICE_X36Y255 FDCE (Prop_fdce_C_Q) 0.204 -2.007 r sys_mngr/key_o_reg[80]/Q
|
| 554 |
|
|
net (fo=7, routed) 0.936 -1.071 sys_mngr/key[80]
|
| 555 |
|
|
SLICE_X25Y254 LUT2 (Prop_lut2_I1_O) 0.136 -0.935 r sys_mngr/state[2][0][7]_i_67/O
|
| 556 |
|
|
net (fo=32, routed) 0.990 0.055 sys_mngr/state[2][0][7]_i_67_n_0
|
| 557 |
|
|
SLICE_X19Y254 LUT6 (Prop_lut6_I1_O) 0.135 0.190 r sys_mngr/state[2][0][2]_i_33/O
|
| 558 |
|
|
net (fo=1, routed) 0.000 0.190 sys_mngr/state[2][0][2]_i_33_n_0
|
| 559 |
|
|
SLICE_X19Y254 MUXF7 (Prop_muxf7_I1_O) 0.122 0.312 r sys_mngr/state_reg[2][0][2]_i_24/O
|
| 560 |
|
|
net (fo=1, routed) 0.000 0.312 sys_mngr/state_reg[2][0][2]_i_24_n_0
|
| 561 |
|
|
SLICE_X19Y254 MUXF8 (Prop_muxf8_I0_O) 0.045 0.357 r sys_mngr/state_reg[2][0][2]_i_11/O
|
| 562 |
|
|
net (fo=5, routed) 0.916 1.273 sys_mngr/enc/p_1_in246_in[3]
|
| 563 |
|
|
SLICE_X26Y248 LUT6 (Prop_lut6_I5_O) 0.126 1.399 r sys_mngr/state[3][0][2]_i_2/O
|
| 564 |
|
|
net (fo=1, routed) 0.567 1.965 sys_mngr/enc/add_round_key[3][0]_return[2]
|
| 565 |
|
|
SLICE_X26Y240 LUT4 (Prop_lut4_I2_O) 0.043 2.008 r sys_mngr/state[3][0][2]_i_1/O
|
| 566 |
|
|
net (fo=1, routed) 0.000 2.008 enc/plain_text_data_valid_o_reg_28[2]
|
| 567 |
|
|
SLICE_X26Y240 FDCE r enc/state_reg[3][0][2]/D
|
| 568 |
|
|
------------------------------------------------------------------- -------------------
|
| 569 |
|
|
|
| 570 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 571 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 572 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 573 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 574 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 575 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 576 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 577 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 578 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 579 |
|
|
net (fo=982, routed) 1.143 8.193 enc/clk_out1
|
| 580 |
|
|
SLICE_X26Y240 FDCE r enc/state_reg[3][0][2]/C
|
| 581 |
|
|
clock pessimism -0.688 7.506
|
| 582 |
|
|
clock uncertainty -0.066 7.439
|
| 583 |
|
|
SLICE_X26Y240 FDCE (Setup_fdce_C_D) 0.033 7.472 enc/state_reg[3][0][2]
|
| 584 |
|
|
-------------------------------------------------------------------
|
| 585 |
|
|
required time 7.472
|
| 586 |
|
|
arrival time -2.008
|
| 587 |
|
|
-------------------------------------------------------------------
|
| 588 |
|
|
slack 5.464
|
| 589 |
|
|
|
| 590 |
|
|
Slack (MET) : 5.480ns (required time - arrival time)
|
| 591 |
|
|
Source: enc/round_reg[0]/C
|
| 592 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 593 |
|
|
Destination: enc/data_o_reg[122]/D
|
| 594 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 595 |
|
|
Path Group: clk_gen
|
| 596 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 597 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 598 |
|
|
Data Path Delay: 4.443ns (logic 0.352ns (7.923%) route 4.091ns (92.077%))
|
| 599 |
|
|
Logic Levels: 3 (LUT4=1 LUT6=2)
|
| 600 |
|
|
Clock Path Skew: -0.045ns (DCD - SCD + CPR)
|
| 601 |
|
|
Destination Clock Delay (DCD): -1.809ns = ( 8.191 - 10.000 )
|
| 602 |
|
|
Source Clock Delay (SCD): -2.371ns
|
| 603 |
|
|
Clock Pessimism Removal (CPR): -0.608ns
|
| 604 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 605 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 606 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 607 |
|
|
Phase Error (PE): 0.000ns
|
| 608 |
|
|
|
| 609 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 610 |
|
|
------------------------------------------------------------------- -------------------
|
| 611 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 612 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 613 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 614 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 615 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 616 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 617 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 618 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 619 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 620 |
|
|
net (fo=982, routed) 1.279 -2.371 enc/clk_out1
|
| 621 |
|
|
SLICE_X35Y239 FDCE r enc/round_reg[0]/C
|
| 622 |
|
|
------------------------------------------------------------------- -------------------
|
| 623 |
|
|
SLICE_X35Y239 FDCE (Prop_fdce_C_Q) 0.223 -2.148 f enc/round_reg[0]/Q
|
| 624 |
|
|
net (fo=158, routed) 1.361 -0.787 enc/round[0]
|
| 625 |
|
|
SLICE_X44Y240 LUT4 (Prop_lut4_I1_O) 0.043 -0.744 r enc/state[2][2][7]_i_15/O
|
| 626 |
|
|
net (fo=128, routed) 1.881 1.137 enc/p_0_in
|
| 627 |
|
|
SLICE_X28Y244 LUT6 (Prop_lut6_I1_O) 0.043 1.180 r enc/state[0][0][2]_i_3/O
|
| 628 |
|
|
net (fo=2, routed) 0.848 2.029 enc/st[0][0]31_out[2]
|
| 629 |
|
|
SLICE_X26Y236 LUT6 (Prop_lut6_I5_O) 0.043 2.072 r enc/data_o[122]_i_1/O
|
| 630 |
|
|
net (fo=1, routed) 0.000 2.072 enc/data_o[122]_i_1_n_0
|
| 631 |
|
|
SLICE_X26Y236 FDCE r enc/data_o_reg[122]/D
|
| 632 |
|
|
------------------------------------------------------------------- -------------------
|
| 633 |
|
|
|
| 634 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 635 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 636 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 637 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 638 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 639 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 640 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 641 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 642 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 643 |
|
|
net (fo=982, routed) 1.141 8.191 enc/clk_out1
|
| 644 |
|
|
SLICE_X26Y236 FDCE r enc/data_o_reg[122]/C
|
| 645 |
|
|
clock pessimism -0.608 7.584
|
| 646 |
|
|
clock uncertainty -0.066 7.517
|
| 647 |
|
|
SLICE_X26Y236 FDCE (Setup_fdce_C_D) 0.034 7.551 enc/data_o_reg[122]
|
| 648 |
|
|
-------------------------------------------------------------------
|
| 649 |
|
|
required time 7.551
|
| 650 |
|
|
arrival time -2.072
|
| 651 |
|
|
-------------------------------------------------------------------
|
| 652 |
|
|
slack 5.480
|
| 653 |
|
|
|
| 654 |
|
|
Slack (MET) : 5.531ns (required time - arrival time)
|
| 655 |
|
|
Source: sys_mngr/key_o_reg[61]/C
|
| 656 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 657 |
|
|
Destination: enc/state_reg[3][2][4]/D
|
| 658 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 659 |
|
|
Path Group: clk_gen
|
| 660 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 661 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 662 |
|
|
Data Path Delay: 4.148ns (logic 0.822ns (19.816%) route 3.326ns (80.184%))
|
| 663 |
|
|
Logic Levels: 6 (LUT2=1 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1)
|
| 664 |
|
|
Clock Path Skew: -0.287ns (DCD - SCD + CPR)
|
| 665 |
|
|
Destination Clock Delay (DCD): -1.814ns = ( 8.186 - 10.000 )
|
| 666 |
|
|
Source Clock Delay (SCD): -2.214ns
|
| 667 |
|
|
Clock Pessimism Removal (CPR): -0.688ns
|
| 668 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 669 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 670 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 671 |
|
|
Phase Error (PE): 0.000ns
|
| 672 |
|
|
|
| 673 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 674 |
|
|
------------------------------------------------------------------- -------------------
|
| 675 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 676 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 677 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 678 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 679 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 680 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 681 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 682 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 683 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 684 |
|
|
net (fo=982, routed) 1.436 -2.214 sys_mngr/clk_out1
|
| 685 |
|
|
SLICE_X38Y258 FDCE r sys_mngr/key_o_reg[61]/C
|
| 686 |
|
|
------------------------------------------------------------------- -------------------
|
| 687 |
|
|
SLICE_X38Y258 FDCE (Prop_fdce_C_Q) 0.236 -1.978 r sys_mngr/key_o_reg[61]/Q
|
| 688 |
|
|
net (fo=3, routed) 0.657 -1.321 sys_mngr/key[61]
|
| 689 |
|
|
SLICE_X35Y260 LUT2 (Prop_lut2_I1_O) 0.132 -1.189 r sys_mngr/state[2][2][7]_i_44/O
|
| 690 |
|
|
net (fo=32, routed) 0.685 -0.504 sys_mngr/state[2][2][7]_i_44_n_0
|
| 691 |
|
|
SLICE_X41Y262 LUT6 (Prop_lut6_I5_O) 0.135 -0.369 r sys_mngr/state[2][2][7]_i_23/O
|
| 692 |
|
|
net (fo=1, routed) 0.000 -0.369 sys_mngr/state[2][2][7]_i_23_n_0
|
| 693 |
|
|
SLICE_X41Y262 MUXF7 (Prop_muxf7_I0_O) 0.107 -0.262 r sys_mngr/state_reg[2][2][7]_i_9/O
|
| 694 |
|
|
net (fo=1, routed) 0.000 -0.262 sys_mngr/state_reg[2][2][7]_i_9_n_0
|
| 695 |
|
|
SLICE_X41Y262 MUXF8 (Prop_muxf8_I1_O) 0.043 -0.219 r sys_mngr/state_reg[2][2][7]_i_3/O
|
| 696 |
|
|
net (fo=11, routed) 1.401 1.182 sys_mngr/state_reg[2][2][7]_i_3_n_0
|
| 697 |
|
|
SLICE_X41Y251 LUT5 (Prop_lut5_I2_O) 0.126 1.308 r sys_mngr/state[3][2][4]_i_4/O
|
| 698 |
|
|
net (fo=1, routed) 0.583 1.891 sys_mngr/state[3][2][4]_i_4_n_0
|
| 699 |
|
|
SLICE_X45Y247 LUT6 (Prop_lut6_I4_O) 0.043 1.934 r sys_mngr/state[3][2][4]_i_1/O
|
| 700 |
|
|
net (fo=1, routed) 0.000 1.934 enc/plain_text_data_valid_o_reg_5[4]
|
| 701 |
|
|
SLICE_X45Y247 FDCE r enc/state_reg[3][2][4]/D
|
| 702 |
|
|
------------------------------------------------------------------- -------------------
|
| 703 |
|
|
|
| 704 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 705 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 706 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 707 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 708 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 709 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 710 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 711 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 712 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 713 |
|
|
net (fo=982, routed) 1.136 8.186 enc/clk_out1
|
| 714 |
|
|
SLICE_X45Y247 FDCE r enc/state_reg[3][2][4]/C
|
| 715 |
|
|
clock pessimism -0.688 7.499
|
| 716 |
|
|
clock uncertainty -0.066 7.432
|
| 717 |
|
|
SLICE_X45Y247 FDCE (Setup_fdce_C_D) 0.033 7.465 enc/state_reg[3][2][4]
|
| 718 |
|
|
-------------------------------------------------------------------
|
| 719 |
|
|
required time 7.465
|
| 720 |
|
|
arrival time -1.934
|
| 721 |
|
|
-------------------------------------------------------------------
|
| 722 |
|
|
slack 5.531
|
| 723 |
|
|
|
| 724 |
|
|
Slack (MET) : 5.550ns (required time - arrival time)
|
| 725 |
|
|
Source: sys_mngr/key_set_in_progress_reg_reg/C
|
| 726 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 727 |
|
|
Destination: sys_mngr/key_o_reg[123]/CE
|
| 728 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 729 |
|
|
Path Group: clk_gen
|
| 730 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 731 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 732 |
|
|
Data Path Delay: 4.194ns (logic 0.352ns (8.392%) route 3.842ns (91.608%))
|
| 733 |
|
|
Logic Levels: 3 (LUT2=1 LUT4=1 LUT5=1)
|
| 734 |
|
|
Clock Path Skew: 0.012ns (DCD - SCD + CPR)
|
| 735 |
|
|
Destination Clock Delay (DCD): -1.679ns = ( 8.321 - 10.000 )
|
| 736 |
|
|
Source Clock Delay (SCD): -2.378ns
|
| 737 |
|
|
Clock Pessimism Removal (CPR): -0.688ns
|
| 738 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 739 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 740 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 741 |
|
|
Phase Error (PE): 0.000ns
|
| 742 |
|
|
|
| 743 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 744 |
|
|
------------------------------------------------------------------- -------------------
|
| 745 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 746 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 747 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 748 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 749 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 750 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 751 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 752 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 753 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 754 |
|
|
net (fo=982, routed) 1.272 -2.378 sys_mngr/clk_out1
|
| 755 |
|
|
SLICE_X29Y231 FDCE r sys_mngr/key_set_in_progress_reg_reg/C
|
| 756 |
|
|
------------------------------------------------------------------- -------------------
|
| 757 |
|
|
SLICE_X29Y231 FDCE (Prop_fdce_C_Q) 0.223 -2.155 f sys_mngr/key_set_in_progress_reg_reg/Q
|
| 758 |
|
|
net (fo=9, routed) 0.398 -1.757 sys_mngr/key_set_in_progress_reg
|
| 759 |
|
|
SLICE_X28Y231 LUT2 (Prop_lut2_I0_O) 0.043 -1.714 f sys_mngr/key_o[127]_i_3/O
|
| 760 |
|
|
net (fo=136, routed) 0.767 -0.947 sys_mngr/key_o[127]_i_3_n_0
|
| 761 |
|
|
SLICE_X24Y235 LUT4 (Prop_lut4_I0_O) 0.043 -0.904 f sys_mngr/key_set_complete_reg_i_2/O
|
| 762 |
|
|
net (fo=3, routed) 0.494 -0.410 sys_mngr/key_set_complete_reg_i_2_n_0
|
| 763 |
|
|
SLICE_X29Y231 LUT5 (Prop_lut5_I1_O) 0.043 -0.367 r sys_mngr/key_o[127]_i_1/O
|
| 764 |
|
|
net (fo=128, routed) 2.183 1.816 sys_mngr/key_0[127]
|
| 765 |
|
|
SLICE_X32Y258 FDCE r sys_mngr/key_o_reg[123]/CE
|
| 766 |
|
|
------------------------------------------------------------------- -------------------
|
| 767 |
|
|
|
| 768 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 769 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 770 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 771 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 772 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 773 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 774 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 775 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 776 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 777 |
|
|
net (fo=982, routed) 1.271 8.321 sys_mngr/clk_out1
|
| 778 |
|
|
SLICE_X32Y258 FDCE r sys_mngr/key_o_reg[123]/C
|
| 779 |
|
|
clock pessimism -0.688 7.634
|
| 780 |
|
|
clock uncertainty -0.066 7.567
|
| 781 |
|
|
SLICE_X32Y258 FDCE (Setup_fdce_C_CE) -0.201 7.366 sys_mngr/key_o_reg[123]
|
| 782 |
|
|
-------------------------------------------------------------------
|
| 783 |
|
|
required time 7.366
|
| 784 |
|
|
arrival time -1.816
|
| 785 |
|
|
-------------------------------------------------------------------
|
| 786 |
|
|
slack 5.550
|
| 787 |
|
|
|
| 788 |
|
|
Slack (MET) : 5.550ns (required time - arrival time)
|
| 789 |
|
|
Source: sys_mngr/key_set_in_progress_reg_reg/C
|
| 790 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 791 |
|
|
Destination: sys_mngr/key_o_reg[124]/CE
|
| 792 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 793 |
|
|
Path Group: clk_gen
|
| 794 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 795 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 796 |
|
|
Data Path Delay: 4.194ns (logic 0.352ns (8.392%) route 3.842ns (91.608%))
|
| 797 |
|
|
Logic Levels: 3 (LUT2=1 LUT4=1 LUT5=1)
|
| 798 |
|
|
Clock Path Skew: 0.012ns (DCD - SCD + CPR)
|
| 799 |
|
|
Destination Clock Delay (DCD): -1.679ns = ( 8.321 - 10.000 )
|
| 800 |
|
|
Source Clock Delay (SCD): -2.378ns
|
| 801 |
|
|
Clock Pessimism Removal (CPR): -0.688ns
|
| 802 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 803 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 804 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 805 |
|
|
Phase Error (PE): 0.000ns
|
| 806 |
|
|
|
| 807 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 808 |
|
|
------------------------------------------------------------------- -------------------
|
| 809 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 810 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 811 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 812 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 813 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 814 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 815 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 816 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 817 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 818 |
|
|
net (fo=982, routed) 1.272 -2.378 sys_mngr/clk_out1
|
| 819 |
|
|
SLICE_X29Y231 FDCE r sys_mngr/key_set_in_progress_reg_reg/C
|
| 820 |
|
|
------------------------------------------------------------------- -------------------
|
| 821 |
|
|
SLICE_X29Y231 FDCE (Prop_fdce_C_Q) 0.223 -2.155 f sys_mngr/key_set_in_progress_reg_reg/Q
|
| 822 |
|
|
net (fo=9, routed) 0.398 -1.757 sys_mngr/key_set_in_progress_reg
|
| 823 |
|
|
SLICE_X28Y231 LUT2 (Prop_lut2_I0_O) 0.043 -1.714 f sys_mngr/key_o[127]_i_3/O
|
| 824 |
|
|
net (fo=136, routed) 0.767 -0.947 sys_mngr/key_o[127]_i_3_n_0
|
| 825 |
|
|
SLICE_X24Y235 LUT4 (Prop_lut4_I0_O) 0.043 -0.904 f sys_mngr/key_set_complete_reg_i_2/O
|
| 826 |
|
|
net (fo=3, routed) 0.494 -0.410 sys_mngr/key_set_complete_reg_i_2_n_0
|
| 827 |
|
|
SLICE_X29Y231 LUT5 (Prop_lut5_I1_O) 0.043 -0.367 r sys_mngr/key_o[127]_i_1/O
|
| 828 |
|
|
net (fo=128, routed) 2.183 1.816 sys_mngr/key_0[127]
|
| 829 |
|
|
SLICE_X32Y258 FDCE r sys_mngr/key_o_reg[124]/CE
|
| 830 |
|
|
------------------------------------------------------------------- -------------------
|
| 831 |
|
|
|
| 832 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 833 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 834 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 835 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 836 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 837 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 838 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 839 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 840 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 841 |
|
|
net (fo=982, routed) 1.271 8.321 sys_mngr/clk_out1
|
| 842 |
|
|
SLICE_X32Y258 FDCE r sys_mngr/key_o_reg[124]/C
|
| 843 |
|
|
clock pessimism -0.688 7.634
|
| 844 |
|
|
clock uncertainty -0.066 7.567
|
| 845 |
|
|
SLICE_X32Y258 FDCE (Setup_fdce_C_CE) -0.201 7.366 sys_mngr/key_o_reg[124]
|
| 846 |
|
|
-------------------------------------------------------------------
|
| 847 |
|
|
required time 7.366
|
| 848 |
|
|
arrival time -1.816
|
| 849 |
|
|
-------------------------------------------------------------------
|
| 850 |
|
|
slack 5.550
|
| 851 |
|
|
|
| 852 |
|
|
Slack (MET) : 5.559ns (required time - arrival time)
|
| 853 |
|
|
Source: enc/round_reg[3]/C
|
| 854 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 855 |
|
|
Destination: enc/data_o_reg[31]/D
|
| 856 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 857 |
|
|
Path Group: clk_gen
|
| 858 |
|
|
Path Type: Setup (Max at Slow Process Corner)
|
| 859 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 860 |
|
|
Data Path Delay: 4.387ns (logic 0.553ns (12.607%) route 3.834ns (87.393%))
|
| 861 |
|
|
Logic Levels: 4 (LUT3=1 LUT6=3)
|
| 862 |
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
| 863 |
|
|
Destination Clock Delay (DCD): -1.816ns = ( 8.184 - 10.000 )
|
| 864 |
|
|
Source Clock Delay (SCD): -2.371ns
|
| 865 |
|
|
Clock Pessimism Removal (CPR): -0.608ns
|
| 866 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 867 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 868 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 869 |
|
|
Phase Error (PE): 0.000ns
|
| 870 |
|
|
|
| 871 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 872 |
|
|
------------------------------------------------------------------- -------------------
|
| 873 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 874 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 875 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 876 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 877 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 878 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 879 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 880 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 881 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 882 |
|
|
net (fo=982, routed) 1.279 -2.371 enc/clk_out1
|
| 883 |
|
|
SLICE_X35Y239 FDCE r enc/round_reg[3]/C
|
| 884 |
|
|
------------------------------------------------------------------- -------------------
|
| 885 |
|
|
SLICE_X35Y239 FDCE (Prop_fdce_C_Q) 0.204 -2.167 r enc/round_reg[3]/Q
|
| 886 |
|
|
net (fo=160, routed) 1.831 -0.336 enc/round[3]
|
| 887 |
|
|
SLICE_X42Y249 LUT3 (Prop_lut3_I1_O) 0.129 -0.207 r enc/state[0][1][6]_i_10/O
|
| 888 |
|
|
net (fo=8, routed) 0.826 0.618 enc/state[0][1][6]_i_10_n_0
|
| 889 |
|
|
SLICE_X35Y246 LUT6 (Prop_lut6_I3_O) 0.134 0.752 r enc/state[0][3][7]_i_4/O
|
| 890 |
|
|
net (fo=1, routed) 0.592 1.344 enc/key[0][1]_1[7]
|
| 891 |
|
|
SLICE_X42Y246 LUT6 (Prop_lut6_I1_O) 0.043 1.387 r enc/state[0][3][7]_i_3/O
|
| 892 |
|
|
net (fo=2, routed) 0.585 1.972 enc/st[0][3]25_out[7]
|
| 893 |
|
|
SLICE_X42Y240 LUT6 (Prop_lut6_I5_O) 0.043 2.015 r enc/data_o[31]_i_1/O
|
| 894 |
|
|
net (fo=1, routed) 0.000 2.015 enc/data_o[31]_i_1_n_0
|
| 895 |
|
|
SLICE_X42Y240 FDCE r enc/data_o_reg[31]/D
|
| 896 |
|
|
------------------------------------------------------------------- -------------------
|
| 897 |
|
|
|
| 898 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 899 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 900 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 901 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 902 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 903 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 904 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 905 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 906 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 907 |
|
|
net (fo=982, routed) 1.134 8.184 enc/clk_out1
|
| 908 |
|
|
SLICE_X42Y240 FDCE r enc/data_o_reg[31]/C
|
| 909 |
|
|
clock pessimism -0.608 7.577
|
| 910 |
|
|
clock uncertainty -0.066 7.510
|
| 911 |
|
|
SLICE_X42Y240 FDCE (Setup_fdce_C_D) 0.064 7.574 enc/data_o_reg[31]
|
| 912 |
|
|
-------------------------------------------------------------------
|
| 913 |
|
|
required time 7.574
|
| 914 |
|
|
arrival time -2.015
|
| 915 |
|
|
-------------------------------------------------------------------
|
| 916 |
|
|
slack 5.559
|
| 917 |
|
|
|
| 918 |
|
|
|
| 919 |
|
|
|
| 920 |
|
|
|
| 921 |
|
|
|
| 922 |
|
|
Min Delay Paths
|
| 923 |
|
|
--------------------------------------------------------------------------------------
|
| 924 |
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
| 925 |
|
|
Source: enc/data_o_reg[80]/C
|
| 926 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 927 |
|
|
Destination: sys_mngr/cipher_data_reg_reg[80]/D
|
| 928 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 929 |
|
|
Path Group: clk_gen
|
| 930 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 931 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 932 |
|
|
Data Path Delay: 0.180ns (logic 0.128ns (71.200%) route 0.052ns (28.800%))
|
| 933 |
|
|
Logic Levels: 1 (LUT3=1)
|
| 934 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 935 |
|
|
Destination Clock Delay (DCD): -0.687ns
|
| 936 |
|
|
Source Clock Delay (SCD): -0.638ns
|
| 937 |
|
|
Clock Pessimism Removal (CPR): -0.061ns
|
| 938 |
|
|
|
| 939 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 940 |
|
|
------------------------------------------------------------------- -------------------
|
| 941 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 942 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 943 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 944 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 945 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 946 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 947 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 948 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 949 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 950 |
|
|
net (fo=982, routed) 0.566 -0.638 enc/clk_out1
|
| 951 |
|
|
SLICE_X34Y237 FDCE r enc/data_o_reg[80]/C
|
| 952 |
|
|
------------------------------------------------------------------- -------------------
|
| 953 |
|
|
SLICE_X34Y237 FDCE (Prop_fdce_C_Q) 0.100 -0.538 r enc/data_o_reg[80]/Q
|
| 954 |
|
|
net (fo=1, routed) 0.052 -0.486 sys_mngr/data_o_reg[127][72]
|
| 955 |
|
|
SLICE_X35Y237 LUT3 (Prop_lut3_I2_O) 0.028 -0.458 r sys_mngr/cipher_data_reg[80]_i_1/O
|
| 956 |
|
|
net (fo=1, routed) 0.000 -0.458 sys_mngr/cipher_data[80]
|
| 957 |
|
|
SLICE_X35Y237 FDCE r sys_mngr/cipher_data_reg_reg[80]/D
|
| 958 |
|
|
------------------------------------------------------------------- -------------------
|
| 959 |
|
|
|
| 960 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 961 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 962 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 963 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 964 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 965 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 966 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 967 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 968 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 969 |
|
|
net (fo=982, routed) 0.770 -0.687 sys_mngr/clk_out1
|
| 970 |
|
|
SLICE_X35Y237 FDCE r sys_mngr/cipher_data_reg_reg[80]/C
|
| 971 |
|
|
clock pessimism 0.061 -0.627
|
| 972 |
|
|
SLICE_X35Y237 FDCE (Hold_fdce_C_D) 0.061 -0.566 sys_mngr/cipher_data_reg_reg[80]
|
| 973 |
|
|
-------------------------------------------------------------------
|
| 974 |
|
|
required time 0.566
|
| 975 |
|
|
arrival time -0.458
|
| 976 |
|
|
-------------------------------------------------------------------
|
| 977 |
|
|
slack 0.108
|
| 978 |
|
|
|
| 979 |
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
| 980 |
|
|
Source: uartlite/U0/UARTLITE_CORE_I/rx_Data_Present_Pre_reg/C
|
| 981 |
|
|
(rising edge-triggered cell FDRE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 982 |
|
|
Destination: uartlite/U0/UARTLITE_CORE_I/Interrupt_reg/D
|
| 983 |
|
|
(rising edge-triggered cell FDRE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 984 |
|
|
Path Group: clk_gen
|
| 985 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 986 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 987 |
|
|
Data Path Delay: 0.180ns (logic 0.128ns (71.200%) route 0.052ns (28.800%))
|
| 988 |
|
|
Logic Levels: 1 (LUT5=1)
|
| 989 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 990 |
|
|
Destination Clock Delay (DCD): -0.693ns
|
| 991 |
|
|
Source Clock Delay (SCD): -0.643ns
|
| 992 |
|
|
Clock Pessimism Removal (CPR): -0.062ns
|
| 993 |
|
|
|
| 994 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 995 |
|
|
------------------------------------------------------------------- -------------------
|
| 996 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 997 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 998 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 999 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1000 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1001 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1002 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1003 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1004 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1005 |
|
|
net (fo=982, routed) 0.561 -0.643 uartlite/U0/UARTLITE_CORE_I/s_axi_aclk
|
| 1006 |
|
|
SLICE_X24Y227 FDRE r uartlite/U0/UARTLITE_CORE_I/rx_Data_Present_Pre_reg/C
|
| 1007 |
|
|
------------------------------------------------------------------- -------------------
|
| 1008 |
|
|
SLICE_X24Y227 FDRE (Prop_fdre_C_Q) 0.100 -0.543 f uartlite/U0/UARTLITE_CORE_I/rx_Data_Present_Pre_reg/Q
|
| 1009 |
|
|
net (fo=1, routed) 0.052 -0.491 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/rx_Data_Present_Pre
|
| 1010 |
|
|
SLICE_X25Y227 LUT5 (Prop_lut5_I0_O) 0.028 -0.463 r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/Interrupt_i_2/O
|
| 1011 |
|
|
net (fo=1, routed) 0.000 -0.463 uartlite/U0/UARTLITE_CORE_I/Interrupt0
|
| 1012 |
|
|
SLICE_X25Y227 FDRE r uartlite/U0/UARTLITE_CORE_I/Interrupt_reg/D
|
| 1013 |
|
|
------------------------------------------------------------------- -------------------
|
| 1014 |
|
|
|
| 1015 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1016 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1017 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1018 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1019 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1020 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1021 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1022 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1023 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1024 |
|
|
net (fo=982, routed) 0.764 -0.693 uartlite/U0/UARTLITE_CORE_I/s_axi_aclk
|
| 1025 |
|
|
SLICE_X25Y227 FDRE r uartlite/U0/UARTLITE_CORE_I/Interrupt_reg/C
|
| 1026 |
|
|
clock pessimism 0.062 -0.632
|
| 1027 |
|
|
SLICE_X25Y227 FDRE (Hold_fdre_C_D) 0.061 -0.571 uartlite/U0/UARTLITE_CORE_I/Interrupt_reg
|
| 1028 |
|
|
-------------------------------------------------------------------
|
| 1029 |
|
|
required time 0.571
|
| 1030 |
|
|
arrival time -0.463
|
| 1031 |
|
|
-------------------------------------------------------------------
|
| 1032 |
|
|
slack 0.108
|
| 1033 |
|
|
|
| 1034 |
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
| 1035 |
|
|
Source: enc/data_o_reg[92]/C
|
| 1036 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1037 |
|
|
Destination: sys_mngr/cipher_data_reg_reg[92]/D
|
| 1038 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1039 |
|
|
Path Group: clk_gen
|
| 1040 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 1041 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 1042 |
|
|
Data Path Delay: 0.182ns (logic 0.128ns (70.416%) route 0.054ns (29.584%))
|
| 1043 |
|
|
Logic Levels: 1 (LUT3=1)
|
| 1044 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 1045 |
|
|
Destination Clock Delay (DCD): -0.686ns
|
| 1046 |
|
|
Source Clock Delay (SCD): -0.638ns
|
| 1047 |
|
|
Clock Pessimism Removal (CPR): -0.060ns
|
| 1048 |
|
|
|
| 1049 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1050 |
|
|
------------------------------------------------------------------- -------------------
|
| 1051 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1052 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1053 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1054 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1055 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1056 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1057 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1058 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1059 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1060 |
|
|
net (fo=982, routed) 0.566 -0.638 enc/clk_out1
|
| 1061 |
|
|
SLICE_X30Y236 FDCE r enc/data_o_reg[92]/C
|
| 1062 |
|
|
------------------------------------------------------------------- -------------------
|
| 1063 |
|
|
SLICE_X30Y236 FDCE (Prop_fdce_C_Q) 0.100 -0.538 r enc/data_o_reg[92]/Q
|
| 1064 |
|
|
net (fo=1, routed) 0.054 -0.484 sys_mngr/data_o_reg[127][84]
|
| 1065 |
|
|
SLICE_X31Y236 LUT3 (Prop_lut3_I2_O) 0.028 -0.456 r sys_mngr/cipher_data_reg[92]_i_1/O
|
| 1066 |
|
|
net (fo=1, routed) 0.000 -0.456 sys_mngr/cipher_data[92]
|
| 1067 |
|
|
SLICE_X31Y236 FDCE r sys_mngr/cipher_data_reg_reg[92]/D
|
| 1068 |
|
|
------------------------------------------------------------------- -------------------
|
| 1069 |
|
|
|
| 1070 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1071 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1072 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1073 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1074 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1075 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1076 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1077 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1078 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1079 |
|
|
net (fo=982, routed) 0.771 -0.686 sys_mngr/clk_out1
|
| 1080 |
|
|
SLICE_X31Y236 FDCE r sys_mngr/cipher_data_reg_reg[92]/C
|
| 1081 |
|
|
clock pessimism 0.060 -0.627
|
| 1082 |
|
|
SLICE_X31Y236 FDCE (Hold_fdce_C_D) 0.061 -0.566 sys_mngr/cipher_data_reg_reg[92]
|
| 1083 |
|
|
-------------------------------------------------------------------
|
| 1084 |
|
|
required time 0.566
|
| 1085 |
|
|
arrival time -0.456
|
| 1086 |
|
|
-------------------------------------------------------------------
|
| 1087 |
|
|
slack 0.110
|
| 1088 |
|
|
|
| 1089 |
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
| 1090 |
|
|
Source: enc/data_o_reg[48]/C
|
| 1091 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1092 |
|
|
Destination: sys_mngr/cipher_data_reg_reg[48]/D
|
| 1093 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1094 |
|
|
Path Group: clk_gen
|
| 1095 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 1096 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 1097 |
|
|
Data Path Delay: 0.182ns (logic 0.128ns (70.383%) route 0.054ns (29.617%))
|
| 1098 |
|
|
Logic Levels: 1 (LUT3=1)
|
| 1099 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 1100 |
|
|
Destination Clock Delay (DCD): -0.689ns
|
| 1101 |
|
|
Source Clock Delay (SCD): -0.640ns
|
| 1102 |
|
|
Clock Pessimism Removal (CPR): -0.061ns
|
| 1103 |
|
|
|
| 1104 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1105 |
|
|
------------------------------------------------------------------- -------------------
|
| 1106 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1107 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1108 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1109 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1110 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1111 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1112 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1113 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1114 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1115 |
|
|
net (fo=982, routed) 0.564 -0.640 enc/clk_out1
|
| 1116 |
|
|
SLICE_X40Y238 FDCE r enc/data_o_reg[48]/C
|
| 1117 |
|
|
------------------------------------------------------------------- -------------------
|
| 1118 |
|
|
SLICE_X40Y238 FDCE (Prop_fdce_C_Q) 0.100 -0.540 r enc/data_o_reg[48]/Q
|
| 1119 |
|
|
net (fo=1, routed) 0.054 -0.486 sys_mngr/data_o_reg[127][40]
|
| 1120 |
|
|
SLICE_X41Y238 LUT3 (Prop_lut3_I2_O) 0.028 -0.458 r sys_mngr/cipher_data_reg[48]_i_1/O
|
| 1121 |
|
|
net (fo=1, routed) 0.000 -0.458 sys_mngr/cipher_data[48]
|
| 1122 |
|
|
SLICE_X41Y238 FDCE r sys_mngr/cipher_data_reg_reg[48]/D
|
| 1123 |
|
|
------------------------------------------------------------------- -------------------
|
| 1124 |
|
|
|
| 1125 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1126 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1127 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1128 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1129 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1130 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1131 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1132 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1133 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1134 |
|
|
net (fo=982, routed) 0.768 -0.689 sys_mngr/clk_out1
|
| 1135 |
|
|
SLICE_X41Y238 FDCE r sys_mngr/cipher_data_reg_reg[48]/C
|
| 1136 |
|
|
clock pessimism 0.061 -0.629
|
| 1137 |
|
|
SLICE_X41Y238 FDCE (Hold_fdce_C_D) 0.060 -0.569 sys_mngr/cipher_data_reg_reg[48]
|
| 1138 |
|
|
-------------------------------------------------------------------
|
| 1139 |
|
|
required time 0.569
|
| 1140 |
|
|
arrival time -0.458
|
| 1141 |
|
|
-------------------------------------------------------------------
|
| 1142 |
|
|
slack 0.111
|
| 1143 |
|
|
|
| 1144 |
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
| 1145 |
|
|
Source: enc/data_o_reg[84]/C
|
| 1146 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1147 |
|
|
Destination: sys_mngr/cipher_data_reg_reg[84]/D
|
| 1148 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1149 |
|
|
Path Group: clk_gen
|
| 1150 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 1151 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 1152 |
|
|
Data Path Delay: 0.182ns (logic 0.128ns (70.383%) route 0.054ns (29.617%))
|
| 1153 |
|
|
Logic Levels: 1 (LUT3=1)
|
| 1154 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 1155 |
|
|
Destination Clock Delay (DCD): -0.687ns
|
| 1156 |
|
|
Source Clock Delay (SCD): -0.638ns
|
| 1157 |
|
|
Clock Pessimism Removal (CPR): -0.061ns
|
| 1158 |
|
|
|
| 1159 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1160 |
|
|
------------------------------------------------------------------- -------------------
|
| 1161 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1162 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1163 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1164 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1165 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1166 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1167 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1168 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1169 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1170 |
|
|
net (fo=982, routed) 0.566 -0.638 enc/clk_out1
|
| 1171 |
|
|
SLICE_X32Y237 FDCE r enc/data_o_reg[84]/C
|
| 1172 |
|
|
------------------------------------------------------------------- -------------------
|
| 1173 |
|
|
SLICE_X32Y237 FDCE (Prop_fdce_C_Q) 0.100 -0.538 r enc/data_o_reg[84]/Q
|
| 1174 |
|
|
net (fo=1, routed) 0.054 -0.484 sys_mngr/data_o_reg[127][76]
|
| 1175 |
|
|
SLICE_X33Y237 LUT3 (Prop_lut3_I2_O) 0.028 -0.456 r sys_mngr/cipher_data_reg[84]_i_1/O
|
| 1176 |
|
|
net (fo=1, routed) 0.000 -0.456 sys_mngr/cipher_data[84]
|
| 1177 |
|
|
SLICE_X33Y237 FDCE r sys_mngr/cipher_data_reg_reg[84]/D
|
| 1178 |
|
|
------------------------------------------------------------------- -------------------
|
| 1179 |
|
|
|
| 1180 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1181 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1182 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1183 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1184 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1185 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1186 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1187 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1188 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1189 |
|
|
net (fo=982, routed) 0.770 -0.687 sys_mngr/clk_out1
|
| 1190 |
|
|
SLICE_X33Y237 FDCE r sys_mngr/cipher_data_reg_reg[84]/C
|
| 1191 |
|
|
clock pessimism 0.061 -0.627
|
| 1192 |
|
|
SLICE_X33Y237 FDCE (Hold_fdce_C_D) 0.060 -0.567 sys_mngr/cipher_data_reg_reg[84]
|
| 1193 |
|
|
-------------------------------------------------------------------
|
| 1194 |
|
|
required time 0.567
|
| 1195 |
|
|
arrival time -0.456
|
| 1196 |
|
|
-------------------------------------------------------------------
|
| 1197 |
|
|
slack 0.111
|
| 1198 |
|
|
|
| 1199 |
|
|
Slack (MET) : 0.112ns (arrival time - required time)
|
| 1200 |
|
|
Source: sys_mngr/cipher_data_reg_reg[111]/C
|
| 1201 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1202 |
|
|
Destination: sys_mngr/cipher_data_reg_reg[119]/D
|
| 1203 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1204 |
|
|
Path Group: clk_gen
|
| 1205 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 1206 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 1207 |
|
|
Data Path Delay: 0.183ns (logic 0.128ns (69.998%) route 0.055ns (30.002%))
|
| 1208 |
|
|
Logic Levels: 1 (LUT3=1)
|
| 1209 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 1210 |
|
|
Destination Clock Delay (DCD): -0.685ns
|
| 1211 |
|
|
Source Clock Delay (SCD): -0.636ns
|
| 1212 |
|
|
Clock Pessimism Removal (CPR): -0.061ns
|
| 1213 |
|
|
|
| 1214 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1215 |
|
|
------------------------------------------------------------------- -------------------
|
| 1216 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1217 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1218 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1219 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1220 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1221 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1222 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1223 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1224 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1225 |
|
|
net (fo=982, routed) 0.568 -0.636 sys_mngr/clk_out1
|
| 1226 |
|
|
SLICE_X26Y235 FDCE r sys_mngr/cipher_data_reg_reg[111]/C
|
| 1227 |
|
|
------------------------------------------------------------------- -------------------
|
| 1228 |
|
|
SLICE_X26Y235 FDCE (Prop_fdce_C_Q) 0.100 -0.536 r sys_mngr/cipher_data_reg_reg[111]/Q
|
| 1229 |
|
|
net (fo=1, routed) 0.055 -0.481 sys_mngr/cipher_data_reg[111]
|
| 1230 |
|
|
SLICE_X27Y235 LUT3 (Prop_lut3_I0_O) 0.028 -0.453 r sys_mngr/cipher_data_reg[119]_i_1/O
|
| 1231 |
|
|
net (fo=1, routed) 0.000 -0.453 sys_mngr/cipher_data[119]
|
| 1232 |
|
|
SLICE_X27Y235 FDCE r sys_mngr/cipher_data_reg_reg[119]/D
|
| 1233 |
|
|
------------------------------------------------------------------- -------------------
|
| 1234 |
|
|
|
| 1235 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1236 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1237 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1238 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1239 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1240 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1241 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1242 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1243 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1244 |
|
|
net (fo=982, routed) 0.772 -0.685 sys_mngr/clk_out1
|
| 1245 |
|
|
SLICE_X27Y235 FDCE r sys_mngr/cipher_data_reg_reg[119]/C
|
| 1246 |
|
|
clock pessimism 0.061 -0.625
|
| 1247 |
|
|
SLICE_X27Y235 FDCE (Hold_fdce_C_D) 0.060 -0.565 sys_mngr/cipher_data_reg_reg[119]
|
| 1248 |
|
|
-------------------------------------------------------------------
|
| 1249 |
|
|
required time 0.565
|
| 1250 |
|
|
arrival time -0.453
|
| 1251 |
|
|
-------------------------------------------------------------------
|
| 1252 |
|
|
slack 0.112
|
| 1253 |
|
|
|
| 1254 |
|
|
Slack (MET) : 0.114ns (arrival time - required time)
|
| 1255 |
|
|
Source: sys_mngr/cur_stat_reg_reg[3]/C
|
| 1256 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1257 |
|
|
Destination: sys_mngr/axi_data_wr_reg_reg[3]/D
|
| 1258 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1259 |
|
|
Path Group: clk_gen
|
| 1260 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 1261 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 1262 |
|
|
Data Path Delay: 0.185ns (logic 0.128ns (69.375%) route 0.057ns (30.625%))
|
| 1263 |
|
|
Logic Levels: 1 (LUT6=1)
|
| 1264 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 1265 |
|
|
Destination Clock Delay (DCD): -0.689ns
|
| 1266 |
|
|
Source Clock Delay (SCD): -0.639ns
|
| 1267 |
|
|
Clock Pessimism Removal (CPR): -0.062ns
|
| 1268 |
|
|
|
| 1269 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1270 |
|
|
------------------------------------------------------------------- -------------------
|
| 1271 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1272 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1273 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1274 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1275 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1276 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1277 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1278 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1279 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1280 |
|
|
net (fo=982, routed) 0.565 -0.639 sys_mngr/clk_out1
|
| 1281 |
|
|
SLICE_X27Y231 FDCE r sys_mngr/cur_stat_reg_reg[3]/C
|
| 1282 |
|
|
------------------------------------------------------------------- -------------------
|
| 1283 |
|
|
SLICE_X27Y231 FDCE (Prop_fdce_C_Q) 0.100 -0.539 r sys_mngr/cur_stat_reg_reg[3]/Q
|
| 1284 |
|
|
net (fo=1, routed) 0.057 -0.482 sys_mngr/cur_stat_reg[3]
|
| 1285 |
|
|
SLICE_X26Y231 LUT6 (Prop_lut6_I1_O) 0.028 -0.454 r sys_mngr/axi_data_wr_reg[3]_i_1/O
|
| 1286 |
|
|
net (fo=1, routed) 0.000 -0.454 sys_mngr/axi_data_wr[3]
|
| 1287 |
|
|
SLICE_X26Y231 FDCE r sys_mngr/axi_data_wr_reg_reg[3]/D
|
| 1288 |
|
|
------------------------------------------------------------------- -------------------
|
| 1289 |
|
|
|
| 1290 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1291 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1292 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1293 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1294 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1295 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1296 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1297 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1298 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1299 |
|
|
net (fo=982, routed) 0.768 -0.689 sys_mngr/clk_out1
|
| 1300 |
|
|
SLICE_X26Y231 FDCE r sys_mngr/axi_data_wr_reg_reg[3]/C
|
| 1301 |
|
|
clock pessimism 0.062 -0.628
|
| 1302 |
|
|
SLICE_X26Y231 FDCE (Hold_fdce_C_D) 0.060 -0.568 sys_mngr/axi_data_wr_reg_reg[3]
|
| 1303 |
|
|
-------------------------------------------------------------------
|
| 1304 |
|
|
required time 0.568
|
| 1305 |
|
|
arrival time -0.454
|
| 1306 |
|
|
-------------------------------------------------------------------
|
| 1307 |
|
|
slack 0.114
|
| 1308 |
|
|
|
| 1309 |
|
|
Slack (MET) : 0.114ns (arrival time - required time)
|
| 1310 |
|
|
Source: uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL[2].fifo_din_reg[2]/C
|
| 1311 |
|
|
(rising edge-triggered cell FDRE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1312 |
|
|
Destination: uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16/D
|
| 1313 |
|
|
(rising edge-triggered cell SRL16E clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1314 |
|
|
Path Group: clk_gen
|
| 1315 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 1316 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 1317 |
|
|
Data Path Delay: 0.240ns (logic 0.118ns (49.264%) route 0.122ns (50.736%))
|
| 1318 |
|
|
Logic Levels: 0
|
| 1319 |
|
|
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
|
| 1320 |
|
|
Destination Clock Delay (DCD): -0.692ns
|
| 1321 |
|
|
Source Clock Delay (SCD): -0.640ns
|
| 1322 |
|
|
Clock Pessimism Removal (CPR): -0.081ns
|
| 1323 |
|
|
|
| 1324 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1325 |
|
|
------------------------------------------------------------------- -------------------
|
| 1326 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1327 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1328 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1329 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1330 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1331 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1332 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1333 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1334 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1335 |
|
|
net (fo=982, routed) 0.564 -0.640 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/s_axi_aclk
|
| 1336 |
|
|
SLICE_X20Y226 FDRE r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL[2].fifo_din_reg[2]/C
|
| 1337 |
|
|
------------------------------------------------------------------- -------------------
|
| 1338 |
|
|
SLICE_X20Y226 FDRE (Prop_fdre_C_Q) 0.118 -0.522 r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL[2].fifo_din_reg[2]/Q
|
| 1339 |
|
|
net (fo=3, routed) 0.122 -0.400 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[1]
|
| 1340 |
|
|
SLICE_X22Y226 SRL16E r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16/D
|
| 1341 |
|
|
------------------------------------------------------------------- -------------------
|
| 1342 |
|
|
|
| 1343 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1344 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1345 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1346 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1347 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1348 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1349 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1350 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1351 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1352 |
|
|
net (fo=982, routed) 0.765 -0.692 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/s_axi_aclk
|
| 1353 |
|
|
SLICE_X22Y226 SRL16E r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16/CLK
|
| 1354 |
|
|
clock pessimism 0.081 -0.612
|
| 1355 |
|
|
SLICE_X22Y226 SRL16E (Hold_srl16e_CLK_D)
|
| 1356 |
|
|
0.098 -0.514 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16
|
| 1357 |
|
|
-------------------------------------------------------------------
|
| 1358 |
|
|
required time 0.514
|
| 1359 |
|
|
arrival time -0.400
|
| 1360 |
|
|
-------------------------------------------------------------------
|
| 1361 |
|
|
slack 0.114
|
| 1362 |
|
|
|
| 1363 |
|
|
Slack (MET) : 0.114ns (arrival time - required time)
|
| 1364 |
|
|
Source: sys_mngr/cur_stat_reg_reg[2]/C
|
| 1365 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1366 |
|
|
Destination: sys_mngr/axi_data_wr_reg_reg[2]/D
|
| 1367 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1368 |
|
|
Path Group: clk_gen
|
| 1369 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 1370 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 1371 |
|
|
Data Path Delay: 0.186ns (logic 0.128ns (68.676%) route 0.058ns (31.324%))
|
| 1372 |
|
|
Logic Levels: 1 (LUT6=1)
|
| 1373 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 1374 |
|
|
Destination Clock Delay (DCD): -0.689ns
|
| 1375 |
|
|
Source Clock Delay (SCD): -0.639ns
|
| 1376 |
|
|
Clock Pessimism Removal (CPR): -0.062ns
|
| 1377 |
|
|
|
| 1378 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1379 |
|
|
------------------------------------------------------------------- -------------------
|
| 1380 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1381 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1382 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1383 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1384 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1385 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1386 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1387 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1388 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1389 |
|
|
net (fo=982, routed) 0.565 -0.639 sys_mngr/clk_out1
|
| 1390 |
|
|
SLICE_X27Y231 FDCE r sys_mngr/cur_stat_reg_reg[2]/C
|
| 1391 |
|
|
------------------------------------------------------------------- -------------------
|
| 1392 |
|
|
SLICE_X27Y231 FDCE (Prop_fdce_C_Q) 0.100 -0.539 r sys_mngr/cur_stat_reg_reg[2]/Q
|
| 1393 |
|
|
net (fo=1, routed) 0.058 -0.480 sys_mngr/cur_stat_reg[2]
|
| 1394 |
|
|
SLICE_X26Y231 LUT6 (Prop_lut6_I1_O) 0.028 -0.452 r sys_mngr/axi_data_wr_reg[2]_i_1/O
|
| 1395 |
|
|
net (fo=1, routed) 0.000 -0.452 sys_mngr/axi_data_wr[2]
|
| 1396 |
|
|
SLICE_X26Y231 FDCE r sys_mngr/axi_data_wr_reg_reg[2]/D
|
| 1397 |
|
|
------------------------------------------------------------------- -------------------
|
| 1398 |
|
|
|
| 1399 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1400 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1401 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1402 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1403 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1404 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1405 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1406 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1407 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1408 |
|
|
net (fo=982, routed) 0.768 -0.689 sys_mngr/clk_out1
|
| 1409 |
|
|
SLICE_X26Y231 FDCE r sys_mngr/axi_data_wr_reg_reg[2]/C
|
| 1410 |
|
|
clock pessimism 0.062 -0.628
|
| 1411 |
|
|
SLICE_X26Y231 FDCE (Hold_fdce_C_D) 0.061 -0.567 sys_mngr/axi_data_wr_reg_reg[2]
|
| 1412 |
|
|
-------------------------------------------------------------------
|
| 1413 |
|
|
required time 0.567
|
| 1414 |
|
|
arrival time -0.452
|
| 1415 |
|
|
-------------------------------------------------------------------
|
| 1416 |
|
|
slack 0.114
|
| 1417 |
|
|
|
| 1418 |
|
|
Slack (MET) : 0.115ns (arrival time - required time)
|
| 1419 |
|
|
Source: uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL[7].fifo_din_reg[7]/C
|
| 1420 |
|
|
(rising edge-triggered cell FDRE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1421 |
|
|
Destination: uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16/D
|
| 1422 |
|
|
(rising edge-triggered cell SRL16E clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1423 |
|
|
Path Group: clk_gen
|
| 1424 |
|
|
Path Type: Hold (Min at Fast Process Corner)
|
| 1425 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 1426 |
|
|
Data Path Delay: 0.237ns (logic 0.118ns (49.866%) route 0.119ns (50.134%))
|
| 1427 |
|
|
Logic Levels: 0
|
| 1428 |
|
|
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
|
| 1429 |
|
|
Destination Clock Delay (DCD): -0.692ns
|
| 1430 |
|
|
Source Clock Delay (SCD): -0.640ns
|
| 1431 |
|
|
Clock Pessimism Removal (CPR): -0.081ns
|
| 1432 |
|
|
|
| 1433 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1434 |
|
|
------------------------------------------------------------------- -------------------
|
| 1435 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1436 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1437 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1438 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 1439 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 1440 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1441 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1442 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 1443 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 1444 |
|
|
net (fo=982, routed) 0.564 -0.640 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/s_axi_aclk
|
| 1445 |
|
|
SLICE_X20Y226 FDRE r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL[7].fifo_din_reg[7]/C
|
| 1446 |
|
|
------------------------------------------------------------------- -------------------
|
| 1447 |
|
|
SLICE_X20Y226 FDRE (Prop_fdre_C_Q) 0.118 -0.522 r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL[7].fifo_din_reg[7]/Q
|
| 1448 |
|
|
net (fo=3, routed) 0.119 -0.403 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[6]
|
| 1449 |
|
|
SLICE_X22Y226 SRL16E r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16/D
|
| 1450 |
|
|
------------------------------------------------------------------- -------------------
|
| 1451 |
|
|
|
| 1452 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1453 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1454 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1455 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 1456 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 1457 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1458 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1459 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 1460 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 1461 |
|
|
net (fo=982, routed) 0.765 -0.692 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/s_axi_aclk
|
| 1462 |
|
|
SLICE_X22Y226 SRL16E r uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16/CLK
|
| 1463 |
|
|
clock pessimism 0.081 -0.612
|
| 1464 |
|
|
SLICE_X22Y226 SRL16E (Hold_srl16e_CLK_D)
|
| 1465 |
|
|
0.094 -0.518 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16
|
| 1466 |
|
|
-------------------------------------------------------------------
|
| 1467 |
|
|
required time 0.518
|
| 1468 |
|
|
arrival time -0.403
|
| 1469 |
|
|
-------------------------------------------------------------------
|
| 1470 |
|
|
slack 0.115
|
| 1471 |
|
|
|
| 1472 |
|
|
|
| 1473 |
|
|
|
| 1474 |
|
|
|
| 1475 |
|
|
|
| 1476 |
|
|
Pulse Width Checks
|
| 1477 |
|
|
--------------------------------------------------------------------------------------
|
| 1478 |
|
|
Clock Name: clk_gen
|
| 1479 |
|
|
Waveform(ns): { 0.000 5.000 }
|
| 1480 |
|
|
Period(ns): 10.000
|
| 1481 |
|
|
Sources: { clkgen/clk_out1 }
|
| 1482 |
|
|
|
| 1483 |
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
| 1484 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X0Y50 clk_div_reg[1]/C
|
| 1485 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X27Y231 sys_mngr/cur_stat_reg_reg[5]/C
|
| 1486 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X27Y231 sys_mngr/cur_stat_reg_reg[6]/C
|
| 1487 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X27Y231 sys_mngr/cur_stat_reg_reg[7]/C
|
| 1488 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X26Y228 sys_mngr/m_axi\\.wdata_reg[3]/C
|
| 1489 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X26Y228 sys_mngr/m_axi\\.wdata_reg[6]/C
|
| 1490 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X26Y229 sys_mngr/m_axi\\.wdata_reg[7]/C
|
| 1491 |
|
|
Min Period n/a FDRE/C n/a 0.750 10.000 9.250 SLICE_X25Y226 uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]/C
|
| 1492 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X33Y255 sys_mngr/key_o_reg[102]/C
|
| 1493 |
|
|
Min Period n/a FDCE/C n/a 0.750 10.000 9.250 SLICE_X26Y255 sys_mngr/key_o_reg[104]/C
|
| 1494 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y224 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15/CLK
|
| 1495 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y224 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15/CLK
|
| 1496 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16/CLK
|
| 1497 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16/CLK
|
| 1498 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16/CLK
|
| 1499 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16/CLK
|
| 1500 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK
|
| 1501 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16/CLK
|
| 1502 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16/CLK
|
| 1503 |
|
|
Low Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16/CLK
|
| 1504 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y224 uartlite/U0/UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15/CLK
|
| 1505 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y224 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15/CLK
|
| 1506 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16/CLK
|
| 1507 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16/CLK
|
| 1508 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16/CLK
|
| 1509 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16/CLK
|
| 1510 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK
|
| 1511 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16/CLK
|
| 1512 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16/CLK
|
| 1513 |
|
|
High Pulse Width Slow SRL16E/CLK n/a 0.642 5.000 4.358 SLICE_X22Y225 uartlite/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16/CLK
|
| 1514 |
|
|
|
| 1515 |
|
|
|
| 1516 |
|
|
|
| 1517 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1518 |
|
|
From Clock: clk_out1_clk_gen
|
| 1519 |
|
|
To Clock: clk_out1_clk_gen
|
| 1520 |
|
|
|
| 1521 |
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
| 1522 |
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
| 1523 |
|
|
PW : 0 Failing Endpoints, Worst Slack 8.592ns, Total Violation 0.000ns
|
| 1524 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1525 |
|
|
|
| 1526 |
|
|
|
| 1527 |
|
|
Pulse Width Checks
|
| 1528 |
|
|
--------------------------------------------------------------------------------------
|
| 1529 |
|
|
Clock Name: clk_out1_clk_gen
|
| 1530 |
|
|
Waveform(ns): { 0.000 5.000 }
|
| 1531 |
|
|
Period(ns): 10.000
|
| 1532 |
|
|
Sources: { clkgen/inst/mmcm_adv_inst/CLKOUT0 }
|
| 1533 |
|
|
|
| 1534 |
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
| 1535 |
|
|
Min Period n/a BUFG/I n/a 1.409 10.000 8.592 BUFGCTRL_X0Y0 clkgen/inst/clkout1_buf/I
|
| 1536 |
|
|
Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.071 10.000 8.929 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1537 |
|
|
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1538 |
|
|
|
| 1539 |
|
|
|
| 1540 |
|
|
|
| 1541 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1542 |
|
|
From Clock: clkfbout_clk_gen
|
| 1543 |
|
|
To Clock: clkfbout_clk_gen
|
| 1544 |
|
|
|
| 1545 |
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
| 1546 |
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
| 1547 |
|
|
PW : 0 Failing Endpoints, Worst Slack 3.592ns, Total Violation 0.000ns
|
| 1548 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1549 |
|
|
|
| 1550 |
|
|
|
| 1551 |
|
|
Pulse Width Checks
|
| 1552 |
|
|
--------------------------------------------------------------------------------------
|
| 1553 |
|
|
Clock Name: clkfbout_clk_gen
|
| 1554 |
|
|
Waveform(ns): { 0.000 2.500 }
|
| 1555 |
|
|
Period(ns): 5.000
|
| 1556 |
|
|
Sources: { clkgen/inst/mmcm_adv_inst/CLKFBOUT }
|
| 1557 |
|
|
|
| 1558 |
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
| 1559 |
|
|
Min Period n/a BUFG/I n/a 1.409 5.000 3.592 BUFGCTRL_X0Y1 clkgen/inst/clkf_buf/I
|
| 1560 |
|
|
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.071 5.000 3.929 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKFBOUT
|
| 1561 |
|
|
Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.071 5.000 3.929 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKFBIN
|
| 1562 |
|
|
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 5.000 95.000 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKFBIN
|
| 1563 |
|
|
Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y1 clkgen/inst/mmcm_adv_inst/CLKFBOUT
|
| 1564 |
|
|
|
| 1565 |
|
|
|
| 1566 |
|
|
|
| 1567 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1568 |
|
|
Path Group: **async_default**
|
| 1569 |
|
|
From Clock: clk_gen
|
| 1570 |
|
|
To Clock: clk_gen
|
| 1571 |
|
|
|
| 1572 |
|
|
Setup : 0 Failing Endpoints, Worst Slack 7.429ns, Total Violation 0.000ns
|
| 1573 |
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.472ns, Total Violation 0.000ns
|
| 1574 |
|
|
---------------------------------------------------------------------------------------------------
|
| 1575 |
|
|
|
| 1576 |
|
|
|
| 1577 |
|
|
Max Delay Paths
|
| 1578 |
|
|
--------------------------------------------------------------------------------------
|
| 1579 |
|
|
Slack (MET) : 7.429ns (required time - arrival time)
|
| 1580 |
|
|
Source: sys_mngr/axi_state_reg[1]_C/C
|
| 1581 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1582 |
|
|
Destination: sys_mngr/axi_state_reg[10]_C/CLR
|
| 1583 |
|
|
(recovery check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1584 |
|
|
Path Group: **async_default**
|
| 1585 |
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
| 1586 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 1587 |
|
|
Data Path Delay: 2.246ns (logic 0.388ns (17.276%) route 1.858ns (82.724%))
|
| 1588 |
|
|
Logic Levels: 3 (LUT3=2 LUT6=1)
|
| 1589 |
|
|
Clock Path Skew: -0.047ns (DCD - SCD + CPR)
|
| 1590 |
|
|
Destination Clock Delay (DCD): -1.814ns = ( 8.186 - 10.000 )
|
| 1591 |
|
|
Source Clock Delay (SCD): -2.374ns
|
| 1592 |
|
|
Clock Pessimism Removal (CPR): -0.608ns
|
| 1593 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 1594 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 1595 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 1596 |
|
|
Phase Error (PE): 0.000ns
|
| 1597 |
|
|
|
| 1598 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1599 |
|
|
------------------------------------------------------------------- -------------------
|
| 1600 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1601 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1602 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1603 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 1604 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 1605 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1606 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1607 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 1608 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 1609 |
|
|
net (fo=982, routed) 1.276 -2.374 sys_mngr/clk_out1
|
| 1610 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 1611 |
|
|
------------------------------------------------------------------- -------------------
|
| 1612 |
|
|
SLICE_X22Y229 FDCE (Prop_fdce_C_Q) 0.259 -2.115 r sys_mngr/axi_state_reg[1]_C/Q
|
| 1613 |
|
|
net (fo=7, routed) 0.509 -1.606 sys_mngr/axi_state_reg[1]_C_n_0
|
| 1614 |
|
|
SLICE_X25Y228 LUT3 (Prop_lut3_I2_O) 0.043 -1.563 r sys_mngr/axi_state[0]_P_i_10/O
|
| 1615 |
|
|
net (fo=9, routed) 0.558 -1.006 sys_mngr/axi_state[1]
|
| 1616 |
|
|
SLICE_X25Y230 LUT6 (Prop_lut6_I5_O) 0.043 -0.963 r sys_mngr/axi_state[10]_P_i_1/O
|
| 1617 |
|
|
net (fo=9, routed) 0.481 -0.482 sys_mngr/axi_state[10]_P_i_1_n_0
|
| 1618 |
|
|
SLICE_X24Y229 LUT3 (Prop_lut3_I0_O) 0.043 -0.439 f sys_mngr/axi_state_reg[10]_LDC_i_1/O
|
| 1619 |
|
|
net (fo=2, routed) 0.310 -0.129 sys_mngr/axi_state_reg[10]_LDC_i_1_n_0
|
| 1620 |
|
|
SLICE_X24Y230 FDCE f sys_mngr/axi_state_reg[10]_C/CLR
|
| 1621 |
|
|
------------------------------------------------------------------- -------------------
|
| 1622 |
|
|
|
| 1623 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 1624 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 1625 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 1626 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 1627 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 1628 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1629 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1630 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 1631 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 1632 |
|
|
net (fo=982, routed) 1.136 8.186 sys_mngr/clk_out1
|
| 1633 |
|
|
SLICE_X24Y230 FDCE r sys_mngr/axi_state_reg[10]_C/C
|
| 1634 |
|
|
clock pessimism -0.608 7.579
|
| 1635 |
|
|
clock uncertainty -0.066 7.512
|
| 1636 |
|
|
SLICE_X24Y230 FDCE (Recov_fdce_C_CLR) -0.212 7.300 sys_mngr/axi_state_reg[10]_C
|
| 1637 |
|
|
-------------------------------------------------------------------
|
| 1638 |
|
|
required time 7.300
|
| 1639 |
|
|
arrival time 0.129
|
| 1640 |
|
|
-------------------------------------------------------------------
|
| 1641 |
|
|
slack 7.429
|
| 1642 |
|
|
|
| 1643 |
|
|
Slack (MET) : 7.441ns (required time - arrival time)
|
| 1644 |
|
|
Source: sys_mngr/axi_state_reg[1]_C/C
|
| 1645 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1646 |
|
|
Destination: sys_mngr/axi_state_reg[10]_P/PRE
|
| 1647 |
|
|
(recovery check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1648 |
|
|
Path Group: **async_default**
|
| 1649 |
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
| 1650 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 1651 |
|
|
Data Path Delay: 2.264ns (logic 0.388ns (17.137%) route 1.876ns (82.863%))
|
| 1652 |
|
|
Logic Levels: 3 (LUT3=2 LUT6=1)
|
| 1653 |
|
|
Clock Path Skew: -0.050ns (DCD - SCD + CPR)
|
| 1654 |
|
|
Destination Clock Delay (DCD): -1.817ns = ( 8.183 - 10.000 )
|
| 1655 |
|
|
Source Clock Delay (SCD): -2.374ns
|
| 1656 |
|
|
Clock Pessimism Removal (CPR): -0.608ns
|
| 1657 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 1658 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 1659 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 1660 |
|
|
Phase Error (PE): 0.000ns
|
| 1661 |
|
|
|
| 1662 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1663 |
|
|
------------------------------------------------------------------- -------------------
|
| 1664 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1665 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1666 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1667 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 1668 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 1669 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1670 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1671 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 1672 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 1673 |
|
|
net (fo=982, routed) 1.276 -2.374 sys_mngr/clk_out1
|
| 1674 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 1675 |
|
|
------------------------------------------------------------------- -------------------
|
| 1676 |
|
|
SLICE_X22Y229 FDCE (Prop_fdce_C_Q) 0.259 -2.115 f sys_mngr/axi_state_reg[1]_C/Q
|
| 1677 |
|
|
net (fo=7, routed) 0.509 -1.606 sys_mngr/axi_state_reg[1]_C_n_0
|
| 1678 |
|
|
SLICE_X25Y228 LUT3 (Prop_lut3_I2_O) 0.043 -1.563 f sys_mngr/axi_state[0]_P_i_10/O
|
| 1679 |
|
|
net (fo=9, routed) 0.558 -1.006 sys_mngr/axi_state[1]
|
| 1680 |
|
|
SLICE_X25Y230 LUT6 (Prop_lut6_I5_O) 0.043 -0.963 f sys_mngr/axi_state[10]_P_i_1/O
|
| 1681 |
|
|
net (fo=9, routed) 0.224 -0.739 sys_mngr/axi_state[10]_P_i_1_n_0
|
| 1682 |
|
|
SLICE_X24Y228 LUT3 (Prop_lut3_I0_O) 0.043 -0.696 f sys_mngr/axi_state[10]_P_i_2/O
|
| 1683 |
|
|
net (fo=2, routed) 0.585 -0.110 sys_mngr/axi_state[10]_P_i_2_n_0
|
| 1684 |
|
|
SLICE_X24Y228 FDPE f sys_mngr/axi_state_reg[10]_P/PRE
|
| 1685 |
|
|
------------------------------------------------------------------- -------------------
|
| 1686 |
|
|
|
| 1687 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 1688 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 1689 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 1690 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 1691 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 1692 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1693 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1694 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 1695 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 1696 |
|
|
net (fo=982, routed) 1.133 8.183 sys_mngr/clk_out1
|
| 1697 |
|
|
SLICE_X24Y228 FDPE r sys_mngr/axi_state_reg[10]_P/C
|
| 1698 |
|
|
clock pessimism -0.608 7.576
|
| 1699 |
|
|
clock uncertainty -0.066 7.509
|
| 1700 |
|
|
SLICE_X24Y228 FDPE (Recov_fdpe_C_PRE) -0.178 7.331 sys_mngr/axi_state_reg[10]_P
|
| 1701 |
|
|
-------------------------------------------------------------------
|
| 1702 |
|
|
required time 7.331
|
| 1703 |
|
|
arrival time 0.110
|
| 1704 |
|
|
-------------------------------------------------------------------
|
| 1705 |
|
|
slack 7.441
|
| 1706 |
|
|
|
| 1707 |
|
|
Slack (MET) : 7.514ns (required time - arrival time)
|
| 1708 |
|
|
Source: uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]/C
|
| 1709 |
|
|
(rising edge-triggered cell FDRE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1710 |
|
|
Destination: sys_mngr/axi_state_reg[2]_P/PRE
|
| 1711 |
|
|
(recovery check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1712 |
|
|
Path Group: **async_default**
|
| 1713 |
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
| 1714 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 1715 |
|
|
Data Path Delay: 2.225ns (logic 0.457ns (20.535%) route 1.768ns (79.465%))
|
| 1716 |
|
|
Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1)
|
| 1717 |
|
|
Clock Path Skew: -0.016ns (DCD - SCD + CPR)
|
| 1718 |
|
|
Destination Clock Delay (DCD): -1.814ns = ( 8.186 - 10.000 )
|
| 1719 |
|
|
Source Clock Delay (SCD): -2.382ns
|
| 1720 |
|
|
Clock Pessimism Removal (CPR): -0.585ns
|
| 1721 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 1722 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 1723 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 1724 |
|
|
Phase Error (PE): 0.000ns
|
| 1725 |
|
|
|
| 1726 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1727 |
|
|
------------------------------------------------------------------- -------------------
|
| 1728 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1729 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1730 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1731 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 1732 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 1733 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1734 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1735 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 1736 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 1737 |
|
|
net (fo=982, routed) 1.268 -2.382 uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_aclk
|
| 1738 |
|
|
SLICE_X25Y226 FDRE r uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]/C
|
| 1739 |
|
|
------------------------------------------------------------------- -------------------
|
| 1740 |
|
|
SLICE_X25Y226 FDRE (Prop_fdre_C_Q) 0.223 -2.159 f uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]/Q
|
| 1741 |
|
|
net (fo=8, routed) 0.584 -1.576 uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0
|
| 1742 |
|
|
SLICE_X25Y227 LUT5 (Prop_lut5_I3_O) 0.054 -1.522 f uartlite/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_arready_INST_0/O
|
| 1743 |
|
|
net (fo=6, routed) 0.444 -1.077 sys_mngr/s_axi_arready
|
| 1744 |
|
|
SLICE_X24Y229 LUT6 (Prop_lut6_I1_O) 0.137 -0.940 f sys_mngr/axi_state[2]_P_i_1/O
|
| 1745 |
|
|
net (fo=3, routed) 0.248 -0.693 sys_mngr/axi_state[2]_P_i_1_n_0
|
| 1746 |
|
|
SLICE_X24Y230 LUT3 (Prop_lut3_I0_O) 0.043 -0.650 f sys_mngr/axi_state[2]_P_i_2/O
|
| 1747 |
|
|
net (fo=2, routed) 0.493 -0.157 sys_mngr/axi_state[2]_P_i_2_n_0
|
| 1748 |
|
|
SLICE_X25Y230 FDPE f sys_mngr/axi_state_reg[2]_P/PRE
|
| 1749 |
|
|
------------------------------------------------------------------- -------------------
|
| 1750 |
|
|
|
| 1751 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 1752 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 1753 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 1754 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 1755 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 1756 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1757 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1758 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 1759 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 1760 |
|
|
net (fo=982, routed) 1.136 8.186 sys_mngr/clk_out1
|
| 1761 |
|
|
SLICE_X25Y230 FDPE r sys_mngr/axi_state_reg[2]_P/C
|
| 1762 |
|
|
clock pessimism -0.585 7.602
|
| 1763 |
|
|
clock uncertainty -0.066 7.535
|
| 1764 |
|
|
SLICE_X25Y230 FDPE (Recov_fdpe_C_PRE) -0.178 7.357 sys_mngr/axi_state_reg[2]_P
|
| 1765 |
|
|
-------------------------------------------------------------------
|
| 1766 |
|
|
required time 7.357
|
| 1767 |
|
|
arrival time 0.157
|
| 1768 |
|
|
-------------------------------------------------------------------
|
| 1769 |
|
|
slack 7.514
|
| 1770 |
|
|
|
| 1771 |
|
|
Slack (MET) : 7.684ns (required time - arrival time)
|
| 1772 |
|
|
Source: sys_mngr/axi_state_reg[1]_C/C
|
| 1773 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1774 |
|
|
Destination: sys_mngr/axi_state_reg[2]_C/CLR
|
| 1775 |
|
|
(recovery check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1776 |
|
|
Path Group: **async_default**
|
| 1777 |
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
| 1778 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 1779 |
|
|
Data Path Delay: 1.990ns (logic 0.388ns (19.502%) route 1.602ns (80.498%))
|
| 1780 |
|
|
Logic Levels: 3 (LUT3=1 LUT6=2)
|
| 1781 |
|
|
Clock Path Skew: -0.048ns (DCD - SCD + CPR)
|
| 1782 |
|
|
Destination Clock Delay (DCD): -1.815ns = ( 8.185 - 10.000 )
|
| 1783 |
|
|
Source Clock Delay (SCD): -2.374ns
|
| 1784 |
|
|
Clock Pessimism Removal (CPR): -0.608ns
|
| 1785 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 1786 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 1787 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 1788 |
|
|
Phase Error (PE): 0.000ns
|
| 1789 |
|
|
|
| 1790 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1791 |
|
|
------------------------------------------------------------------- -------------------
|
| 1792 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1793 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1794 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1795 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 1796 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 1797 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1798 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1799 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 1800 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 1801 |
|
|
net (fo=982, routed) 1.276 -2.374 sys_mngr/clk_out1
|
| 1802 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 1803 |
|
|
------------------------------------------------------------------- -------------------
|
| 1804 |
|
|
SLICE_X22Y229 FDCE (Prop_fdce_C_Q) 0.259 -2.115 r sys_mngr/axi_state_reg[1]_C/Q
|
| 1805 |
|
|
net (fo=7, routed) 0.509 -1.606 sys_mngr/axi_state_reg[1]_C_n_0
|
| 1806 |
|
|
SLICE_X25Y228 LUT3 (Prop_lut3_I2_O) 0.043 -1.563 r sys_mngr/axi_state[0]_P_i_10/O
|
| 1807 |
|
|
net (fo=9, routed) 0.558 -1.006 sys_mngr/axi_state[1]
|
| 1808 |
|
|
SLICE_X25Y230 LUT6 (Prop_lut6_I5_O) 0.043 -0.963 r sys_mngr/axi_state[10]_P_i_1/O
|
| 1809 |
|
|
net (fo=9, routed) 0.225 -0.738 sys_mngr/axi_state[10]_P_i_1_n_0
|
| 1810 |
|
|
SLICE_X24Y228 LUT6 (Prop_lut6_I4_O) 0.043 -0.695 f sys_mngr/axi_state_reg[2]_LDC_i_1/O
|
| 1811 |
|
|
net (fo=2, routed) 0.310 -0.385 sys_mngr/axi_state_reg[2]_LDC_i_1_n_0
|
| 1812 |
|
|
SLICE_X25Y229 FDCE f sys_mngr/axi_state_reg[2]_C/CLR
|
| 1813 |
|
|
------------------------------------------------------------------- -------------------
|
| 1814 |
|
|
|
| 1815 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 1816 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 1817 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 1818 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 1819 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 1820 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1821 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1822 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 1823 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 1824 |
|
|
net (fo=982, routed) 1.135 8.185 sys_mngr/clk_out1
|
| 1825 |
|
|
SLICE_X25Y229 FDCE r sys_mngr/axi_state_reg[2]_C/C
|
| 1826 |
|
|
clock pessimism -0.608 7.578
|
| 1827 |
|
|
clock uncertainty -0.066 7.511
|
| 1828 |
|
|
SLICE_X25Y229 FDCE (Recov_fdce_C_CLR) -0.212 7.299 sys_mngr/axi_state_reg[2]_C
|
| 1829 |
|
|
-------------------------------------------------------------------
|
| 1830 |
|
|
required time 7.299
|
| 1831 |
|
|
arrival time 0.385
|
| 1832 |
|
|
-------------------------------------------------------------------
|
| 1833 |
|
|
slack 7.684
|
| 1834 |
|
|
|
| 1835 |
|
|
Slack (MET) : 7.804ns (required time - arrival time)
|
| 1836 |
|
|
Source: sys_mngr/axi_state_reg[1]_C/C
|
| 1837 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1838 |
|
|
Destination: sys_mngr/axi_state_reg[1]_C/CLR
|
| 1839 |
|
|
(recovery check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1840 |
|
|
Path Group: **async_default**
|
| 1841 |
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
| 1842 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 1843 |
|
|
Data Path Delay: 1.975ns (logic 0.388ns (19.642%) route 1.587ns (80.358%))
|
| 1844 |
|
|
Logic Levels: 3 (LUT3=1 LUT6=2)
|
| 1845 |
|
|
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
|
| 1846 |
|
|
Destination Clock Delay (DCD): -1.811ns = ( 8.189 - 10.000 )
|
| 1847 |
|
|
Source Clock Delay (SCD): -2.374ns
|
| 1848 |
|
|
Clock Pessimism Removal (CPR): -0.564ns
|
| 1849 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 1850 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 1851 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 1852 |
|
|
Phase Error (PE): 0.000ns
|
| 1853 |
|
|
|
| 1854 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1855 |
|
|
------------------------------------------------------------------- -------------------
|
| 1856 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1857 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1858 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1859 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 1860 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 1861 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1862 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1863 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 1864 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 1865 |
|
|
net (fo=982, routed) 1.276 -2.374 sys_mngr/clk_out1
|
| 1866 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 1867 |
|
|
------------------------------------------------------------------- -------------------
|
| 1868 |
|
|
SLICE_X22Y229 FDCE (Prop_fdce_C_Q) 0.259 -2.115 r sys_mngr/axi_state_reg[1]_C/Q
|
| 1869 |
|
|
net (fo=7, routed) 0.509 -1.606 sys_mngr/axi_state_reg[1]_C_n_0
|
| 1870 |
|
|
SLICE_X25Y228 LUT3 (Prop_lut3_I2_O) 0.043 -1.563 r sys_mngr/axi_state[0]_P_i_10/O
|
| 1871 |
|
|
net (fo=9, routed) 0.377 -1.186 sys_mngr/axi_state[1]
|
| 1872 |
|
|
SLICE_X25Y229 LUT6 (Prop_lut6_I5_O) 0.043 -1.143 r sys_mngr/axi_state_reg[1]_LDC_i_2/O
|
| 1873 |
|
|
net (fo=1, routed) 0.358 -0.785 sys_mngr/axi_state_reg[1]_LDC_i_2_n_0
|
| 1874 |
|
|
SLICE_X24Y229 LUT6 (Prop_lut6_I0_O) 0.043 -0.742 f sys_mngr/axi_state_reg[1]_LDC_i_1/O
|
| 1875 |
|
|
net (fo=2, routed) 0.343 -0.399 sys_mngr/axi_state_reg[1]_LDC_i_1_n_0
|
| 1876 |
|
|
SLICE_X22Y229 FDCE f sys_mngr/axi_state_reg[1]_C/CLR
|
| 1877 |
|
|
------------------------------------------------------------------- -------------------
|
| 1878 |
|
|
|
| 1879 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 1880 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 1881 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 1882 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 1883 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 1884 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1885 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1886 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 1887 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 1888 |
|
|
net (fo=982, routed) 1.139 8.189 sys_mngr/clk_out1
|
| 1889 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 1890 |
|
|
clock pessimism -0.564 7.626
|
| 1891 |
|
|
clock uncertainty -0.066 7.559
|
| 1892 |
|
|
SLICE_X22Y229 FDCE (Recov_fdce_C_CLR) -0.154 7.405 sys_mngr/axi_state_reg[1]_C
|
| 1893 |
|
|
-------------------------------------------------------------------
|
| 1894 |
|
|
required time 7.405
|
| 1895 |
|
|
arrival time 0.399
|
| 1896 |
|
|
-------------------------------------------------------------------
|
| 1897 |
|
|
slack 7.804
|
| 1898 |
|
|
|
| 1899 |
|
|
Slack (MET) : 7.823ns (required time - arrival time)
|
| 1900 |
|
|
Source: sys_mngr/axi_state_reg[1]_C/C
|
| 1901 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1902 |
|
|
Destination: sys_mngr/axi_state_reg[0]_P/PRE
|
| 1903 |
|
|
(recovery check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1904 |
|
|
Path Group: **async_default**
|
| 1905 |
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
| 1906 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 1907 |
|
|
Data Path Delay: 1.883ns (logic 0.388ns (20.610%) route 1.495ns (79.390%))
|
| 1908 |
|
|
Logic Levels: 3 (LUT3=2 LUT6=1)
|
| 1909 |
|
|
Clock Path Skew: -0.050ns (DCD - SCD + CPR)
|
| 1910 |
|
|
Destination Clock Delay (DCD): -1.817ns = ( 8.183 - 10.000 )
|
| 1911 |
|
|
Source Clock Delay (SCD): -2.374ns
|
| 1912 |
|
|
Clock Pessimism Removal (CPR): -0.608ns
|
| 1913 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 1914 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 1915 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 1916 |
|
|
Phase Error (PE): 0.000ns
|
| 1917 |
|
|
|
| 1918 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1919 |
|
|
------------------------------------------------------------------- -------------------
|
| 1920 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1921 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1922 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1923 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 1924 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 1925 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1926 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1927 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 1928 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 1929 |
|
|
net (fo=982, routed) 1.276 -2.374 sys_mngr/clk_out1
|
| 1930 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 1931 |
|
|
------------------------------------------------------------------- -------------------
|
| 1932 |
|
|
SLICE_X22Y229 FDCE (Prop_fdce_C_Q) 0.259 -2.115 r sys_mngr/axi_state_reg[1]_C/Q
|
| 1933 |
|
|
net (fo=7, routed) 0.509 -1.606 sys_mngr/axi_state_reg[1]_C_n_0
|
| 1934 |
|
|
SLICE_X25Y228 LUT3 (Prop_lut3_I2_O) 0.043 -1.563 r sys_mngr/axi_state[0]_P_i_10/O
|
| 1935 |
|
|
net (fo=9, routed) 0.466 -1.097 sys_mngr/axi_state[1]
|
| 1936 |
|
|
SLICE_X25Y229 LUT6 (Prop_lut6_I5_O) 0.043 -1.054 f sys_mngr/axi_state[0]_P_i_2/O
|
| 1937 |
|
|
net (fo=4, routed) 0.278 -0.776 sys_mngr/axi_state[0]_P_i_2_n_0
|
| 1938 |
|
|
SLICE_X27Y228 LUT3 (Prop_lut3_I0_O) 0.043 -0.733 f sys_mngr/axi_state[0]_P_i_3/O
|
| 1939 |
|
|
net (fo=2, routed) 0.241 -0.492 sys_mngr/axi_state[0]_P_i_3_n_0
|
| 1940 |
|
|
SLICE_X27Y228 FDPE f sys_mngr/axi_state_reg[0]_P/PRE
|
| 1941 |
|
|
------------------------------------------------------------------- -------------------
|
| 1942 |
|
|
|
| 1943 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 1944 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 1945 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 1946 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 1947 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 1948 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1949 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1950 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 1951 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 1952 |
|
|
net (fo=982, routed) 1.133 8.183 sys_mngr/clk_out1
|
| 1953 |
|
|
SLICE_X27Y228 FDPE r sys_mngr/axi_state_reg[0]_P/C
|
| 1954 |
|
|
clock pessimism -0.608 7.576
|
| 1955 |
|
|
clock uncertainty -0.066 7.509
|
| 1956 |
|
|
SLICE_X27Y228 FDPE (Recov_fdpe_C_PRE) -0.178 7.331 sys_mngr/axi_state_reg[0]_P
|
| 1957 |
|
|
-------------------------------------------------------------------
|
| 1958 |
|
|
required time 7.331
|
| 1959 |
|
|
arrival time 0.492
|
| 1960 |
|
|
-------------------------------------------------------------------
|
| 1961 |
|
|
slack 7.823
|
| 1962 |
|
|
|
| 1963 |
|
|
Slack (MET) : 7.877ns (required time - arrival time)
|
| 1964 |
|
|
Source: sys_mngr/axi_state_reg[1]_C/C
|
| 1965 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1966 |
|
|
Destination: sys_mngr/axi_state_reg[0]_C/CLR
|
| 1967 |
|
|
(recovery check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 1968 |
|
|
Path Group: **async_default**
|
| 1969 |
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
| 1970 |
|
|
Requirement: 10.000ns (clk_gen rise@10.000ns - clk_gen rise@0.000ns)
|
| 1971 |
|
|
Data Path Delay: 1.796ns (logic 0.388ns (21.599%) route 1.408ns (78.401%))
|
| 1972 |
|
|
Logic Levels: 3 (LUT3=2 LUT6=1)
|
| 1973 |
|
|
Clock Path Skew: -0.048ns (DCD - SCD + CPR)
|
| 1974 |
|
|
Destination Clock Delay (DCD): -1.815ns = ( 8.185 - 10.000 )
|
| 1975 |
|
|
Source Clock Delay (SCD): -2.374ns
|
| 1976 |
|
|
Clock Pessimism Removal (CPR): -0.608ns
|
| 1977 |
|
|
Clock Uncertainty: 0.066ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
| 1978 |
|
|
Total System Jitter (TSJ): 0.071ns
|
| 1979 |
|
|
Discrete Jitter (DJ): 0.112ns
|
| 1980 |
|
|
Phase Error (PE): 0.000ns
|
| 1981 |
|
|
|
| 1982 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 1983 |
|
|
------------------------------------------------------------------- -------------------
|
| 1984 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 1985 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 1986 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 1987 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.832 0.832 r clkgen/inst/clkin1_ibufgds/O
|
| 1988 |
|
|
net (fo=1, routed) 1.081 1.913 clkgen/inst/clk_in1_clk_gen
|
| 1989 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 1990 |
|
|
-7.786 -5.873 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 1991 |
|
|
net (fo=1, routed) 2.130 -3.743 clkgen/inst/clk_out1_clk_gen
|
| 1992 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -3.650 r clkgen/inst/clkout1_buf/O
|
| 1993 |
|
|
net (fo=982, routed) 1.276 -2.374 sys_mngr/clk_out1
|
| 1994 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 1995 |
|
|
------------------------------------------------------------------- -------------------
|
| 1996 |
|
|
SLICE_X22Y229 FDCE (Prop_fdce_C_Q) 0.259 -2.115 r sys_mngr/axi_state_reg[1]_C/Q
|
| 1997 |
|
|
net (fo=7, routed) 0.509 -1.606 sys_mngr/axi_state_reg[1]_C_n_0
|
| 1998 |
|
|
SLICE_X25Y228 LUT3 (Prop_lut3_I2_O) 0.043 -1.563 r sys_mngr/axi_state[0]_P_i_10/O
|
| 1999 |
|
|
net (fo=9, routed) 0.466 -1.097 sys_mngr/axi_state[1]
|
| 2000 |
|
|
SLICE_X25Y229 LUT6 (Prop_lut6_I5_O) 0.043 -1.054 r sys_mngr/axi_state[0]_P_i_2/O
|
| 2001 |
|
|
net (fo=4, routed) 0.191 -0.862 sys_mngr/axi_state[0]_P_i_2_n_0
|
| 2002 |
|
|
SLICE_X27Y229 LUT3 (Prop_lut3_I2_O) 0.043 -0.819 f sys_mngr/axi_state_reg[0]_LDC_i_1/O
|
| 2003 |
|
|
net (fo=2, routed) 0.241 -0.578 sys_mngr/axi_state_reg[0]_LDC_i_1_n_0
|
| 2004 |
|
|
SLICE_X27Y229 FDCE f sys_mngr/axi_state_reg[0]_C/CLR
|
| 2005 |
|
|
------------------------------------------------------------------- -------------------
|
| 2006 |
|
|
|
| 2007 |
|
|
(clock clk_gen rise edge) 10.000 10.000 r
|
| 2008 |
|
|
AD12 0.000 10.000 r CLK_IN_P (IN)
|
| 2009 |
|
|
net (fo=0) 0.000 10.000 clkgen/inst/clk_in1_p
|
| 2010 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.735 10.735 r clkgen/inst/clkin1_ibufgds/O
|
| 2011 |
|
|
net (fo=1, routed) 0.986 11.721 clkgen/inst/clk_in1_clk_gen
|
| 2012 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2013 |
|
|
-6.759 4.962 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2014 |
|
|
net (fo=1, routed) 2.005 6.967 clkgen/inst/clk_out1_clk_gen
|
| 2015 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 7.050 r clkgen/inst/clkout1_buf/O
|
| 2016 |
|
|
net (fo=982, routed) 1.135 8.185 sys_mngr/clk_out1
|
| 2017 |
|
|
SLICE_X27Y229 FDCE r sys_mngr/axi_state_reg[0]_C/C
|
| 2018 |
|
|
clock pessimism -0.608 7.578
|
| 2019 |
|
|
clock uncertainty -0.066 7.511
|
| 2020 |
|
|
SLICE_X27Y229 FDCE (Recov_fdce_C_CLR) -0.212 7.299 sys_mngr/axi_state_reg[0]_C
|
| 2021 |
|
|
-------------------------------------------------------------------
|
| 2022 |
|
|
required time 7.299
|
| 2023 |
|
|
arrival time 0.578
|
| 2024 |
|
|
-------------------------------------------------------------------
|
| 2025 |
|
|
slack 7.877
|
| 2026 |
|
|
|
| 2027 |
|
|
|
| 2028 |
|
|
|
| 2029 |
|
|
|
| 2030 |
|
|
|
| 2031 |
|
|
Min Delay Paths
|
| 2032 |
|
|
--------------------------------------------------------------------------------------
|
| 2033 |
|
|
Slack (MET) : 0.472ns (arrival time - required time)
|
| 2034 |
|
|
Source: sys_mngr/axi_state_reg[10]_P/C
|
| 2035 |
|
|
(rising edge-triggered cell FDPE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2036 |
|
|
Destination: sys_mngr/axi_state_reg[1]_C/CLR
|
| 2037 |
|
|
(removal check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2038 |
|
|
Path Group: **async_default**
|
| 2039 |
|
|
Path Type: Removal (Min at Fast Process Corner)
|
| 2040 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 2041 |
|
|
Data Path Delay: 0.456ns (logic 0.128ns (28.096%) route 0.328ns (71.904%))
|
| 2042 |
|
|
Logic Levels: 1 (LUT6=1)
|
| 2043 |
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
| 2044 |
|
|
Destination Clock Delay (DCD): -0.688ns
|
| 2045 |
|
|
Source Clock Delay (SCD): -0.642ns
|
| 2046 |
|
|
Clock Pessimism Removal (CPR): -0.081ns
|
| 2047 |
|
|
|
| 2048 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 2049 |
|
|
------------------------------------------------------------------- -------------------
|
| 2050 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2051 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2052 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2053 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 2054 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 2055 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2056 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2057 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 2058 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 2059 |
|
|
net (fo=982, routed) 0.562 -0.642 sys_mngr/clk_out1
|
| 2060 |
|
|
SLICE_X24Y228 FDPE r sys_mngr/axi_state_reg[10]_P/C
|
| 2061 |
|
|
------------------------------------------------------------------- -------------------
|
| 2062 |
|
|
SLICE_X24Y228 FDPE (Prop_fdpe_C_Q) 0.100 -0.542 r sys_mngr/axi_state_reg[10]_P/Q
|
| 2063 |
|
|
net (fo=5, routed) 0.143 -0.399 sys_mngr/axi_state_reg[10]_P_n_0
|
| 2064 |
|
|
SLICE_X24Y229 LUT6 (Prop_lut6_I3_O) 0.028 -0.371 f sys_mngr/axi_state_reg[1]_LDC_i_1/O
|
| 2065 |
|
|
net (fo=2, routed) 0.185 -0.186 sys_mngr/axi_state_reg[1]_LDC_i_1_n_0
|
| 2066 |
|
|
SLICE_X22Y229 FDCE f sys_mngr/axi_state_reg[1]_C/CLR
|
| 2067 |
|
|
------------------------------------------------------------------- -------------------
|
| 2068 |
|
|
|
| 2069 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2070 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2071 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2072 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 2073 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 2074 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2075 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2076 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 2077 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 2078 |
|
|
net (fo=982, routed) 0.769 -0.688 sys_mngr/clk_out1
|
| 2079 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 2080 |
|
|
clock pessimism 0.081 -0.608
|
| 2081 |
|
|
SLICE_X22Y229 FDCE (Remov_fdce_C_CLR) -0.050 -0.658 sys_mngr/axi_state_reg[1]_C
|
| 2082 |
|
|
-------------------------------------------------------------------
|
| 2083 |
|
|
required time 0.658
|
| 2084 |
|
|
arrival time -0.186
|
| 2085 |
|
|
-------------------------------------------------------------------
|
| 2086 |
|
|
slack 0.472
|
| 2087 |
|
|
|
| 2088 |
|
|
Slack (MET) : 0.552ns (arrival time - required time)
|
| 2089 |
|
|
Source: sys_mngr/axi_state_reg[10]_P/C
|
| 2090 |
|
|
(rising edge-triggered cell FDPE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2091 |
|
|
Destination: sys_mngr/axi_state_reg[0]_C/CLR
|
| 2092 |
|
|
(removal check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2093 |
|
|
Path Group: **async_default**
|
| 2094 |
|
|
Path Type: Removal (Min at Fast Process Corner)
|
| 2095 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 2096 |
|
|
Data Path Delay: 0.496ns (logic 0.156ns (31.441%) route 0.340ns (68.559%))
|
| 2097 |
|
|
Logic Levels: 2 (LUT3=1 LUT6=1)
|
| 2098 |
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
| 2099 |
|
|
Destination Clock Delay (DCD): -0.691ns
|
| 2100 |
|
|
Source Clock Delay (SCD): -0.642ns
|
| 2101 |
|
|
Clock Pessimism Removal (CPR): -0.063ns
|
| 2102 |
|
|
|
| 2103 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 2104 |
|
|
------------------------------------------------------------------- -------------------
|
| 2105 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2106 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2107 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2108 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 2109 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 2110 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2111 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2112 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 2113 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 2114 |
|
|
net (fo=982, routed) 0.562 -0.642 sys_mngr/clk_out1
|
| 2115 |
|
|
SLICE_X24Y228 FDPE r sys_mngr/axi_state_reg[10]_P/C
|
| 2116 |
|
|
------------------------------------------------------------------- -------------------
|
| 2117 |
|
|
SLICE_X24Y228 FDPE (Prop_fdpe_C_Q) 0.100 -0.542 r sys_mngr/axi_state_reg[10]_P/Q
|
| 2118 |
|
|
net (fo=5, routed) 0.133 -0.408 sys_mngr/axi_state_reg[10]_P_n_0
|
| 2119 |
|
|
SLICE_X25Y229 LUT6 (Prop_lut6_I2_O) 0.028 -0.380 r sys_mngr/axi_state[0]_P_i_2/O
|
| 2120 |
|
|
net (fo=4, routed) 0.099 -0.281 sys_mngr/axi_state[0]_P_i_2_n_0
|
| 2121 |
|
|
SLICE_X27Y229 LUT3 (Prop_lut3_I2_O) 0.028 -0.253 f sys_mngr/axi_state_reg[0]_LDC_i_1/O
|
| 2122 |
|
|
net (fo=2, routed) 0.107 -0.145 sys_mngr/axi_state_reg[0]_LDC_i_1_n_0
|
| 2123 |
|
|
SLICE_X27Y229 FDCE f sys_mngr/axi_state_reg[0]_C/CLR
|
| 2124 |
|
|
------------------------------------------------------------------- -------------------
|
| 2125 |
|
|
|
| 2126 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2127 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2128 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2129 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 2130 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 2131 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2132 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2133 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 2134 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 2135 |
|
|
net (fo=982, routed) 0.766 -0.691 sys_mngr/clk_out1
|
| 2136 |
|
|
SLICE_X27Y229 FDCE r sys_mngr/axi_state_reg[0]_C/C
|
| 2137 |
|
|
clock pessimism 0.063 -0.629
|
| 2138 |
|
|
SLICE_X27Y229 FDCE (Remov_fdce_C_CLR) -0.069 -0.698 sys_mngr/axi_state_reg[0]_C
|
| 2139 |
|
|
-------------------------------------------------------------------
|
| 2140 |
|
|
required time 0.698
|
| 2141 |
|
|
arrival time -0.145
|
| 2142 |
|
|
-------------------------------------------------------------------
|
| 2143 |
|
|
slack 0.552
|
| 2144 |
|
|
|
| 2145 |
|
|
Slack (MET) : 0.595ns (arrival time - required time)
|
| 2146 |
|
|
Source: sys_mngr/axi_state_reg[10]_C/C
|
| 2147 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2148 |
|
|
Destination: sys_mngr/axi_state_reg[2]_C/CLR
|
| 2149 |
|
|
(removal check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2150 |
|
|
Path Group: **async_default**
|
| 2151 |
|
|
Path Type: Removal (Min at Fast Process Corner)
|
| 2152 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 2153 |
|
|
Data Path Delay: 0.537ns (logic 0.156ns (29.071%) route 0.381ns (70.929%))
|
| 2154 |
|
|
Logic Levels: 2 (LUT6=2)
|
| 2155 |
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
| 2156 |
|
|
Destination Clock Delay (DCD): -0.691ns
|
| 2157 |
|
|
Source Clock Delay (SCD): -0.640ns
|
| 2158 |
|
|
Clock Pessimism Removal (CPR): -0.063ns
|
| 2159 |
|
|
|
| 2160 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 2161 |
|
|
------------------------------------------------------------------- -------------------
|
| 2162 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2163 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2164 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2165 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 2166 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 2167 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2168 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2169 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 2170 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 2171 |
|
|
net (fo=982, routed) 0.564 -0.640 sys_mngr/clk_out1
|
| 2172 |
|
|
SLICE_X24Y230 FDCE r sys_mngr/axi_state_reg[10]_C/C
|
| 2173 |
|
|
------------------------------------------------------------------- -------------------
|
| 2174 |
|
|
SLICE_X24Y230 FDCE (Prop_fdce_C_Q) 0.100 -0.540 r sys_mngr/axi_state_reg[10]_C/Q
|
| 2175 |
|
|
net (fo=6, routed) 0.107 -0.433 sys_mngr/axi_state_reg[10]_C_n_0
|
| 2176 |
|
|
SLICE_X25Y230 LUT6 (Prop_lut6_I3_O) 0.028 -0.405 r sys_mngr/axi_state[10]_P_i_1/O
|
| 2177 |
|
|
net (fo=9, routed) 0.130 -0.275 sys_mngr/axi_state[10]_P_i_1_n_0
|
| 2178 |
|
|
SLICE_X24Y228 LUT6 (Prop_lut6_I4_O) 0.028 -0.247 f sys_mngr/axi_state_reg[2]_LDC_i_1/O
|
| 2179 |
|
|
net (fo=2, routed) 0.144 -0.103 sys_mngr/axi_state_reg[2]_LDC_i_1_n_0
|
| 2180 |
|
|
SLICE_X25Y229 FDCE f sys_mngr/axi_state_reg[2]_C/CLR
|
| 2181 |
|
|
------------------------------------------------------------------- -------------------
|
| 2182 |
|
|
|
| 2183 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2184 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2185 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2186 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 2187 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 2188 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2189 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2190 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 2191 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 2192 |
|
|
net (fo=982, routed) 0.766 -0.691 sys_mngr/clk_out1
|
| 2193 |
|
|
SLICE_X25Y229 FDCE r sys_mngr/axi_state_reg[2]_C/C
|
| 2194 |
|
|
clock pessimism 0.063 -0.629
|
| 2195 |
|
|
SLICE_X25Y229 FDCE (Remov_fdce_C_CLR) -0.069 -0.698 sys_mngr/axi_state_reg[2]_C
|
| 2196 |
|
|
-------------------------------------------------------------------
|
| 2197 |
|
|
required time 0.698
|
| 2198 |
|
|
arrival time -0.103
|
| 2199 |
|
|
-------------------------------------------------------------------
|
| 2200 |
|
|
slack 0.595
|
| 2201 |
|
|
|
| 2202 |
|
|
Slack (MET) : 0.602ns (arrival time - required time)
|
| 2203 |
|
|
Source: sys_mngr/axi_state_reg[10]_P/C
|
| 2204 |
|
|
(rising edge-triggered cell FDPE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2205 |
|
|
Destination: sys_mngr/axi_state_reg[0]_P/PRE
|
| 2206 |
|
|
(removal check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2207 |
|
|
Path Group: **async_default**
|
| 2208 |
|
|
Path Type: Removal (Min at Fast Process Corner)
|
| 2209 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 2210 |
|
|
Data Path Delay: 0.542ns (logic 0.156ns (28.766%) route 0.386ns (71.234%))
|
| 2211 |
|
|
Logic Levels: 2 (LUT3=1 LUT6=1)
|
| 2212 |
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
| 2213 |
|
|
Destination Clock Delay (DCD): -0.692ns
|
| 2214 |
|
|
Source Clock Delay (SCD): -0.642ns
|
| 2215 |
|
|
Clock Pessimism Removal (CPR): -0.063ns
|
| 2216 |
|
|
|
| 2217 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 2218 |
|
|
------------------------------------------------------------------- -------------------
|
| 2219 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2220 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2221 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2222 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 2223 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 2224 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2225 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2226 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 2227 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 2228 |
|
|
net (fo=982, routed) 0.562 -0.642 sys_mngr/clk_out1
|
| 2229 |
|
|
SLICE_X24Y228 FDPE r sys_mngr/axi_state_reg[10]_P/C
|
| 2230 |
|
|
------------------------------------------------------------------- -------------------
|
| 2231 |
|
|
SLICE_X24Y228 FDPE (Prop_fdpe_C_Q) 0.100 -0.542 f sys_mngr/axi_state_reg[10]_P/Q
|
| 2232 |
|
|
net (fo=5, routed) 0.133 -0.408 sys_mngr/axi_state_reg[10]_P_n_0
|
| 2233 |
|
|
SLICE_X25Y229 LUT6 (Prop_lut6_I2_O) 0.028 -0.380 f sys_mngr/axi_state[0]_P_i_2/O
|
| 2234 |
|
|
net (fo=4, routed) 0.146 -0.235 sys_mngr/axi_state[0]_P_i_2_n_0
|
| 2235 |
|
|
SLICE_X27Y228 LUT3 (Prop_lut3_I0_O) 0.028 -0.207 f sys_mngr/axi_state[0]_P_i_3/O
|
| 2236 |
|
|
net (fo=2, routed) 0.107 -0.099 sys_mngr/axi_state[0]_P_i_3_n_0
|
| 2237 |
|
|
SLICE_X27Y228 FDPE f sys_mngr/axi_state_reg[0]_P/PRE
|
| 2238 |
|
|
------------------------------------------------------------------- -------------------
|
| 2239 |
|
|
|
| 2240 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2241 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2242 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2243 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 2244 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 2245 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2246 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2247 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 2248 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 2249 |
|
|
net (fo=982, routed) 0.765 -0.692 sys_mngr/clk_out1
|
| 2250 |
|
|
SLICE_X27Y228 FDPE r sys_mngr/axi_state_reg[0]_P/C
|
| 2251 |
|
|
clock pessimism 0.063 -0.630
|
| 2252 |
|
|
SLICE_X27Y228 FDPE (Remov_fdpe_C_PRE) -0.072 -0.702 sys_mngr/axi_state_reg[0]_P
|
| 2253 |
|
|
-------------------------------------------------------------------
|
| 2254 |
|
|
required time 0.702
|
| 2255 |
|
|
arrival time -0.099
|
| 2256 |
|
|
-------------------------------------------------------------------
|
| 2257 |
|
|
slack 0.602
|
| 2258 |
|
|
|
| 2259 |
|
|
Slack (MET) : 0.724ns (arrival time - required time)
|
| 2260 |
|
|
Source: sys_mngr/axi_state_reg[10]_C/C
|
| 2261 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2262 |
|
|
Destination: sys_mngr/axi_state_reg[10]_C/CLR
|
| 2263 |
|
|
(removal check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2264 |
|
|
Path Group: **async_default**
|
| 2265 |
|
|
Path Type: Removal (Min at Fast Process Corner)
|
| 2266 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 2267 |
|
|
Data Path Delay: 0.655ns (logic 0.156ns (23.819%) route 0.499ns (76.181%))
|
| 2268 |
|
|
Logic Levels: 2 (LUT3=1 LUT6=1)
|
| 2269 |
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
| 2270 |
|
|
Destination Clock Delay (DCD): -0.690ns
|
| 2271 |
|
|
Source Clock Delay (SCD): -0.640ns
|
| 2272 |
|
|
Clock Pessimism Removal (CPR): -0.051ns
|
| 2273 |
|
|
|
| 2274 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 2275 |
|
|
------------------------------------------------------------------- -------------------
|
| 2276 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2277 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2278 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2279 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 2280 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 2281 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2282 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2283 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 2284 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 2285 |
|
|
net (fo=982, routed) 0.564 -0.640 sys_mngr/clk_out1
|
| 2286 |
|
|
SLICE_X24Y230 FDCE r sys_mngr/axi_state_reg[10]_C/C
|
| 2287 |
|
|
------------------------------------------------------------------- -------------------
|
| 2288 |
|
|
SLICE_X24Y230 FDCE (Prop_fdce_C_Q) 0.100 -0.540 r sys_mngr/axi_state_reg[10]_C/Q
|
| 2289 |
|
|
net (fo=6, routed) 0.107 -0.433 sys_mngr/axi_state_reg[10]_C_n_0
|
| 2290 |
|
|
SLICE_X25Y230 LUT6 (Prop_lut6_I3_O) 0.028 -0.405 r sys_mngr/axi_state[10]_P_i_1/O
|
| 2291 |
|
|
net (fo=9, routed) 0.246 -0.159 sys_mngr/axi_state[10]_P_i_1_n_0
|
| 2292 |
|
|
SLICE_X24Y229 LUT3 (Prop_lut3_I0_O) 0.028 -0.131 f sys_mngr/axi_state_reg[10]_LDC_i_1/O
|
| 2293 |
|
|
net (fo=2, routed) 0.146 0.015 sys_mngr/axi_state_reg[10]_LDC_i_1_n_0
|
| 2294 |
|
|
SLICE_X24Y230 FDCE f sys_mngr/axi_state_reg[10]_C/CLR
|
| 2295 |
|
|
------------------------------------------------------------------- -------------------
|
| 2296 |
|
|
|
| 2297 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2298 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2299 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2300 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 2301 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 2302 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2303 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2304 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 2305 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 2306 |
|
|
net (fo=982, routed) 0.767 -0.690 sys_mngr/clk_out1
|
| 2307 |
|
|
SLICE_X24Y230 FDCE r sys_mngr/axi_state_reg[10]_C/C
|
| 2308 |
|
|
clock pessimism 0.051 -0.640
|
| 2309 |
|
|
SLICE_X24Y230 FDCE (Remov_fdce_C_CLR) -0.069 -0.709 sys_mngr/axi_state_reg[10]_C
|
| 2310 |
|
|
-------------------------------------------------------------------
|
| 2311 |
|
|
required time 0.709
|
| 2312 |
|
|
arrival time 0.015
|
| 2313 |
|
|
-------------------------------------------------------------------
|
| 2314 |
|
|
slack 0.724
|
| 2315 |
|
|
|
| 2316 |
|
|
Slack (MET) : 0.785ns (arrival time - required time)
|
| 2317 |
|
|
Source: sys_mngr/axi_state_reg[10]_C/C
|
| 2318 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2319 |
|
|
Destination: sys_mngr/axi_state_reg[10]_P/PRE
|
| 2320 |
|
|
(removal check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2321 |
|
|
Path Group: **async_default**
|
| 2322 |
|
|
Path Type: Removal (Min at Fast Process Corner)
|
| 2323 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 2324 |
|
|
Data Path Delay: 0.723ns (logic 0.156ns (21.570%) route 0.567ns (78.430%))
|
| 2325 |
|
|
Logic Levels: 2 (LUT3=1 LUT6=1)
|
| 2326 |
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
| 2327 |
|
|
Destination Clock Delay (DCD): -0.692ns
|
| 2328 |
|
|
Source Clock Delay (SCD): -0.640ns
|
| 2329 |
|
|
Clock Pessimism Removal (CPR): -0.063ns
|
| 2330 |
|
|
|
| 2331 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 2332 |
|
|
------------------------------------------------------------------- -------------------
|
| 2333 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2334 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2335 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2336 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 2337 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 2338 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2339 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2340 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 2341 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 2342 |
|
|
net (fo=982, routed) 0.564 -0.640 sys_mngr/clk_out1
|
| 2343 |
|
|
SLICE_X24Y230 FDCE r sys_mngr/axi_state_reg[10]_C/C
|
| 2344 |
|
|
------------------------------------------------------------------- -------------------
|
| 2345 |
|
|
SLICE_X24Y230 FDCE (Prop_fdce_C_Q) 0.100 -0.540 f sys_mngr/axi_state_reg[10]_C/Q
|
| 2346 |
|
|
net (fo=6, routed) 0.107 -0.433 sys_mngr/axi_state_reg[10]_C_n_0
|
| 2347 |
|
|
SLICE_X25Y230 LUT6 (Prop_lut6_I3_O) 0.028 -0.405 f sys_mngr/axi_state[10]_P_i_1/O
|
| 2348 |
|
|
net (fo=9, routed) 0.130 -0.275 sys_mngr/axi_state[10]_P_i_1_n_0
|
| 2349 |
|
|
SLICE_X24Y228 LUT3 (Prop_lut3_I0_O) 0.028 -0.247 f sys_mngr/axi_state[10]_P_i_2/O
|
| 2350 |
|
|
net (fo=2, routed) 0.330 0.084 sys_mngr/axi_state[10]_P_i_2_n_0
|
| 2351 |
|
|
SLICE_X24Y228 FDPE f sys_mngr/axi_state_reg[10]_P/PRE
|
| 2352 |
|
|
------------------------------------------------------------------- -------------------
|
| 2353 |
|
|
|
| 2354 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2355 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2356 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2357 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 2358 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 2359 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2360 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2361 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 2362 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 2363 |
|
|
net (fo=982, routed) 0.765 -0.692 sys_mngr/clk_out1
|
| 2364 |
|
|
SLICE_X24Y228 FDPE r sys_mngr/axi_state_reg[10]_P/C
|
| 2365 |
|
|
clock pessimism 0.063 -0.630
|
| 2366 |
|
|
SLICE_X24Y228 FDPE (Remov_fdpe_C_PRE) -0.072 -0.702 sys_mngr/axi_state_reg[10]_P
|
| 2367 |
|
|
-------------------------------------------------------------------
|
| 2368 |
|
|
required time 0.702
|
| 2369 |
|
|
arrival time 0.084
|
| 2370 |
|
|
-------------------------------------------------------------------
|
| 2371 |
|
|
slack 0.785
|
| 2372 |
|
|
|
| 2373 |
|
|
Slack (MET) : 0.877ns (arrival time - required time)
|
| 2374 |
|
|
Source: sys_mngr/axi_state_reg[1]_C/C
|
| 2375 |
|
|
(rising edge-triggered cell FDCE clocked by clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2376 |
|
|
Destination: sys_mngr/axi_state_reg[2]_P/PRE
|
| 2377 |
|
|
(removal check against rising-edge clock clk_gen {rise@0.000ns fall@5.000ns period=10.000ns})
|
| 2378 |
|
|
Path Group: **async_default**
|
| 2379 |
|
|
Path Type: Removal (Min at Fast Process Corner)
|
| 2380 |
|
|
Requirement: 0.000ns (clk_gen rise@0.000ns - clk_gen rise@0.000ns)
|
| 2381 |
|
|
Data Path Delay: 0.833ns (logic 0.174ns (20.895%) route 0.659ns (79.105%))
|
| 2382 |
|
|
Logic Levels: 2 (LUT3=1 LUT6=1)
|
| 2383 |
|
|
Clock Path Skew: 0.028ns (DCD - SCD - CPR)
|
| 2384 |
|
|
Destination Clock Delay (DCD): -0.690ns
|
| 2385 |
|
|
Source Clock Delay (SCD): -0.638ns
|
| 2386 |
|
|
Clock Pessimism Removal (CPR): -0.081ns
|
| 2387 |
|
|
|
| 2388 |
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
| 2389 |
|
|
------------------------------------------------------------------- -------------------
|
| 2390 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2391 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2392 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2393 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.367 0.367 r clkgen/inst/clkin1_ibufgds/O
|
| 2394 |
|
|
net (fo=1, routed) 0.503 0.870 clkgen/inst/clk_in1_clk_gen
|
| 2395 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2396 |
|
|
-3.040 -2.170 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2397 |
|
|
net (fo=1, routed) 0.940 -1.230 clkgen/inst/clk_out1_clk_gen
|
| 2398 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.204 r clkgen/inst/clkout1_buf/O
|
| 2399 |
|
|
net (fo=982, routed) 0.566 -0.638 sys_mngr/clk_out1
|
| 2400 |
|
|
SLICE_X22Y229 FDCE r sys_mngr/axi_state_reg[1]_C/C
|
| 2401 |
|
|
------------------------------------------------------------------- -------------------
|
| 2402 |
|
|
SLICE_X22Y229 FDCE (Prop_fdce_C_Q) 0.118 -0.520 f sys_mngr/axi_state_reg[1]_C/Q
|
| 2403 |
|
|
net (fo=7, routed) 0.241 -0.278 sys_mngr/axi_state_reg[1]_C_n_0
|
| 2404 |
|
|
SLICE_X24Y229 LUT6 (Prop_lut6_I3_O) 0.028 -0.250 f sys_mngr/axi_state[2]_P_i_1/O
|
| 2405 |
|
|
net (fo=3, routed) 0.133 -0.118 sys_mngr/axi_state[2]_P_i_1_n_0
|
| 2406 |
|
|
SLICE_X24Y230 LUT3 (Prop_lut3_I0_O) 0.028 -0.090 f sys_mngr/axi_state[2]_P_i_2/O
|
| 2407 |
|
|
net (fo=2, routed) 0.285 0.195 sys_mngr/axi_state[2]_P_i_2_n_0
|
| 2408 |
|
|
SLICE_X25Y230 FDPE f sys_mngr/axi_state_reg[2]_P/PRE
|
| 2409 |
|
|
------------------------------------------------------------------- -------------------
|
| 2410 |
|
|
|
| 2411 |
|
|
(clock clk_gen rise edge) 0.000 0.000 r
|
| 2412 |
|
|
AD12 0.000 0.000 r CLK_IN_P (IN)
|
| 2413 |
|
|
net (fo=0) 0.000 0.000 clkgen/inst/clk_in1_p
|
| 2414 |
|
|
AD12 IBUFDS (Prop_ibufds_I_O) 0.446 0.446 r clkgen/inst/clkin1_ibufgds/O
|
| 2415 |
|
|
net (fo=1, routed) 0.553 0.999 clkgen/inst/clk_in1_clk_gen
|
| 2416 |
|
|
MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
|
| 2417 |
|
|
-3.493 -2.494 r clkgen/inst/mmcm_adv_inst/CLKOUT0
|
| 2418 |
|
|
net (fo=1, routed) 1.007 -1.487 clkgen/inst/clk_out1_clk_gen
|
| 2419 |
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -1.457 r clkgen/inst/clkout1_buf/O
|
| 2420 |
|
|
net (fo=982, routed) 0.767 -0.690 sys_mngr/clk_out1
|
| 2421 |
|
|
SLICE_X25Y230 FDPE r sys_mngr/axi_state_reg[2]_P/C
|
| 2422 |
|
|
clock pessimism 0.081 -0.610
|
| 2423 |
|
|
SLICE_X25Y230 FDPE (Remov_fdpe_C_PRE) -0.072 -0.682 sys_mngr/axi_state_reg[2]_P
|
| 2424 |
|
|
-------------------------------------------------------------------
|
| 2425 |
|
|
required time 0.682
|
| 2426 |
|
|
arrival time 0.195
|
| 2427 |
|
|
-------------------------------------------------------------------
|
| 2428 |
|
|
slack 0.877
|
| 2429 |
|
|
|
| 2430 |
|
|
|
| 2431 |
|
|
|
| 2432 |
|
|
|
| 2433 |
|
|
|
