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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [impl_1/] [aes128_ecb_fpga_wrap_utilization_placed.rpt] - Blame information for rev 2

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1 2 vv_gulyaev 
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
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| Date         : Thu Jul 30 13:55:42 2020
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| Host         : orme22 running 64-bit Ubuntu 18.04.4 LTS
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| Command      : report_utilization -file aes128_ecb_fpga_wrap_utilization_placed.rpt -pb aes128_ecb_fpga_wrap_utilization_placed.pb
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| Design       : aes128_ecb_fpga_wrap
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| Device       : 7k325tffg900-2
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| Design State : Fully Placed
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-------------------------------------------------------------------------------------------------------------------------------------
11 
 
12 
Utilization Design Information
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14 
Table of Contents
15 
-----------------
16 
1. Slice Logic
17 
1.1 Summary of Registers by Type
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2. Slice Logic Distribution
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3. Memory
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4. DSP
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5. IO and GT Specific
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6. Clocking
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7. Specific Feature
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8. Primitives
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9. Black Boxes
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10. Instantiated Netlists
27 
 
28 
1. Slice Logic
29 
--------------
30 
 
31 
+----------------------------+------+-------+-----------+-------+
32 
|          Site Type         | Used | Fixed | Available | Util% |
33 
+----------------------------+------+-------+-----------+-------+
34 
| Slice LUTs                 | 2830 |     0 |    203800 |  1.39 |
35 
|   LUT as Logic             | 2820 |     0 |    203800 |  1.38 |
36 
|   LUT as Memory            |   10 |     0 |     64000 |  0.02 |
37 
|     LUT as Distributed RAM |    0 |     0 |           |       |
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|     LUT as Shift Register  |   10 |     0 |           |       |
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| Slice Registers            |  968 |     0 |    407600 |  0.24 |
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|   Register as Flip Flop    |  964 |     0 |    407600 |  0.24 |
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|   Register as Latch        |    4 |     0 |    407600 | <0.01 |
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| F7 Muxes                   |  637 |     0 |    101900 |  0.63 |
43 
| F8 Muxes                   |  270 |     0 |     50950 |  0.53 |
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+----------------------------+------+-------+-----------+-------+
45 
 
46 
 
47 
1.1 Summary of Registers by Type
48 
--------------------------------
49 
 
50 
+-------+--------------+-------------+--------------+
51 
| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0     |            _ |           - |            - |
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| 0     |            _ |           - |          Set |
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| 0     |            _ |           - |        Reset |
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| 0     |            _ |         Set |            - |
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| 0     |            _ |       Reset |            - |
58 
| 0     |          Yes |           - |            - |
59 
| 4     |          Yes |           - |          Set |
60 
| 872   |          Yes |           - |        Reset |
61 
| 16    |          Yes |         Set |            - |
62 
| 76    |          Yes |       Reset |            - |
63 
+-------+--------------+-------------+--------------+
64 
 
65 
 
66 
2. Slice Logic Distribution
67 
---------------------------
68 
 
69 
+-------------------------------------------+------+-------+-----------+-------+
70 
|                 Site Type                 | Used | Fixed | Available | Util% |
71 
+-------------------------------------------+------+-------+-----------+-------+
72 
| Slice                                     |  813 |     0 |     50950 |  1.60 |
73 
|   SLICEL                                  |  692 |     0 |           |       |
74 
|   SLICEM                                  |  121 |     0 |           |       |
75 
| LUT as Logic                              | 2820 |     0 |    203800 |  1.38 |
76 
|   using O5 output only                    |    0 |       |           |       |
77 
|   using O6 output only                    | 2482 |       |           |       |
78 
|   using O5 and O6                         |  338 |       |           |       |
79 
| LUT as Memory                             |   10 |     0 |     64000 |  0.02 |
80 
|   LUT as Distributed RAM                  |    0 |     0 |           |       |
81 
|   LUT as Shift Register                   |   10 |     0 |           |       |
82 
|     using O5 output only                  |    2 |       |           |       |
83 
|     using O6 output only                  |    0 |       |           |       |
84 
|     using O5 and O6                       |    8 |       |           |       |
85 
| LUT Flip Flop Pairs                       |  755 |     0 |    203800 |  0.37 |
86 
|   fully used LUT-FF pairs                 |  141 |       |           |       |
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|   LUT-FF pairs with one unused LUT output |  599 |       |           |       |
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|   LUT-FF pairs with one unused Flip Flop  |  608 |       |           |       |
89 
| Unique Control Sets                       |   45 |       |           |       |
90 
+-------------------------------------------+------+-------+-----------+-------+
91 
* Note: Review the Control Sets Report for more information regarding control sets.
92 
 
93 
 
94 
3. Memory
95 
---------
96 
 
97 
+----------------+------+-------+-----------+-------+
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|    Site Type   | Used | Fixed | Available | Util% |
99 
+----------------+------+-------+-----------+-------+
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| Block RAM Tile |    0 |     0 |       445 |  0.00 |
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|   RAMB36/FIFO* |    0 |     0 |       445 |  0.00 |
102 
|   RAMB18       |    0 |     0 |       890 |  0.00 |
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+----------------+------+-------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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106 
 
107 
4. DSP
108 
------
109 
 
110 
+-----------+------+-------+-----------+-------+
111 
| Site Type | Used | Fixed | Available | Util% |
112 
+-----------+------+-------+-----------+-------+
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| DSPs      |    0 |     0 |       840 |  0.00 |
114 
+-----------+------+-------+-----------+-------+
115 
 
116 
 
117 
5. IO and GT Specific
118 
---------------------
119 
 
120 
+-----------------------------+------+-------+-----------+-------+
121 
|          Site Type          | Used | Fixed | Available | Util% |
122 
+-----------------------------+------+-------+-----------+-------+
123 
| Bonded IOB                  |    9 |     9 |       500 |  1.80 |
124 
|   IOB Master Pads           |    2 |       |           |       |
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|   IOB Slave Pads            |    4 |       |           |       |
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| Bonded IPADs                |    0 |     0 |        50 |  0.00 |
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| Bonded OPADs                |    0 |     0 |        32 |  0.00 |
128 
| PHY_CONTROL                 |    0 |     0 |        10 |  0.00 |
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| PHASER_REF                  |    0 |     0 |        10 |  0.00 |
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| OUT_FIFO                    |    0 |     0 |        40 |  0.00 |
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| IN_FIFO                     |    0 |     0 |        40 |  0.00 |
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| IDELAYCTRL                  |    0 |     0 |        10 |  0.00 |
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| IBUFDS                      |    1 |     1 |       480 |  0.21 |
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| GTXE2_COMMON                |    0 |     0 |         4 |  0.00 |
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| GTXE2_CHANNEL               |    0 |     0 |        16 |  0.00 |
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| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        40 |  0.00 |
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| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        40 |  0.00 |
138 
| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       500 |  0.00 |
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| ODELAYE2/ODELAYE2_FINEDELAY |    0 |     0 |       150 |  0.00 |
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| IBUFDS_GTE2                 |    0 |     0 |         8 |  0.00 |
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| ILOGIC                      |    0 |     0 |       500 |  0.00 |
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| OLOGIC                      |    0 |     0 |       500 |  0.00 |
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+-----------------------------+------+-------+-----------+-------+
144 
 
145 
 
146 
6. Clocking
147 
-----------
148 
 
149 
+------------+------+-------+-----------+-------+
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|  Site Type | Used | Fixed | Available | Util% |
151 
+------------+------+-------+-----------+-------+
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| BUFGCTRL   |    2 |     0 |        32 |  6.25 |
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| BUFIO      |    0 |     0 |        40 |  0.00 |
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| MMCME2_ADV |    1 |     0 |        10 | 10.00 |
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| PLLE2_ADV  |    0 |     0 |        10 |  0.00 |
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| BUFMRCE    |    0 |     0 |        20 |  0.00 |
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| BUFHCE     |    0 |     0 |       168 |  0.00 |
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| BUFR       |    0 |     0 |        40 |  0.00 |
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+------------+------+-------+-----------+-------+
160 
 
161 
 
162 
7. Specific Feature
163 
-------------------
164 
 
165 
+-------------+------+-------+-----------+-------+
166 
|  Site Type  | Used | Fixed | Available | Util% |
167 
+-------------+------+-------+-----------+-------+
168 
| BSCANE2     |    0 |     0 |         4 |  0.00 |
169 
| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
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| DNA_PORT    |    0 |     0 |         1 |  0.00 |
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| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
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| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
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| ICAPE2      |    0 |     0 |         2 |  0.00 |
174 
| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
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| STARTUPE2   |    0 |     0 |         1 |  0.00 |
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| XADC        |    0 |     0 |         1 |  0.00 |
177 
+-------------+------+-------+-----------+-------+
178 
 
179 
 
180 
8. Primitives
181 
-------------
182 
 
183 
+------------+------+---------------------+
184 
|  Ref Name  | Used | Functional Category |
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+------------+------+---------------------+
186 
| LUT6       | 1941 |                 LUT |
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| FDCE       |  868 |        Flop & Latch |
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| MUXF7      |  637 |               MuxFx |
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| LUT2       |  450 |                 LUT |
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| LUT3       |  323 |                 LUT |
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| MUXF8      |  270 |               MuxFx |
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| LUT5       |  268 |                 LUT |
193 
| LUT4       |  173 |                 LUT |
194 
| FDRE       |   76 |        Flop & Latch |
195 
| SRL16E     |   18 |  Distributed Memory |
196 
| FDSE       |   16 |        Flop & Latch |
197 
| CARRY4     |    8 |          CarryLogic |
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| OBUF       |    5 |                  IO |
199 
| LDCE       |    4 |        Flop & Latch |
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| FDPE       |    4 |        Flop & Latch |
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| LUT1       |    3 |                 LUT |
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| IBUF       |    2 |                  IO |
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| BUFG       |    2 |               Clock |
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| MMCME2_ADV |    1 |               Clock |
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| IBUFDS     |    1 |                  IO |
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+------------+------+---------------------+
207 
 
208 
 
209 
9. Black Boxes
210 
--------------
211 
 
212 
+----------+------+
213 
| Ref Name | Used |
214 
+----------+------+
215 
 
216 
 
217 
10. Instantiated Netlists
218 
-------------------------
219 
 
220 
+---------------------+------+
221 
|       Ref Name      | Used |
222 
+---------------------+------+
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| clk_gen             |    1 |
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| axi_uartlite_module |    1 |
225 
+---------------------+------+
226 
 
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