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vv_gulyaev |
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*** Running vivado
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with args -log aes128_ecb_fpga_wrap.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source aes128_ecb_fpga_wrap.tcl -notrace
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****** Vivado v2017.4 (64-bit)
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**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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source aes128_ecb_fpga_wrap.tcl -notrace
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Command: link_design -top aes128_ecb_fpga_wrap -part xc7k325tffg900-2
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Project 1-454] Reading design checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen'
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INFO: [Project 1-454] Reading design checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite'
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INFO: [Netlist 29-17] Analyzing 919 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2017.4
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INFO: [Device 21-403] Loading part xc7k325tffg900-2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst'
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst'
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
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INFO: [Timing 38-2] Deriving generated clocks [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
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get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2076.297 ; gain = 549.656 ; free physical = 2287 ; free virtual = 5864
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'uartlite/U0'
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'uartlite/U0'
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'uartlite/U0'
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'uartlite/U0'
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
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Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc]
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Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc]
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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11 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:39 . Memory (MB): peak = 2076.297 ; gain = 911.250 ; free physical = 2295 ; free virtual = 5867
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 4 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2116.316 ; gain = 32.016 ; free physical = 2287 ; free virtual = 5859
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: 18bd964f5
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Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2288 ; free virtual = 5860
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INFO: [Opt 31-389] Phase Retarget created 10 cells and removed 12 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: 18bd964f5
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Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2288 ; free virtual = 5860
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: 18872f0f7
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Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2288 ; free virtual = 5860
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: 18872f0f7
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Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2288 ; free virtual = 5860
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INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 18872f0f7
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Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2288 ; free virtual = 5860
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2288 ; free virtual = 5860
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Ending Logic Optimization Task | Checksum: 18872f0f7
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Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2288 ; free virtual = 5860
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 169758e13
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Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2288 ; free virtual = 5860
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INFO: [Common 17-83] Releasing license: Implementation
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26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2132.316 ; gain = 0.000 ; free physical = 2287 ; free virtual = 5860
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INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file aes128_ecb_fpga_wrap_drc_opted.rpt -pb aes128_ecb_fpga_wrap_drc_opted.pb -rpx aes128_ecb_fpga_wrap_drc_opted.rpx
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Command: report_drc -file aes128_ecb_fpga_wrap_drc_opted.rpt -pb aes128_ecb_fpga_wrap_drc_opted.pb -rpx aes128_ecb_fpga_wrap_drc_opted.rpx
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 4 threads
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INFO: [Coretcl 2-168] The results of DRC are in file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap_drc_opted.rpt.
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report_drc completed successfully
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INFO: [Chipscope 16-241] No debug cores found in the current design.
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Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
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or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
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INFO: [DRC 23-27] Running DRC with 4 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 4 threads
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WARNING: [DRC PORTPROP-2] selectio_diff_term: The port CLK_IN_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
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WARNING: [DRC PORTPROP-2] selectio_diff_term: The port CLK_IN_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2132.320 ; gain = 0.000 ; free physical = 2276 ; free virtual = 5849
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7ac379e0
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Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2132.320 ; gain = 0.000 ; free physical = 2276 ; free virtual = 5849
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2132.320 ; gain = 0.000 ; free physical = 2277 ; free virtual = 5850
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bb646e39
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Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2132.320 ; gain = 0.000 ; free physical = 2263 ; free virtual = 5840
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 19410c43e
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2135.328 ; gain = 3.008 ; free physical = 2251 ; free virtual = 5829
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 19410c43e
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2135.328 ; gain = 3.008 ; free physical = 2251 ; free virtual = 5829
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Phase 1 Placer Initialization | Checksum: 19410c43e
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Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2135.328 ; gain = 3.008 ; free physical = 2251 ; free virtual = 5829
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Phase 2 Global Placement
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Phase 2 Global Placement | Checksum: 11f809644
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Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2220 ; free virtual = 5798
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Phase 3 Detail Placement
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Phase 3.1 Commit Multi Column Macros
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Phase 3.1 Commit Multi Column Macros | Checksum: 11f809644
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2220 ; free virtual = 5798
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Phase 3.2 Commit Most Macros & LUTRAMs
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Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c69181d7
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2218 ; free virtual = 5796
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| 185 |
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Phase 3.3 Area Swap Optimization
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| 186 |
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Phase 3.3 Area Swap Optimization | Checksum: 1fabbf6a3
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| 187 |
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2217 ; free virtual = 5795
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| 190 |
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Phase 3.4 Pipeline Register Optimization
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| 191 |
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Phase 3.4 Pipeline Register Optimization | Checksum: 1fabbf6a3
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| 192 |
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| 193 |
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Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2217 ; free virtual = 5795
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Phase 3.5 Small Shape Detail Placement
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Phase 3.5 Small Shape Detail Placement | Checksum: c1d1a0e3
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| 197 |
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2209 ; free virtual = 5788
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| 200 |
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Phase 3.6 Re-assign LUT pins
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Phase 3.6 Re-assign LUT pins | Checksum: ab864e22
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| 203 |
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2209 ; free virtual = 5788
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| 205 |
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Phase 3.7 Pipeline Register Optimization
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| 206 |
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Phase 3.7 Pipeline Register Optimization | Checksum: ab864e22
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2209 ; free virtual = 5788
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Phase 3 Detail Placement | Checksum: ab864e22
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 2159.340 ; gain = 27.020 ; free physical = 2209 ; free virtual = 5788
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Phase 4 Post Placement Optimization and Clean-Up
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Phase 4.1 Post Commit Optimization
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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| 217 |
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| 218 |
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Phase 4.1.1 Post Placement Optimization
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Post Placement Optimization Initialization | Checksum: f3bc30c8
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Phase 4.1.1.1 BUFG Insertion
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INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
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| 223 |
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INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
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Phase 4.1.1.1 BUFG Insertion | Checksum: f3bc30c8
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Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2167.332 ; gain = 35.012 ; free physical = 2209 ; free virtual = 5788
|
| 227 |
|
|
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.507. For the most accurate timing information please run report_timing.
|
| 228 |
|
|
Phase 4.1.1 Post Placement Optimization | Checksum: 16ccbd4e1
|
| 229 |
|
|
|
| 230 |
|
|
Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2167.332 ; gain = 35.012 ; free physical = 2209 ; free virtual = 5788
|
| 231 |
|
|
Phase 4.1 Post Commit Optimization | Checksum: 16ccbd4e1
|
| 232 |
|
|
|
| 233 |
|
|
Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2167.332 ; gain = 35.012 ; free physical = 2209 ; free virtual = 5788
|
| 234 |
|
|
|
| 235 |
|
|
Phase 4.2 Post Placement Cleanup
|
| 236 |
|
|
Phase 4.2 Post Placement Cleanup | Checksum: 16ccbd4e1
|
| 237 |
|
|
|
| 238 |
|
|
Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2168.332 ; gain = 36.012 ; free physical = 2216 ; free virtual = 5795
|
| 239 |
|
|
|
| 240 |
|
|
Phase 4.3 Placer Reporting
|
| 241 |
|
|
Phase 4.3 Placer Reporting | Checksum: 16ccbd4e1
|
| 242 |
|
|
|
| 243 |
|
|
Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2168.332 ; gain = 36.012 ; free physical = 2216 ; free virtual = 5795
|
| 244 |
|
|
|
| 245 |
|
|
Phase 4.4 Final Placement Cleanup
|
| 246 |
|
|
Phase 4.4 Final Placement Cleanup | Checksum: 14ea6a809
|
| 247 |
|
|
|
| 248 |
|
|
Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2168.332 ; gain = 36.012 ; free physical = 2216 ; free virtual = 5795
|
| 249 |
|
|
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14ea6a809
|
| 250 |
|
|
|
| 251 |
|
|
Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 2168.332 ; gain = 36.012 ; free physical = 2216 ; free virtual = 5795
|
| 252 |
|
|
Ending Placer Task | Checksum: 5e2c148b
|
| 253 |
|
|
|
| 254 |
|
|
Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 2168.332 ; gain = 36.012 ; free physical = 2251 ; free virtual = 5830
|
| 255 |
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
| 256 |
|
|
48 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
| 257 |
|
|
place_design completed successfully
|
| 258 |
|
|
place_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 2168.332 ; gain = 36.016 ; free physical = 2251 ; free virtual = 5830
|
| 259 |
|
|
Writing placer database...
|
| 260 |
|
|
Writing XDEF routing.
|
| 261 |
|
|
Writing XDEF routing logical nets.
|
| 262 |
|
|
Writing XDEF routing special nets.
|
| 263 |
|
|
Write XDEF Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2168.332 ; gain = 0.000 ; free physical = 2246 ; free virtual = 5829
|
| 264 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap_placed.dcp' has been generated.
|
| 265 |
|
|
INFO: [runtcl-4] Executing : report_io -file aes128_ecb_fpga_wrap_io_placed.rpt
|
| 266 |
|
|
report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2168.332 ; gain = 0.000 ; free physical = 2227 ; free virtual = 5807
|
| 267 |
|
|
INFO: [runtcl-4] Executing : report_utilization -file aes128_ecb_fpga_wrap_utilization_placed.rpt -pb aes128_ecb_fpga_wrap_utilization_placed.pb
|
| 268 |
|
|
report_utilization: Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2168.332 ; gain = 0.000 ; free physical = 2246 ; free virtual = 5826
|
| 269 |
|
|
INFO: [runtcl-4] Executing : report_control_sets -verbose -file aes128_ecb_fpga_wrap_control_sets_placed.rpt
|
| 270 |
|
|
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2168.332 ; gain = 0.000 ; free physical = 2246 ; free virtual = 5826
|
| 271 |
|
|
Command: route_design
|
| 272 |
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
|
| 273 |
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
|
| 274 |
|
|
Running DRC as a precondition to command route_design
|
| 275 |
|
|
INFO: [DRC 23-27] Running DRC with 4 threads
|
| 276 |
|
|
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port CLK_IN_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
|
| 277 |
|
|
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port CLK_IN_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
|
| 278 |
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 2 Warnings
|
| 279 |
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
| 280 |
|
|
|
| 281 |
|
|
|
| 282 |
|
|
Starting Routing Task
|
| 283 |
|
|
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
|
| 284 |
|
|
Checksum: PlaceDB: 22a049de ConstDB: 0 ShapeSum: 3b8bcaad RouteDB: 0
|
| 285 |
|
|
|
| 286 |
|
|
Phase 1 Build RT Design
|
| 287 |
|
|
Phase 1 Build RT Design | Checksum: 10f93e09a
|
| 288 |
|
|
|
| 289 |
|
|
Time (s): cpu = 00:00:31 ; elapsed = 00:00:21 . Memory (MB): peak = 2441.629 ; gain = 273.293 ; free physical = 1979 ; free virtual = 5560
|
| 290 |
|
|
Post Restoration Checksum: NetGraph: f9819b73 NumContArr: 16124527 Constraints: 0 Timing: 0
|
| 291 |
|
|
|
| 292 |
|
|
Phase 2 Router Initialization
|
| 293 |
|
|
|
| 294 |
|
|
Phase 2.1 Create Timer
|
| 295 |
|
|
Phase 2.1 Create Timer | Checksum: 10f93e09a
|
| 296 |
|
|
|
| 297 |
|
|
Time (s): cpu = 00:00:31 ; elapsed = 00:00:21 . Memory (MB): peak = 2441.629 ; gain = 273.293 ; free physical = 1980 ; free virtual = 5561
|
| 298 |
|
|
|
| 299 |
|
|
Phase 2.2 Fix Topology Constraints
|
| 300 |
|
|
Phase 2.2 Fix Topology Constraints | Checksum: 10f93e09a
|
| 301 |
|
|
|
| 302 |
|
|
Time (s): cpu = 00:00:31 ; elapsed = 00:00:21 . Memory (MB): peak = 2441.629 ; gain = 273.293 ; free physical = 1958 ; free virtual = 5539
|
| 303 |
|
|
|
| 304 |
|
|
Phase 2.3 Pre Route Cleanup
|
| 305 |
|
|
Phase 2.3 Pre Route Cleanup | Checksum: 10f93e09a
|
| 306 |
|
|
|
| 307 |
|
|
Time (s): cpu = 00:00:31 ; elapsed = 00:00:21 . Memory (MB): peak = 2441.629 ; gain = 273.293 ; free physical = 1958 ; free virtual = 5539
|
| 308 |
|
|
Number of Nodes with overlaps = 0
|
| 309 |
|
|
|
| 310 |
|
|
Phase 2.4 Update Timing
|
| 311 |
|
|
Phase 2.4 Update Timing | Checksum: 24702e645
|
| 312 |
|
|
|
| 313 |
|
|
Time (s): cpu = 00:00:33 ; elapsed = 00:00:23 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1952 ; free virtual = 5533
|
| 314 |
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.504 | TNS=0.000 | WHS=-0.153 | THS=-35.083|
|
| 315 |
|
|
|
| 316 |
|
|
Phase 2 Router Initialization | Checksum: 1bcd3ae25
|
| 317 |
|
|
|
| 318 |
|
|
Time (s): cpu = 00:00:34 ; elapsed = 00:00:23 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1949 ; free virtual = 5531
|
| 319 |
|
|
|
| 320 |
|
|
Phase 3 Initial Routing
|
| 321 |
|
|
Phase 3 Initial Routing | Checksum: 27d21dd15
|
| 322 |
|
|
|
| 323 |
|
|
Time (s): cpu = 00:00:35 ; elapsed = 00:00:23 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1947 ; free virtual = 5528
|
| 324 |
|
|
|
| 325 |
|
|
Phase 4 Rip-up And Reroute
|
| 326 |
|
|
|
| 327 |
|
|
Phase 4.1 Global Iteration 0
|
| 328 |
|
|
Number of Nodes with overlaps = 624
|
| 329 |
|
|
Number of Nodes with overlaps = 0
|
| 330 |
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.330 | TNS=0.000 | WHS=N/A | THS=N/A |
|
| 331 |
|
|
|
| 332 |
|
|
Phase 4.1 Global Iteration 0 | Checksum: 10b269bc4
|
| 333 |
|
|
|
| 334 |
|
|
Time (s): cpu = 00:00:37 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1946 ; free virtual = 5528
|
| 335 |
|
|
Phase 4 Rip-up And Reroute | Checksum: 10b269bc4
|
| 336 |
|
|
|
| 337 |
|
|
Time (s): cpu = 00:00:37 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1946 ; free virtual = 5528
|
| 338 |
|
|
|
| 339 |
|
|
Phase 5 Delay and Skew Optimization
|
| 340 |
|
|
|
| 341 |
|
|
Phase 5.1 Delay CleanUp
|
| 342 |
|
|
Phase 5.1 Delay CleanUp | Checksum: 10b269bc4
|
| 343 |
|
|
|
| 344 |
|
|
Time (s): cpu = 00:00:37 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1946 ; free virtual = 5528
|
| 345 |
|
|
|
| 346 |
|
|
Phase 5.2 Clock Skew Optimization
|
| 347 |
|
|
Phase 5.2 Clock Skew Optimization | Checksum: 10b269bc4
|
| 348 |
|
|
|
| 349 |
|
|
Time (s): cpu = 00:00:37 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1946 ; free virtual = 5528
|
| 350 |
|
|
Phase 5 Delay and Skew Optimization | Checksum: 10b269bc4
|
| 351 |
|
|
|
| 352 |
|
|
Time (s): cpu = 00:00:37 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1946 ; free virtual = 5528
|
| 353 |
|
|
|
| 354 |
|
|
Phase 6 Post Hold Fix
|
| 355 |
|
|
|
| 356 |
|
|
Phase 6.1 Hold Fix Iter
|
| 357 |
|
|
|
| 358 |
|
|
Phase 6.1.1 Update Timing
|
| 359 |
|
|
Phase 6.1.1 Update Timing | Checksum: 18b88dfe9
|
| 360 |
|
|
|
| 361 |
|
|
Time (s): cpu = 00:00:37 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1946 ; free virtual = 5528
|
| 362 |
|
|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.330 | TNS=0.000 | WHS=0.105 | THS=0.000 |
|
| 363 |
|
|
|
| 364 |
|
|
Phase 6.1 Hold Fix Iter | Checksum: 18b88dfe9
|
| 365 |
|
|
|
| 366 |
|
|
Time (s): cpu = 00:00:37 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1946 ; free virtual = 5528
|
| 367 |
|
|
Phase 6 Post Hold Fix | Checksum: 18b88dfe9
|
| 368 |
|
|
|
| 369 |
|
|
Time (s): cpu = 00:00:37 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1946 ; free virtual = 5528
|
| 370 |
|
|
|
| 371 |
|
|
Phase 7 Route finalize
|
| 372 |
|
|
|
| 373 |
|
|
Router Utilization Summary
|
| 374 |
|
|
Global Vertical Routing Utilization = 0.193573 %
|
| 375 |
|
|
Global Horizontal Routing Utilization = 0.230848 %
|
| 376 |
|
|
Routable Net Status*
|
| 377 |
|
|
*Does not include unroutable nets such as driverless and loadless.
|
| 378 |
|
|
Run report_route_status for detailed report.
|
| 379 |
|
|
Number of Failed Nets = 0
|
| 380 |
|
|
Number of Unrouted Nets = 0
|
| 381 |
|
|
Number of Partially Routed Nets = 0
|
| 382 |
|
|
Number of Node Overlaps = 0
|
| 383 |
|
|
|
| 384 |
|
|
Phase 7 Route finalize | Checksum: 1b8bd5c0d
|
| 385 |
|
|
|
| 386 |
|
|
Time (s): cpu = 00:00:38 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1945 ; free virtual = 5526
|
| 387 |
|
|
|
| 388 |
|
|
Phase 8 Verifying routed nets
|
| 389 |
|
|
|
| 390 |
|
|
Verification completed successfully
|
| 391 |
|
|
Phase 8 Verifying routed nets | Checksum: 1b8bd5c0d
|
| 392 |
|
|
|
| 393 |
|
|
Time (s): cpu = 00:00:38 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1944 ; free virtual = 5525
|
| 394 |
|
|
|
| 395 |
|
|
Phase 9 Depositing Routes
|
| 396 |
|
|
Phase 9 Depositing Routes | Checksum: 178289230
|
| 397 |
|
|
|
| 398 |
|
|
Time (s): cpu = 00:00:38 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1944 ; free virtual = 5525
|
| 399 |
|
|
|
| 400 |
|
|
Phase 10 Post Router Timing
|
| 401 |
|
|
INFO: [Route 35-57] Estimated Timing Summary | WNS=2.330 | TNS=0.000 | WHS=0.105 | THS=0.000 |
|
| 402 |
|
|
|
| 403 |
|
|
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
| 404 |
|
|
Phase 10 Post Router Timing | Checksum: 178289230
|
| 405 |
|
|
|
| 406 |
|
|
Time (s): cpu = 00:00:38 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1945 ; free virtual = 5527
|
| 407 |
|
|
INFO: [Route 35-16] Router Completed Successfully
|
| 408 |
|
|
|
| 409 |
|
|
Time (s): cpu = 00:00:38 ; elapsed = 00:00:24 . Memory (MB): peak = 2467.551 ; gain = 299.215 ; free physical = 1977 ; free virtual = 5559
|
| 410 |
|
|
|
| 411 |
|
|
Routing Is Done.
|
| 412 |
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
| 413 |
|
|
64 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
| 414 |
|
|
route_design completed successfully
|
| 415 |
|
|
route_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:26 . Memory (MB): peak = 2467.551 ; gain = 299.219 ; free physical = 1974 ; free virtual = 5557
|
| 416 |
|
|
Writing placer database...
|
| 417 |
|
|
Writing XDEF routing.
|
| 418 |
|
|
Writing XDEF routing logical nets.
|
| 419 |
|
|
Writing XDEF routing special nets.
|
| 420 |
|
|
Write XDEF Complete: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2467.551 ; gain = 0.000 ; free physical = 1968 ; free virtual = 5556
|
| 421 |
|
|
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap_routed.dcp' has been generated.
|
| 422 |
|
|
INFO: [runtcl-4] Executing : report_drc -file aes128_ecb_fpga_wrap_drc_routed.rpt -pb aes128_ecb_fpga_wrap_drc_routed.pb -rpx aes128_ecb_fpga_wrap_drc_routed.rpx
|
| 423 |
|
|
Command: report_drc -file aes128_ecb_fpga_wrap_drc_routed.rpt -pb aes128_ecb_fpga_wrap_drc_routed.pb -rpx aes128_ecb_fpga_wrap_drc_routed.rpx
|
| 424 |
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
| 425 |
|
|
INFO: [DRC 23-27] Running DRC with 4 threads
|
| 426 |
|
|
INFO: [Coretcl 2-168] The results of DRC are in file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap_drc_routed.rpt.
|
| 427 |
|
|
report_drc completed successfully
|
| 428 |
|
|
INFO: [runtcl-4] Executing : report_methodology -file aes128_ecb_fpga_wrap_methodology_drc_routed.rpt -pb aes128_ecb_fpga_wrap_methodology_drc_routed.pb -rpx aes128_ecb_fpga_wrap_methodology_drc_routed.rpx
|
| 429 |
|
|
Command: report_methodology -file aes128_ecb_fpga_wrap_methodology_drc_routed.rpt -pb aes128_ecb_fpga_wrap_methodology_drc_routed.pb -rpx aes128_ecb_fpga_wrap_methodology_drc_routed.rpx
|
| 430 |
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
| 431 |
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
| 432 |
|
|
INFO: [DRC 23-133] Running Methodology with 4 threads
|
| 433 |
|
|
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap_methodology_drc_routed.rpt.
|
| 434 |
|
|
report_methodology completed successfully
|
| 435 |
|
|
INFO: [runtcl-4] Executing : report_power -file aes128_ecb_fpga_wrap_power_routed.rpt -pb aes128_ecb_fpga_wrap_power_summary_routed.pb -rpx aes128_ecb_fpga_wrap_power_routed.rpx
|
| 436 |
|
|
Command: report_power -file aes128_ecb_fpga_wrap_power_routed.rpt -pb aes128_ecb_fpga_wrap_power_summary_routed.pb -rpx aes128_ecb_fpga_wrap_power_routed.rpx
|
| 437 |
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
| 438 |
|
|
Running Vector-less Activity Propagation...
|
| 439 |
|
|
|
| 440 |
|
|
Finished Running Vector-less Activity Propagation
|
| 441 |
|
|
76 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
| 442 |
|
|
report_power completed successfully
|
| 443 |
|
|
INFO: [runtcl-4] Executing : report_route_status -file aes128_ecb_fpga_wrap_route_status.rpt -pb aes128_ecb_fpga_wrap_route_status.pb
|
| 444 |
|
|
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file aes128_ecb_fpga_wrap_timing_summary_routed.rpt -rpx aes128_ecb_fpga_wrap_timing_summary_routed.rpx -warn_on_violation
|
| 445 |
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
|
| 446 |
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
|
| 447 |
|
|
INFO: [runtcl-4] Executing : report_incremental_reuse -file aes128_ecb_fpga_wrap_incremental_reuse_routed.rpt
|
| 448 |
|
|
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
|
| 449 |
|
|
INFO: [runtcl-4] Executing : report_clock_utilization -file aes128_ecb_fpga_wrap_clock_utilization_routed.rpt
|
| 450 |
|
|
report_clock_utilization: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2523.594 ; gain = 0.000 ; free physical = 1955 ; free virtual = 5541
|
| 451 |
|
|
Command: write_bitstream -force aes128_ecb_fpga_wrap.bit
|
| 452 |
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
|
| 453 |
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
|
| 454 |
|
|
Running DRC as a precondition to command write_bitstream
|
| 455 |
|
|
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
| 456 |
|
|
INFO: [DRC 23-27] Running DRC with 4 threads
|
| 457 |
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net sys_mngr/axi_state[0]_P_i_3_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[0]_P_i_3/O, cell sys_mngr/axi_state[0]_P_i_3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
| 458 |
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net sys_mngr/axi_state[10]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[10]_P_i_2/O, cell sys_mngr/axi_state[10]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
| 459 |
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net sys_mngr/axi_state[1]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[1]_P_i_2/O, cell sys_mngr/axi_state[1]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
| 460 |
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net sys_mngr/axi_state[2]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[2]_P_i_2/O, cell sys_mngr/axi_state[2]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
| 461 |
|
|
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port CLK_IN_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
|
| 462 |
|
|
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port CLK_IN_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
|
| 463 |
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 6 Warnings
|
| 464 |
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
| 465 |
|
|
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
|
| 466 |
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
|
| 467 |
|
|
Loading data files...
|
| 468 |
|
|
Loading site data...
|
| 469 |
|
|
Loading route data...
|
| 470 |
|
|
Processing options...
|
| 471 |
|
|
WARNING: [Designutils 20-2079] The BITSTREAM.CONFIG.EXTMASTERCCLK_EN property value "DIV-2" will cause the BITSTREAM.CONFIG.CONFIGRATE property value "33" to be ignored.
|
| 472 |
|
|
Creating bitmap...
|
| 473 |
|
|
Creating bitstream...
|
| 474 |
|
|
Writing bitstream ./aes128_ecb_fpga_wrap.bit...
|
| 475 |
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
| 476 |
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
| 477 |
|
|
92 Infos, 11 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
| 478 |
|
|
write_bitstream completed successfully
|
| 479 |
|
|
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 2849.238 ; gain = 325.645 ; free physical = 1923 ; free virtual = 5520
|
| 480 |
|
|
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:56:36 2020...
|
| 481 |
|
|
|
| 482 |
|
|
*** Running vivado
|
| 483 |
|
|
with args -log aes128_ecb_fpga_wrap.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source aes128_ecb_fpga_wrap.tcl -notrace
|
| 484 |
|
|
|
| 485 |
|
|
|
| 486 |
|
|
****** Vivado v2017.4 (64-bit)
|
| 487 |
|
|
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
|
| 488 |
|
|
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
|
| 489 |
|
|
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
|
| 490 |
|
|
|
| 491 |
|
|
source aes128_ecb_fpga_wrap.tcl -notrace
|
| 492 |
|
|
Command: open_checkpoint aes128_ecb_fpga_wrap_routed.dcp
|
| 493 |
|
|
|
| 494 |
|
|
Starting open_checkpoint Task
|
| 495 |
|
|
|
| 496 |
|
|
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1163.023 ; gain = 0.000 ; free physical = 2264 ; free virtual = 6195
|
| 497 |
|
|
INFO: [Netlist 29-17] Analyzing 919 Unisim elements for replacement
|
| 498 |
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
| 499 |
|
|
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
|
| 500 |
|
|
INFO: [Device 21-403] Loading part xc7k325tffg900-2
|
| 501 |
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
| 502 |
|
|
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/.Xil/Vivado-15976-orme22/dcp1/aes128_ecb_fpga_wrap_board.xdc]
|
| 503 |
|
|
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/.Xil/Vivado-15976-orme22/dcp1/aes128_ecb_fpga_wrap_board.xdc]
|
| 504 |
|
|
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/.Xil/Vivado-15976-orme22/dcp1/aes128_ecb_fpga_wrap_early.xdc]
|
| 505 |
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
|
| 506 |
|
|
INFO: [Timing 38-2] Deriving generated clocks [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
|
| 507 |
|
|
get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:21 . Memory (MB): peak = 2028.965 ; gain = 549.656 ; free physical = 1506 ; free virtual = 5433
|
| 508 |
|
|
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/.Xil/Vivado-15976-orme22/dcp1/aes128_ecb_fpga_wrap_early.xdc]
|
| 509 |
|
|
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/.Xil/Vivado-15976-orme22/dcp1/aes128_ecb_fpga_wrap.xdc]
|
| 510 |
|
|
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/.Xil/Vivado-15976-orme22/dcp1/aes128_ecb_fpga_wrap.xdc]
|
| 511 |
|
|
Reading XDEF placement.
|
| 512 |
|
|
Reading placer database...
|
| 513 |
|
|
Reading XDEF routing.
|
| 514 |
|
|
Read XDEF File: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2032.965 ; gain = 4.000 ; free physical = 1502 ; free virtual = 5429
|
| 515 |
|
|
Restored from archive | CPU: 0.170000 secs | Memory: 4.270599 MB |
|
| 516 |
|
|
Finished XDEF File Restore: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2032.965 ; gain = 4.000 ; free physical = 1502 ; free virtual = 5429
|
| 517 |
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
| 518 |
|
|
No Unisim elements were transformed.
|
| 519 |
|
|
|
| 520 |
|
|
INFO: [Project 1-604] Checkpoint was created with Vivado v2017.4 (64-bit) build 2086221
|
| 521 |
|
|
open_checkpoint: Time (s): cpu = 00:00:23 ; elapsed = 00:00:41 . Memory (MB): peak = 2033.965 ; gain = 870.941 ; free physical = 1507 ; free virtual = 5428
|
| 522 |
|
|
Command: write_bitstream -force aes128_ecb_fpga_wrap.bit
|
| 523 |
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
|
| 524 |
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
|
| 525 |
|
|
Running DRC as a precondition to command write_bitstream
|
| 526 |
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
| 527 |
|
|
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
| 528 |
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
|
| 529 |
|
|
INFO: [DRC 23-27] Running DRC with 4 threads
|
| 530 |
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net sys_mngr/axi_state[0]_P_i_3_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[0]_P_i_3/O, cell sys_mngr/axi_state[0]_P_i_3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
| 531 |
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net sys_mngr/axi_state[10]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[10]_P_i_2/O, cell sys_mngr/axi_state[10]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
| 532 |
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net sys_mngr/axi_state[1]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[1]_P_i_2/O, cell sys_mngr/axi_state[1]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
| 533 |
|
|
WARNING: [DRC PDRC-153] Gated clock check: Net sys_mngr/axi_state[2]_P_i_2_n_0 is a gated clock net sourced by a combinational pin sys_mngr/axi_state[2]_P_i_2/O, cell sys_mngr/axi_state[2]_P_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
| 534 |
|
|
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port CLK_IN_N has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
|
| 535 |
|
|
WARNING: [DRC PORTPROP-2] selectio_diff_term: The port CLK_IN_P has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
|
| 536 |
|
|
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 6 Warnings
|
| 537 |
|
|
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
| 538 |
|
|
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
|
| 539 |
|
|
INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
|
| 540 |
|
|
Loading data files...
|
| 541 |
|
|
Loading site data...
|
| 542 |
|
|
Loading route data...
|
| 543 |
|
|
Processing options...
|
| 544 |
|
|
WARNING: [Designutils 20-2079] The BITSTREAM.CONFIG.EXTMASTERCCLK_EN property value "DIV-2" will cause the BITSTREAM.CONFIG.CONFIGRATE property value "33" to be ignored.
|
| 545 |
|
|
Creating bitmap...
|
| 546 |
|
|
Creating bitstream...
|
| 547 |
|
|
Writing bitstream ./aes128_ecb_fpga_wrap.bit...
|
| 548 |
|
|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
| 549 |
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
| 550 |
|
|
20 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
| 551 |
|
|
write_bitstream completed successfully
|
| 552 |
|
|
write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 2589.641 ; gain = 555.676 ; free physical = 1443 ; free virtual = 5370
|
| 553 |
|
|
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 15:32:07 2020...
|
