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vv_gulyaev |
#
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# Synthesis run script generated by Vivado
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#
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proc create_report { reportName command } {
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set status "."
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append status $reportName ".fail"
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if { [file exists $status] } {
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eval file delete [glob $status]
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}
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send_msg_id runtcl-4 info "Executing : $command"
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set retval [eval catch { $command } msg]
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if { $retval != 0 } {
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set fp [open $status w]
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close $fp
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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set_param xicom.use_bs_reader 1
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create_project -in_memory -part xc7k325tffg900-2
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set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
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set_property webtalk.parent_dir /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.cache/wt [current_project]
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set_property parent.project_path /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr [current_project]
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set_property XPM_LIBRARIES XPM_CDC [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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set_property board_part xilinx.com:kc705:part0:1.5 [current_project]
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set_property ip_output_repo /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.cache/ip [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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read_verilog -library xil_defaultlib -sv {
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/home/user/aes128/src/aes128_enc.sv
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/home/user/aes128/src/wrap/axi_interface.sv
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/home/user/aes128/src/wrap/system_manager.sv
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/home/user/aes128/src/wrap/aes128_ecb_fpga_wrap.sv
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}
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read_ip -quiet /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xci
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set_property used_in_implementation false [get_files -all /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc]
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set_property used_in_implementation false [get_files -all /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc]
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set_property used_in_implementation false [get_files -all /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_ooc.xdc]
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read_ip -quiet /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xci
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set_property used_in_implementation false [get_files -all /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc]
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set_property used_in_implementation false [get_files -all /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_ooc.xdc]
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set_property used_in_implementation false [get_files -all /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc]
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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# design are intentionally left as such for best results. Dcp files will be
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# stitched into the design at a later time, either when this synthesis run is
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# opened, or when it is stitched into a dependent implementation run.
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foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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set_property used_in_implementation false $dcp
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}
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read_xdc /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc
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set_property used_in_implementation false [get_files /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
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read_xdc /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc
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set_property used_in_implementation false [get_files /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc]
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synth_design -top aes128_ecb_fpga_wrap -part xc7k325tffg900-2
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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write_checkpoint -force -noxdef aes128_ecb_fpga_wrap.dcp
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file aes128_ecb_fpga_wrap_utilization_synth.rpt -pb aes128_ecb_fpga_wrap_utilization_synth.pb"
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