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URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [synth_1/] [aes128_ecb_fpga_wrap.vds] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev 
#-----------------------------------------------------------
2 
# Vivado v2017.4 (64-bit)
3 
# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
4 
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
5 
# Start of session at: Thu Jul 30 13:52:02 2020
6 
# Process ID: 9700
7 
# Current directory: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1
8 
# Command line: vivado -log aes128_ecb_fpga_wrap.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source aes128_ecb_fpga_wrap.tcl
9 
# Log file: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/aes128_ecb_fpga_wrap.vds
10 
# Journal file: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/vivado.jou
11 
#-----------------------------------------------------------
12 
source aes128_ecb_fpga_wrap.tcl -notrace
13 
Command: synth_design -top aes128_ecb_fpga_wrap -part xc7k325tffg900-2
14 
Starting synth_design
15 
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
16 
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
17 
INFO: Launching helper process for spawning children vivado processes
18 
INFO: Helper process launched with PID 9709
19 
---------------------------------------------------------------------------------
20 
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1279.145 ; gain = 86.996 ; free physical = 1340 ; free virtual = 6471
21 
---------------------------------------------------------------------------------
22 
INFO: [Synth 8-638] synthesizing module 'aes128_ecb_fpga_wrap' [/home/user/aes128/src/wrap/aes128_ecb_fpga_wrap.sv:1]
23 
INFO: [Synth 8-638] synthesizing module 'axi_interface' [/home/user/aes128/src/wrap/axi_interface.sv:1]
24 
INFO: [Synth 8-256] done synthesizing module 'axi_interface' (0#1) [/home/user/aes128/src/wrap/axi_interface.sv:1]
25 
INFO: [Synth 8-638] synthesizing module 'clk_gen' [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/realtime/clk_gen_stub.v:5]
26 
INFO: [Synth 8-256] done synthesizing module 'clk_gen' (1#1) [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/realtime/clk_gen_stub.v:5]
27 
INFO: [Synth 8-638] synthesizing module 'aes128_enc' [/home/user/aes128/src/aes128_enc.sv:1]
28 
        Parameter Sbox bound to: 2048'b01100011011111000111011101111011111100100110101101101111110001010011000000000001011001110010101111111110110101111010101101110110110010101000001011001001011111011111101001011001010001111111000010101101110101001010001010101111100111001010010001110010110000001011011111111101100100110010011000110110001111111111011111001100001101001010010111100101111100010111000111011000001100010001010100000100110001110010001111000011000110001001011000000101100110100000011100010010100000001110001011101011001001111011001001110101000010011000001100101100000110100001101101101110010110101010000001010010001110111101011010110011001010011110001100101111100001000101001111010001000000001110110100100000111111001011000101011011011010101100101110111110001110010100101001001100010110001100111111010000111011111010101011111011010000110100110100110011100001010100010111111001000000100111111101010000001111001001111110101000010100011010001101000000100011111001001010011101001110001111010110111100101101101101101000100001000100001111111111110011110100101100110100001100000100111110110001011111100101110100010000010111110001001010011101111110001111010110010001011101000110010111001101100000100000010100111111011100001000100010101010010000100010000100011011101110101110000001010011011110010111100000101111011011111000000011001000111010000010100100100100000110001001000101110011000010110100111010110001100010100100011001010111100100011110011110011111001000001101110110110110001101110101010100111010101001011011000101011011110100111010100110010101111010101011100000100010111010011110000010010100101110000111001010011010110100110001101110100011011101011101000001111101001011101111011000101110001010011100000011111010110101011001100100100000000011111101100000111001100001001101010101011110111001100001101100000100011101100111101110000111111000100110000001000101101001110110011000111010010100100110110001111010000111111010011100111001010101001010001101111110001100101000011000100100001101101111111110011001000010011010000100000110011001001011010000111110110000010101001011101100010110
29 
        Parameter Rcon bound to: 320'b00000001000000100000010000001000000100000010000001000000100000000001101100110110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
30 
WARNING: [Synth 8-5856] 3D RAM state_reg  for this pattern/configuration is not supported. This will most likely be implemented in registers
31 
WARNING: [Synth 8-5856] 3D RAM round_key_reg  for this pattern/configuration is not supported. This will most likely be implemented in registers
32 
INFO: [Synth 8-256] done synthesizing module 'aes128_enc' (2#1) [/home/user/aes128/src/aes128_enc.sv:1]
33 
INFO: [Synth 8-638] synthesizing module 'axi_uartlite_module' [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/realtime/axi_uartlite_module_stub.v:6]
34 
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite_module' (3#1) [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/realtime/axi_uartlite_module_stub.v:6]
35 
INFO: [Synth 8-638] synthesizing module 'system_manager' [/home/user/aes128/src/wrap/system_manager.sv:1]
36 
        Parameter STARTUP_PAUSE_DUTY bound to: 100 - type: integer
37 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:215]
38 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:336]
39 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:269]
40 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:431]
41 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:480]
42 
WARNING: [Synth 8-6014] Unused sequential element rd_data_reg_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:161]
43 
WARNING: [Synth 8-6014] Unused sequential element rx_fifo_full_reg_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:163]
44 
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_empty_reg_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:164]
45 
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_full_reg_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:165]
46 
WARNING: [Synth 8-5788] Register axi_state_reg in module system_manager is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code  [/home/user/aes128/src/wrap/system_manager.sv:408]
47 
INFO: [Synth 8-256] done synthesizing module 'system_manager' (4#1) [/home/user/aes128/src/wrap/system_manager.sv:1]
48 
INFO: [Synth 8-256] done synthesizing module 'aes128_ecb_fpga_wrap' (5#1) [/home/user/aes128/src/wrap/aes128_ecb_fpga_wrap.sv:1]
49 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[31]
50 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[30]
51 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[29]
52 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[28]
53 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[27]
54 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[26]
55 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[25]
56 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[24]
57 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[23]
58 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[22]
59 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[21]
60 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[20]
61 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[19]
62 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[18]
63 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[17]
64 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[16]
65 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[15]
66 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[14]
67 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[13]
68 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[12]
69 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[11]
70 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[10]
71 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[9]
72 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[8]
73 
---------------------------------------------------------------------------------
74 
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1353.676 ; gain = 161.527 ; free physical = 1318 ; free virtual = 6450
75 
---------------------------------------------------------------------------------
76 
 
77 
Report Check Netlist:
78 
+------+------------------+-------+---------+-------+------------------+
79 
|      |Item              |Errors |Warnings |Status |Description       |
80 
+------+------------------+-------+---------+-------+------------------+
81 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
82 
+------+------------------+-------+---------+-------+------------------+
83 
---------------------------------------------------------------------------------
84 
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1353.676 ; gain = 161.527 ; free physical = 1327 ; free virtual = 6459
85 
---------------------------------------------------------------------------------
86 
INFO: [Device 21-403] Loading part xc7k325tffg900-2
87 
INFO: [Project 1-570] Preparing netlist for logic optimization
88 
 
89 
Processing XDC Constraints
90 
Initializing timing engine
91 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc] for cell 'clkgen'
92 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc] for cell 'clkgen'
93 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp3/axi_uartlite_module_in_context.xdc] for cell 'uartlite'
94 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp3/axi_uartlite_module_in_context.xdc] for cell 'uartlite'
95 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
96 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
97 
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/aes128_ecb_fpga_wrap_propImpl.xdc].
98 
Resolution: To avoid this warning, move constraints listed in [.Xil/aes128_ecb_fpga_wrap_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
99 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc]
100 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc]
101 
Completed Processing XDC Constraints
102 
 
103 
INFO: [Project 1-111] Unisim Transformation Summary:
104 
No Unisim elements were transformed.
105 
 
106 
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1735.738 ; gain = 0.000 ; free physical = 1013 ; free virtual = 6145
107 
---------------------------------------------------------------------------------
108 
Finished Constraint Validation : Time (s): cpu = 00:00:25 ; elapsed = 00:00:35 . Memory (MB): peak = 1735.738 ; gain = 543.590 ; free physical = 1107 ; free virtual = 6239
109 
---------------------------------------------------------------------------------
110 
---------------------------------------------------------------------------------
111 
Start Loading Part and Timing Information
112 
---------------------------------------------------------------------------------
113 
Loading part: xc7k325tffg900-2
114 
---------------------------------------------------------------------------------
115 
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:25 ; elapsed = 00:00:35 . Memory (MB): peak = 1735.738 ; gain = 543.590 ; free physical = 1107 ; free virtual = 6239
116 
---------------------------------------------------------------------------------
117 
---------------------------------------------------------------------------------
118 
Start Applying 'set_property' XDC Constraints
119 
---------------------------------------------------------------------------------
120 
Applied set_property IO_BUFFER_TYPE = NONE for CLK_IN_N. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc, line 3).
121 
Applied set_property CLOCK_BUFFER_TYPE = NONE for CLK_IN_N. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc, line 4).
122 
Applied set_property IO_BUFFER_TYPE = NONE for CLK_IN_P. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc, line 5).
123 
Applied set_property CLOCK_BUFFER_TYPE = NONE for CLK_IN_P. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc, line 6).
124 
Applied set_property DONT_TOUCH = true for clkgen. (constraint file  auto generated constraint, line ).
125 
Applied set_property DONT_TOUCH = true for uartlite. (constraint file  auto generated constraint, line ).
126 
---------------------------------------------------------------------------------
127 
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:35 . Memory (MB): peak = 1735.738 ; gain = 543.590 ; free physical = 1107 ; free virtual = 6239
128 
---------------------------------------------------------------------------------
129 
INFO: [Synth 8-5544] ROM "busy" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
130 
INFO: [Synth 8-5544] ROM "valid_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
131 
INFO: [Synth 8-4471] merging register 'm_axi\.wvalid_reg' into 'm_axi\.awvalid_reg' [/home/user/aes128/src/wrap/system_manager.sv:402]
132 
WARNING: [Synth 8-6014] Unused sequential element m_axi\.wvalid_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:402]
133 
INFO: [Synth 8-802] inferred FSM for state register 'sys_state_reg' in module 'system_manager'
134 
INFO: [Synth 8-5545] ROM "startup_pause_complete" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
135 
INFO: [Synth 8-5546] ROM "key_set_complete" won't be mapped to RAM because it is too sparse
136 
INFO: [Synth 8-5544] ROM "key_set_complete" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
137 
INFO: [Synth 8-5546] ROM "plain_text_set_in_progress" won't be mapped to RAM because it is too sparse
138 
INFO: [Synth 8-5546] ROM "data_counter" won't be mapped to RAM because it is too sparse
139 
INFO: [Synth 8-5544] ROM "cipher_data" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
140 
INFO: [Synth 8-5546] ROM "get_stat" won't be mapped to RAM because it is too sparse
141 
INFO: [Synth 8-5545] ROM "check_stat" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
142 
INFO: [Synth 8-5544] ROM "sys_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
143 
WARNING: [Synth 8-6014] Unused sequential element startup_pause_cnt_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:145]
144 
INFO: [Synth 8-5545] ROM "startup_pause_complete" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
145 
INFO: [Synth 8-5546] ROM "key_set_complete" won't be mapped to RAM because it is too sparse
146 
INFO: [Synth 8-5544] ROM "key_set_complete" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
147 
INFO: [Synth 8-5546] ROM "plain_text_set_in_progress" won't be mapped to RAM because it is too sparse
148 
INFO: [Synth 8-5546] ROM "data_counter" won't be mapped to RAM because it is too sparse
149 
INFO: [Synth 8-5544] ROM "cipher_data" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
150 
INFO: [Synth 8-5546] ROM "get_stat" won't be mapped to RAM because it is too sparse
151 
INFO: [Synth 8-5545] ROM "check_stat" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
152 
INFO: [Synth 8-5544] ROM "sys_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
153 
INFO: [Synth 8-5544] ROM "addr" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
154 
INFO: [Synth 8-5544] ROM "axi_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
155 
INFO: [Synth 8-5544] ROM "axi_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
156 
INFO: [Synth 8-5544] ROM "axi_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
157 
---------------------------------------------------------------------------------------------------
158 
                   State |                     New Encoding |                Previous Encoding
159 
---------------------------------------------------------------------------------------------------
160 
                SYS_IDLE |                              000 | 00000000000000000000000000000000
161 
      INIT_UART_CTRL_REG |                              001 | 00000000000000000000000000000001
162 
        RD_UART_STAT_REG |                              010 | 00000000000000000000000000000010
163 
              RD_RX_FIFO |                              011 | 00000000000000000000000000000011
164 
              WR_TX_FIFO |                              100 | 00000000000000000000000000000100
165 
---------------------------------------------------------------------------------------------------
166 
INFO: [Synth 8-3354] encoded FSM with state register 'sys_state_reg' using encoding 'sequential' in module 'system_manager'
167 
---------------------------------------------------------------------------------
168 
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 1735.738 ; gain = 543.590 ; free physical = 1072 ; free virtual = 6204
169 
---------------------------------------------------------------------------------
170 
 
171 
Report RTL Partitions:
172 
+------+--------------------------+------------+----------+
173 
|      |RTL Partition             |Replication |Instances |
174 
+------+--------------------------+------------+----------+
175 
|1     |aes128_enc__GB0           |           1|     32784|
176 
|2     |aes128_enc__GB1           |           1|      6120|
177 
|3     |aes128_enc__GB2           |           1|      4699|
178 
|4     |aes128_enc__GB3           |           1|     10352|
179 
|5     |aes128_enc__GB4           |           1|     11267|
180 
|6     |aes128_enc__GB5           |           1|     20400|
181 
|7     |aes128_ecb_fpga_wrap__GC0 |           1|     21176|
182 
+------+--------------------------+------------+----------+
183 
---------------------------------------------------------------------------------
184 
Start RTL Component Statistics
185 
---------------------------------------------------------------------------------
186 
Detailed RTL Component Info :
187 
+---Adders :
188 
           2 Input      4 Bit       Adders := 2
189 
           2 Input      2 Bit       Adders := 1
190 
+---XORs :
191 
           2 Input    128 Bit         XORs := 1
192 
           4 Input      8 Bit         XORs := 8
193 
           2 Input      8 Bit         XORs := 86
194 
           5 Input      8 Bit         XORs := 16
195 
           6 Input      8 Bit         XORs := 8
196 
           3 Input      8 Bit         XORs := 2
197 
+---Registers :
198 
                      128 Bit    Registers := 4
199 
                       32 Bit    Registers := 1
200 
                        8 Bit    Registers := 34
201 
                        4 Bit    Registers := 6
202 
                        2 Bit    Registers := 1
203 
                        1 Bit    Registers := 19
204 
+---Muxes :
205 
           2 Input    128 Bit        Muxes := 15
206 
           4 Input    128 Bit        Muxes := 1
207 
           3 Input    128 Bit        Muxes := 1
208 
           5 Input    128 Bit        Muxes := 5
209 
           2 Input     32 Bit        Muxes := 4
210 
           6 Input     32 Bit        Muxes := 2
211 
           2 Input      8 Bit        Muxes := 85
212 
           6 Input      8 Bit        Muxes := 3
213 
           5 Input      8 Bit        Muxes := 2
214 
           2 Input      4 Bit        Muxes := 10
215 
           5 Input      4 Bit        Muxes := 2
216 
           6 Input      4 Bit        Muxes := 3
217 
           2 Input      3 Bit        Muxes := 1
218 
           7 Input      3 Bit        Muxes := 1
219 
           2 Input      1 Bit        Muxes := 30
220 
           6 Input      1 Bit        Muxes := 11
221 
           4 Input      1 Bit        Muxes := 3
222 
           5 Input      1 Bit        Muxes := 24
223 
           3 Input      1 Bit        Muxes := 1
224 
---------------------------------------------------------------------------------
225 
Finished RTL Component Statistics
226 
---------------------------------------------------------------------------------
227 
---------------------------------------------------------------------------------
228 
Start RTL Hierarchical Component Statistics
229 
---------------------------------------------------------------------------------
230 
Hierarchical RTL Component report
231 
Module aes128_ecb_fpga_wrap
232 
Detailed RTL Component Info :
233 
+---Adders :
234 
           2 Input      2 Bit       Adders := 1
235 
+---Registers :
236 
                        2 Bit    Registers := 1
237 
Module aes128_enc
238 
Detailed RTL Component Info :
239 
+---Adders :
240 
           2 Input      4 Bit       Adders := 1
241 
+---XORs :
242 
           2 Input    128 Bit         XORs := 1
243 
           4 Input      8 Bit         XORs := 8
244 
           2 Input      8 Bit         XORs := 86
245 
           5 Input      8 Bit         XORs := 16
246 
           6 Input      8 Bit         XORs := 8
247 
           3 Input      8 Bit         XORs := 2
248 
+---Registers :
249 
                      128 Bit    Registers := 1
250 
                        8 Bit    Registers := 32
251 
                        4 Bit    Registers := 1
252 
                        1 Bit    Registers := 2
253 
+---Muxes :
254 
           2 Input    128 Bit        Muxes := 3
255 
           2 Input      8 Bit        Muxes := 80
256 
           2 Input      4 Bit        Muxes := 3
257 
           2 Input      1 Bit        Muxes := 3
258 
Module system_manager
259 
Detailed RTL Component Info :
260 
+---Adders :
261 
           2 Input      4 Bit       Adders := 1
262 
+---Registers :
263 
                      128 Bit    Registers := 3
264 
                       32 Bit    Registers := 1
265 
                        8 Bit    Registers := 2
266 
                        4 Bit    Registers := 5
267 
                        1 Bit    Registers := 17
268 
+---Muxes :
269 
           2 Input    128 Bit        Muxes := 12
270 
           4 Input    128 Bit        Muxes := 1
271 
           3 Input    128 Bit        Muxes := 1
272 
           5 Input    128 Bit        Muxes := 5
273 
           2 Input     32 Bit        Muxes := 4
274 
           6 Input     32 Bit        Muxes := 2
275 
           2 Input      8 Bit        Muxes := 5
276 
           6 Input      8 Bit        Muxes := 3
277 
           5 Input      8 Bit        Muxes := 2
278 
           2 Input      4 Bit        Muxes := 7
279 
           5 Input      4 Bit        Muxes := 2
280 
           6 Input      4 Bit        Muxes := 3
281 
           2 Input      3 Bit        Muxes := 1
282 
           7 Input      3 Bit        Muxes := 1
283 
           2 Input      1 Bit        Muxes := 27
284 
           6 Input      1 Bit        Muxes := 11
285 
           4 Input      1 Bit        Muxes := 3
286 
           5 Input      1 Bit        Muxes := 24
287 
           3 Input      1 Bit        Muxes := 1
288 
---------------------------------------------------------------------------------
289 
Finished RTL Hierarchical Component Statistics
290 
---------------------------------------------------------------------------------
291 
---------------------------------------------------------------------------------
292 
Start Part Resource Summary
293 
---------------------------------------------------------------------------------
294 
Part Resources:
295 
DSPs: 840 (col length:140)
296 
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
297 
---------------------------------------------------------------------------------
298 
Finished Part Resource Summary
299 
---------------------------------------------------------------------------------
300 
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 4 processes.
301 
---------------------------------------------------------------------------------
302 
Start Cross Boundary and Area Optimization
303 
---------------------------------------------------------------------------------
304 
INFO: [Synth 8-5545] ROM "startup_pause_complete" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
305 
WARNING: [Synth 8-6014] Unused sequential element startup_pause_cnt_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:145]
306 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[31]
307 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[30]
308 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[29]
309 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[28]
310 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[27]
311 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[26]
312 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[25]
313 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[24]
314 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[23]
315 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[22]
316 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[21]
317 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[20]
318 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[19]
319 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[18]
320 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[17]
321 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[16]
322 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[15]
323 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[14]
324 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[13]
325 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[12]
326 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[11]
327 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[10]
328 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[9]
329 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[8]
330 
INFO: [Synth 8-3886] merging instance 'sys_mngr/addr_reg_reg[0]' (FDCE) to 'sys_mngr/addr_reg_reg[1]'
331 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sys_mngr/addr_reg_reg[1] )
332 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[19]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
333 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[18]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
334 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[17]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
335 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[23]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
336 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[22]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
337 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[21]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
338 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[20]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
339 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[29]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
340 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[28]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
341 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[31]' (FDCPE) to 'sys_mngr/axi_state_reg[30]'
342 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[30]' (FDCPE) to 'sys_mngr/axi_state_reg[27]'
343 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[25]' (FDCPE) to 'sys_mngr/axi_state_reg[27]'
344 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[24]' (FDCPE) to 'sys_mngr/axi_state_reg[27]'
345 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[27]' (FDCPE) to 'sys_mngr/axi_state_reg[26]'
346 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[26]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
347 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[5]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
348 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[3]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
349 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[4]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
350 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[9]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
351 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[8]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
352 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[7]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
353 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[6]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
354 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[14]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
355 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[13]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
356 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[16]' (FDCPE) to 'sys_mngr/axi_state_reg[15]'
357 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[15]' (FDCPE) to 'sys_mngr/axi_state_reg[12]'
358 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[12]' (FDCPE) to 'sys_mngr/axi_state_reg[11]'
359 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[11]' (FDCPE) to 'sys_mngr/axi_state_reg[10]'
360 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wstrb_reg[0]' (FDCE) to 'sys_mngr/m_axi\.wstrb_reg[3]'
361 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wstrb_reg[1]' (FDCE) to 'sys_mngr/m_axi\.wstrb_reg[3]'
362 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wstrb_reg[2]' (FDCE) to 'sys_mngr/m_axi\.wstrb_reg[3]'
363 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[8]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[9]'
364 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[9]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[10]'
365 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[10]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[11]'
366 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[11]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[12]'
367 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[12]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[13]'
368 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[13]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[14]'
369 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[14]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[15]'
370 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[15]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[16]'
371 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[16]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[17]'
372 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[17]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[18]'
373 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[18]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[19]'
374 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[19]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[20]'
375 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[20]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[21]'
376 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[21]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[22]'
377 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[22]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[23]'
378 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[23]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[24]'
379 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[24]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[25]'
380 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[25]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[26]'
381 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[26]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[27]'
382 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[27]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[28]'
383 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[28]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[29]'
384 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[29]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[30]'
385 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[30]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[31]'
386 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sys_mngr/m_axi\.wdata_reg[31] )
387 
---------------------------------------------------------------------------------
388 
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:01:32 . Memory (MB): peak = 1739.660 ; gain = 547.512 ; free physical = 300 ; free virtual = 4155
389 
---------------------------------------------------------------------------------
390 
 
391 
Report RTL Partitions:
392 
+------+--------------------------+------------+----------+
393 
|      |RTL Partition             |Replication |Instances |
394 
+------+--------------------------+------------+----------+
395 
|1     |aes128_enc__GB0           |           1|      8259|
396 
|2     |aes128_enc__GB1           |           1|      1218|
397 
|3     |aes128_enc__GB2           |           1|      1352|
398 
|4     |aes128_enc__GB3           |           1|      2182|
399 
|5     |aes128_enc__GB4           |           1|      2828|
400 
|6     |aes128_enc__GB5           |           1|      4060|
401 
|7     |aes128_ecb_fpga_wrap__GC0 |           1|      1924|
402 
+------+--------------------------+------------+----------+
403 
---------------------------------------------------------------------------------
404 
Start Applying XDC Timing Constraints
405 
---------------------------------------------------------------------------------
406 
INFO: [Synth 8-5578] Moved timing constraint from pin 'clkgen/clk_out1' to pin 'clkgen/bbstub_clk_out1/O'
407 
INFO: [Synth 8-5783] Moving clock source from hierarchical pin 'clkgen/clk_in1_p' to 'CLK_IN_P'
408 
INFO: [Synth 8-5819] Moved 2 constraints on hierarchical pins to their respective driving/loading pins
409 
---------------------------------------------------------------------------------
410 
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:45 ; elapsed = 00:01:40 . Memory (MB): peak = 1843.027 ; gain = 650.879 ; free physical = 170 ; free virtual = 4025
411 
---------------------------------------------------------------------------------
412 
---------------------------------------------------------------------------------
413 
Start Timing Optimization
414 
---------------------------------------------------------------------------------
415 
---------------------------------------------------------------------------------
416 
Finished Timing Optimization : Time (s): cpu = 00:01:13 ; elapsed = 00:02:08 . Memory (MB): peak = 2199.262 ; gain = 1007.113 ; free physical = 567 ; free virtual = 4111
417 
---------------------------------------------------------------------------------
418 
 
419 
Report RTL Partitions:
420 
+------+-------------------------+------------+----------+
421 
|      |RTL Partition            |Replication |Instances |
422 
+------+-------------------------+------------+----------+
423 
|1     |aes128_ecb_fpga_wrap_GT0 |           1|     21778|
424 
+------+-------------------------+------------+----------+
425 
---------------------------------------------------------------------------------
426 
Start Technology Mapping
427 
---------------------------------------------------------------------------------
428 
INFO: [Synth 8-3886] merging instance 'i_0/sys_mngr/cur_stat_reg_reg[0]' (FDCE) to 'i_0/sys_mngr/rx_fifo_valid_data_reg_reg'
429 
INFO: [Synth 8-3886] merging instance 'i_0/sys_mngr/m_axi\.wstrb_reg[3]' (FDCE) to 'i_0/sys_mngr/m_axi\.awvalid_reg'
430 
---------------------------------------------------------------------------------
431 
Finished Technology Mapping : Time (s): cpu = 00:01:13 ; elapsed = 00:02:20 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
432 
---------------------------------------------------------------------------------
433 
 
434 
Report RTL Partitions:
435 
+------+-------------------------+------------+----------+
436 
|      |RTL Partition            |Replication |Instances |
437 
+------+-------------------------+------------+----------+
438 
|1     |aes128_ecb_fpga_wrap_GT0 |           1|      4826|
439 
+------+-------------------------+------------+----------+
440 
---------------------------------------------------------------------------------
441 
Start IO Insertion
442 
---------------------------------------------------------------------------------
443 
---------------------------------------------------------------------------------
444 
Start Flattening Before IO Insertion
445 
---------------------------------------------------------------------------------
446 
---------------------------------------------------------------------------------
447 
Finished Flattening Before IO Insertion
448 
---------------------------------------------------------------------------------
449 
---------------------------------------------------------------------------------
450 
Start Final Netlist Cleanup
451 
---------------------------------------------------------------------------------
452 
---------------------------------------------------------------------------------
453 
Finished Final Netlist Cleanup
454 
---------------------------------------------------------------------------------
455 
---------------------------------------------------------------------------------
456 
Finished IO Insertion : Time (s): cpu = 00:01:14 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
457 
---------------------------------------------------------------------------------
458 
 
459 
Report Check Netlist:
460 
+------+------------------+-------+---------+-------+------------------+
461 
|      |Item              |Errors |Warnings |Status |Description       |
462 
+------+------------------+-------+---------+-------+------------------+
463 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
464 
+------+------------------+-------+---------+-------+------------------+
465 
---------------------------------------------------------------------------------
466 
Start Renaming Generated Instances
467 
---------------------------------------------------------------------------------
468 
---------------------------------------------------------------------------------
469 
Finished Renaming Generated Instances : Time (s): cpu = 00:01:14 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
470 
---------------------------------------------------------------------------------
471 
 
472 
Report RTL Partitions:
473 
+-+--------------+------------+----------+
474 
| |RTL Partition |Replication |Instances |
475 
+-+--------------+------------+----------+
476 
+-+--------------+------------+----------+
477 
---------------------------------------------------------------------------------
478 
Start Rebuilding User Hierarchy
479 
---------------------------------------------------------------------------------
480 
---------------------------------------------------------------------------------
481 
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
482 
---------------------------------------------------------------------------------
483 
---------------------------------------------------------------------------------
484 
Start Renaming Generated Ports
485 
---------------------------------------------------------------------------------
486 
---------------------------------------------------------------------------------
487 
Finished Renaming Generated Ports : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
488 
---------------------------------------------------------------------------------
489 
---------------------------------------------------------------------------------
490 
Start Handling Custom Attributes
491 
---------------------------------------------------------------------------------
492 
---------------------------------------------------------------------------------
493 
Finished Handling Custom Attributes : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 435 ; free virtual = 3980
494 
---------------------------------------------------------------------------------
495 
---------------------------------------------------------------------------------
496 
Start Renaming Generated Nets
497 
---------------------------------------------------------------------------------
498 
---------------------------------------------------------------------------------
499 
Finished Renaming Generated Nets : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 435 ; free virtual = 3980
500 
---------------------------------------------------------------------------------
501 
---------------------------------------------------------------------------------
502 
Start Writing Synthesis Report
503 
---------------------------------------------------------------------------------
504 
 
505 
Report BlackBoxes:
506 
+------+--------------------+----------+
507 
|      |BlackBox name       |Instances |
508 
+------+--------------------+----------+
509 
|1     |clk_gen             |         1|
510 
|2     |axi_uartlite_module |         1|
511 
+------+--------------------+----------+
512 
 
513 
Report Cell Usage:
514 
+------+--------------------+------+
515 
|      |Cell                |Count |
516 
+------+--------------------+------+
517 
|1     |axi_uartlite_module |     1|
518 
|2     |clk_gen             |     1|
519 
|3     |CARRY4              |     8|
520 
|4     |LUT1                |     3|
521 
|5     |LUT2                |   435|
522 
|6     |LUT3                |   306|
523 
|7     |LUT4                |   154|
524 
|8     |LUT5                |   220|
525 
|9     |LUT6                |  1930|
526 
|10    |MUXF7               |   637|
527 
|11    |MUXF8               |   270|
528 
|12    |FDCE                |   868|
529 
|13    |FDPE                |     4|
530 
|14    |LDC                 |     4|
531 
|15    |IBUF                |     2|
532 
|16    |OBUF                |     5|
533 
+------+--------------------+------+
534 
 
535 
Report Instance Areas:
536 
+------+-----------+---------------+------+
537 
|      |Instance   |Module         |Cells |
538 
+------+-----------+---------------+------+
539 
|1     |top        |               |  4891|
540 
|2     |  enc      |aes128_enc     |  2095|
541 
|3     |  sys_mngr |system_manager |  2740|
542 
+------+-----------+---------------+------+
543 
---------------------------------------------------------------------------------
544 
Finished Writing Synthesis Report : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 435 ; free virtual = 3980
545 
---------------------------------------------------------------------------------
546 
Synthesis finished with 0 errors, 0 critical warnings and 27 warnings.
547 
Synthesis Optimization Runtime : Time (s): cpu = 00:01:06 ; elapsed = 00:02:07 . Memory (MB): peak = 2211.188 ; gain = 636.977 ; free physical = 2600 ; free virtual = 6146
548 
Synthesis Optimization Complete : Time (s): cpu = 00:01:15 ; elapsed = 00:02:26 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 2603 ; free virtual = 6146
549 
INFO: [Project 1-571] Translating synthesized netlist
550 
INFO: [Netlist 29-17] Analyzing 921 Unisim elements for replacement
551 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
552 
INFO: [Project 1-570] Preparing netlist for logic optimization
553 
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
554 
INFO: [Project 1-111] Unisim Transformation Summary:
555 
  A total of 4 instances were transformed.
556 
  LDC => LDCE: 4 instances
557 
 
558 
INFO: [Common 17-83] Releasing license: Synthesis
559 
120 Infos, 58 Warnings, 0 Critical Warnings and 0 Errors encountered.
560 
synth_design completed successfully
561 
synth_design: Time (s): cpu = 00:01:17 ; elapsed = 00:02:28 . Memory (MB): peak = 2223.273 ; gain = 1058.230 ; free physical = 2595 ; free virtual = 6139
562 
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/aes128_ecb_fpga_wrap.dcp' has been generated.
563 
INFO: [runtcl-4] Executing : report_utilization -file aes128_ecb_fpga_wrap_utilization_synth.rpt -pb aes128_ecb_fpga_wrap_utilization_synth.pb
564 
report_utilization: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2247.285 ; gain = 0.000 ; free physical = 2593 ; free virtual = 6139
565 
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:54:39 2020...

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