OpenCores
URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.runs/] [synth_1/] [runme.log] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 vv_gulyaev 
 
2 
*** Running vivado
3 
    with args -log aes128_ecb_fpga_wrap.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source aes128_ecb_fpga_wrap.tcl
4 
 
5 
 
6 
****** Vivado v2017.4 (64-bit)
7 
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
8 
  **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
9 
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
10 
 
11 
source aes128_ecb_fpga_wrap.tcl -notrace
12 
Command: synth_design -top aes128_ecb_fpga_wrap -part xc7k325tffg900-2
13 
Starting synth_design
14 
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
15 
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
16 
INFO: Launching helper process for spawning children vivado processes
17 
INFO: Helper process launched with PID 9709
18 
---------------------------------------------------------------------------------
19 
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1279.145 ; gain = 86.996 ; free physical = 1340 ; free virtual = 6471
20 
---------------------------------------------------------------------------------
21 
INFO: [Synth 8-638] synthesizing module 'aes128_ecb_fpga_wrap' [/home/user/aes128/src/wrap/aes128_ecb_fpga_wrap.sv:1]
22 
INFO: [Synth 8-638] synthesizing module 'axi_interface' [/home/user/aes128/src/wrap/axi_interface.sv:1]
23 
INFO: [Synth 8-256] done synthesizing module 'axi_interface' (0#1) [/home/user/aes128/src/wrap/axi_interface.sv:1]
24 
INFO: [Synth 8-638] synthesizing module 'clk_gen' [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/realtime/clk_gen_stub.v:5]
25 
INFO: [Synth 8-256] done synthesizing module 'clk_gen' (1#1) [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/realtime/clk_gen_stub.v:5]
26 
INFO: [Synth 8-638] synthesizing module 'aes128_enc' [/home/user/aes128/src/aes128_enc.sv:1]
27 
        Parameter Sbox bound to: 2048'b01100011011111000111011101111011111100100110101101101111110001010011000000000001011001110010101111111110110101111010101101110110110010101000001011001001011111011111101001011001010001111111000010101101110101001010001010101111100111001010010001110010110000001011011111111101100100110010011000110110001111111111011111001100001101001010010111100101111100010111000111011000001100010001010100000100110001110010001111000011000110001001011000000101100110100000011100010010100000001110001011101011001001111011001001110101000010011000001100101100000110100001101101101110010110101010000001010010001110111101011010110011001010011110001100101111100001000101001111010001000000001110110100100000111111001011000101011011011010101100101110111110001110010100101001001100010110001100111111010000111011111010101011111011010000110100110100110011100001010100010111111001000000100111111101010000001111001001111110101000010100011010001101000000100011111001001010011101001110001111010110111100101101101101101000100001000100001111111111110011110100101100110100001100000100111110110001011111100101110100010000010111110001001010011101111110001111010110010001011101000110010111001101100000100000010100111111011100001000100010101010010000100010000100011011101110101110000001010011011110010111100000101111011011111000000011001000111010000010100100100100000110001001000101110011000010110100111010110001100010100100011001010111100100011110011110011111001000001101110110110110001101110101010100111010101001011011000101011011110100111010100110010101111010101011100000100010111010011110000010010100101110000111001010011010110100110001101110100011011101011101000001111101001011101111011000101110001010011100000011111010110101011001100100100000000011111101100000111001100001001101010101011110111001100001101100000100011101100111101110000111111000100110000001000101101001110110011000111010010100100110110001111010000111111010011100111001010101001010001101111110001100101000011000100100001101101111111110011001000010011010000100000110011001001011010000111110110000010101001011101100010110
28 
        Parameter Rcon bound to: 320'b00000001000000100000010000001000000100000010000001000000100000000001101100110110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
29 
WARNING: [Synth 8-5856] 3D RAM state_reg  for this pattern/configuration is not supported. This will most likely be implemented in registers
30 
WARNING: [Synth 8-5856] 3D RAM round_key_reg  for this pattern/configuration is not supported. This will most likely be implemented in registers
31 
INFO: [Synth 8-256] done synthesizing module 'aes128_enc' (2#1) [/home/user/aes128/src/aes128_enc.sv:1]
32 
INFO: [Synth 8-638] synthesizing module 'axi_uartlite_module' [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/realtime/axi_uartlite_module_stub.v:6]
33 
INFO: [Synth 8-256] done synthesizing module 'axi_uartlite_module' (3#1) [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/realtime/axi_uartlite_module_stub.v:6]
34 
INFO: [Synth 8-638] synthesizing module 'system_manager' [/home/user/aes128/src/wrap/system_manager.sv:1]
35 
        Parameter STARTUP_PAUSE_DUTY bound to: 100 - type: integer
36 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:215]
37 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:336]
38 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:269]
39 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:431]
40 
INFO: [Synth 8-155] case statement is not full and has no default [/home/user/aes128/src/wrap/system_manager.sv:480]
41 
WARNING: [Synth 8-6014] Unused sequential element rd_data_reg_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:161]
42 
WARNING: [Synth 8-6014] Unused sequential element rx_fifo_full_reg_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:163]
43 
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_empty_reg_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:164]
44 
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_full_reg_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:165]
45 
WARNING: [Synth 8-5788] Register axi_state_reg in module system_manager is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code  [/home/user/aes128/src/wrap/system_manager.sv:408]
46 
INFO: [Synth 8-256] done synthesizing module 'system_manager' (4#1) [/home/user/aes128/src/wrap/system_manager.sv:1]
47 
INFO: [Synth 8-256] done synthesizing module 'aes128_ecb_fpga_wrap' (5#1) [/home/user/aes128/src/wrap/aes128_ecb_fpga_wrap.sv:1]
48 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[31]
49 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[30]
50 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[29]
51 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[28]
52 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[27]
53 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[26]
54 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[25]
55 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[24]
56 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[23]
57 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[22]
58 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[21]
59 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[20]
60 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[19]
61 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[18]
62 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[17]
63 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[16]
64 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[15]
65 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[14]
66 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[13]
67 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[12]
68 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[11]
69 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[10]
70 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[9]
71 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[8]
72 
---------------------------------------------------------------------------------
73 
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1353.676 ; gain = 161.527 ; free physical = 1318 ; free virtual = 6450
74 
---------------------------------------------------------------------------------
75 
 
76 
Report Check Netlist:
77 
+------+------------------+-------+---------+-------+------------------+
78 
|      |Item              |Errors |Warnings |Status |Description       |
79 
+------+------------------+-------+---------+-------+------------------+
80 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
81 
+------+------------------+-------+---------+-------+------------------+
82 
---------------------------------------------------------------------------------
83 
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1353.676 ; gain = 161.527 ; free physical = 1327 ; free virtual = 6459
84 
---------------------------------------------------------------------------------
85 
INFO: [Device 21-403] Loading part xc7k325tffg900-2
86 
INFO: [Project 1-570] Preparing netlist for logic optimization
87 
 
88 
Processing XDC Constraints
89 
Initializing timing engine
90 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc] for cell 'clkgen'
91 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc] for cell 'clkgen'
92 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp3/axi_uartlite_module_in_context.xdc] for cell 'uartlite'
93 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp3/axi_uartlite_module_in_context.xdc] for cell 'uartlite'
94 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
95 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
96 
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/pinout.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/aes128_ecb_fpga_wrap_propImpl.xdc].
97 
Resolution: To avoid this warning, move constraints listed in [.Xil/aes128_ecb_fpga_wrap_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
98 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc]
99 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/constrs_1/new/timings.xdc]
100 
Completed Processing XDC Constraints
101 
 
102 
INFO: [Project 1-111] Unisim Transformation Summary:
103 
No Unisim elements were transformed.
104 
 
105 
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1735.738 ; gain = 0.000 ; free physical = 1013 ; free virtual = 6145
106 
---------------------------------------------------------------------------------
107 
Finished Constraint Validation : Time (s): cpu = 00:00:25 ; elapsed = 00:00:35 . Memory (MB): peak = 1735.738 ; gain = 543.590 ; free physical = 1107 ; free virtual = 6239
108 
---------------------------------------------------------------------------------
109 
---------------------------------------------------------------------------------
110 
Start Loading Part and Timing Information
111 
---------------------------------------------------------------------------------
112 
Loading part: xc7k325tffg900-2
113 
---------------------------------------------------------------------------------
114 
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:25 ; elapsed = 00:00:35 . Memory (MB): peak = 1735.738 ; gain = 543.590 ; free physical = 1107 ; free virtual = 6239
115 
---------------------------------------------------------------------------------
116 
---------------------------------------------------------------------------------
117 
Start Applying 'set_property' XDC Constraints
118 
---------------------------------------------------------------------------------
119 
Applied set_property IO_BUFFER_TYPE = NONE for CLK_IN_N. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc, line 3).
120 
Applied set_property CLOCK_BUFFER_TYPE = NONE for CLK_IN_N. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc, line 4).
121 
Applied set_property IO_BUFFER_TYPE = NONE for CLK_IN_P. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc, line 5).
122 
Applied set_property CLOCK_BUFFER_TYPE = NONE for CLK_IN_P. (constraint file  /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/.Xil/Vivado-9700-orme22/dcp2/clk_gen_in_context.xdc, line 6).
123 
Applied set_property DONT_TOUCH = true for clkgen. (constraint file  auto generated constraint, line ).
124 
Applied set_property DONT_TOUCH = true for uartlite. (constraint file  auto generated constraint, line ).
125 
---------------------------------------------------------------------------------
126 
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:35 . Memory (MB): peak = 1735.738 ; gain = 543.590 ; free physical = 1107 ; free virtual = 6239
127 
---------------------------------------------------------------------------------
128 
INFO: [Synth 8-5544] ROM "busy" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
129 
INFO: [Synth 8-5544] ROM "valid_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
130 
INFO: [Synth 8-4471] merging register 'm_axi\.wvalid_reg' into 'm_axi\.awvalid_reg' [/home/user/aes128/src/wrap/system_manager.sv:402]
131 
WARNING: [Synth 8-6014] Unused sequential element m_axi\.wvalid_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:402]
132 
INFO: [Synth 8-802] inferred FSM for state register 'sys_state_reg' in module 'system_manager'
133 
INFO: [Synth 8-5545] ROM "startup_pause_complete" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
134 
INFO: [Synth 8-5546] ROM "key_set_complete" won't be mapped to RAM because it is too sparse
135 
INFO: [Synth 8-5544] ROM "key_set_complete" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
136 
INFO: [Synth 8-5546] ROM "plain_text_set_in_progress" won't be mapped to RAM because it is too sparse
137 
INFO: [Synth 8-5546] ROM "data_counter" won't be mapped to RAM because it is too sparse
138 
INFO: [Synth 8-5544] ROM "cipher_data" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
139 
INFO: [Synth 8-5546] ROM "get_stat" won't be mapped to RAM because it is too sparse
140 
INFO: [Synth 8-5545] ROM "check_stat" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
141 
INFO: [Synth 8-5544] ROM "sys_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
142 
WARNING: [Synth 8-6014] Unused sequential element startup_pause_cnt_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:145]
143 
INFO: [Synth 8-5545] ROM "startup_pause_complete" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
144 
INFO: [Synth 8-5546] ROM "key_set_complete" won't be mapped to RAM because it is too sparse
145 
INFO: [Synth 8-5544] ROM "key_set_complete" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
146 
INFO: [Synth 8-5546] ROM "plain_text_set_in_progress" won't be mapped to RAM because it is too sparse
147 
INFO: [Synth 8-5546] ROM "data_counter" won't be mapped to RAM because it is too sparse
148 
INFO: [Synth 8-5544] ROM "cipher_data" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
149 
INFO: [Synth 8-5546] ROM "get_stat" won't be mapped to RAM because it is too sparse
150 
INFO: [Synth 8-5545] ROM "check_stat" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
151 
INFO: [Synth 8-5544] ROM "sys_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
152 
INFO: [Synth 8-5544] ROM "addr" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
153 
INFO: [Synth 8-5544] ROM "axi_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
154 
INFO: [Synth 8-5544] ROM "axi_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
155 
INFO: [Synth 8-5544] ROM "axi_next_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
156 
---------------------------------------------------------------------------------------------------
157 
                   State |                     New Encoding |                Previous Encoding
158 
---------------------------------------------------------------------------------------------------
159 
                SYS_IDLE |                              000 | 00000000000000000000000000000000
160 
      INIT_UART_CTRL_REG |                              001 | 00000000000000000000000000000001
161 
        RD_UART_STAT_REG |                              010 | 00000000000000000000000000000010
162 
              RD_RX_FIFO |                              011 | 00000000000000000000000000000011
163 
              WR_TX_FIFO |                              100 | 00000000000000000000000000000100
164 
---------------------------------------------------------------------------------------------------
165 
INFO: [Synth 8-3354] encoded FSM with state register 'sys_state_reg' using encoding 'sequential' in module 'system_manager'
166 
---------------------------------------------------------------------------------
167 
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 1735.738 ; gain = 543.590 ; free physical = 1072 ; free virtual = 6204
168 
---------------------------------------------------------------------------------
169 
 
170 
Report RTL Partitions:
171 
+------+--------------------------+------------+----------+
172 
|      |RTL Partition             |Replication |Instances |
173 
+------+--------------------------+------------+----------+
174 
|1     |aes128_enc__GB0           |           1|     32784|
175 
|2     |aes128_enc__GB1           |           1|      6120|
176 
|3     |aes128_enc__GB2           |           1|      4699|
177 
|4     |aes128_enc__GB3           |           1|     10352|
178 
|5     |aes128_enc__GB4           |           1|     11267|
179 
|6     |aes128_enc__GB5           |           1|     20400|
180 
|7     |aes128_ecb_fpga_wrap__GC0 |           1|     21176|
181 
+------+--------------------------+------------+----------+
182 
---------------------------------------------------------------------------------
183 
Start RTL Component Statistics
184 
---------------------------------------------------------------------------------
185 
Detailed RTL Component Info :
186 
+---Adders :
187 
           2 Input      4 Bit       Adders := 2
188 
           2 Input      2 Bit       Adders := 1
189 
+---XORs :
190 
           2 Input    128 Bit         XORs := 1
191 
           4 Input      8 Bit         XORs := 8
192 
           2 Input      8 Bit         XORs := 86
193 
           5 Input      8 Bit         XORs := 16
194 
           6 Input      8 Bit         XORs := 8
195 
           3 Input      8 Bit         XORs := 2
196 
+---Registers :
197 
                      128 Bit    Registers := 4
198 
                       32 Bit    Registers := 1
199 
                        8 Bit    Registers := 34
200 
                        4 Bit    Registers := 6
201 
                        2 Bit    Registers := 1
202 
                        1 Bit    Registers := 19
203 
+---Muxes :
204 
           2 Input    128 Bit        Muxes := 15
205 
           4 Input    128 Bit        Muxes := 1
206 
           3 Input    128 Bit        Muxes := 1
207 
           5 Input    128 Bit        Muxes := 5
208 
           2 Input     32 Bit        Muxes := 4
209 
           6 Input     32 Bit        Muxes := 2
210 
           2 Input      8 Bit        Muxes := 85
211 
           6 Input      8 Bit        Muxes := 3
212 
           5 Input      8 Bit        Muxes := 2
213 
           2 Input      4 Bit        Muxes := 10
214 
           5 Input      4 Bit        Muxes := 2
215 
           6 Input      4 Bit        Muxes := 3
216 
           2 Input      3 Bit        Muxes := 1
217 
           7 Input      3 Bit        Muxes := 1
218 
           2 Input      1 Bit        Muxes := 30
219 
           6 Input      1 Bit        Muxes := 11
220 
           4 Input      1 Bit        Muxes := 3
221 
           5 Input      1 Bit        Muxes := 24
222 
           3 Input      1 Bit        Muxes := 1
223 
---------------------------------------------------------------------------------
224 
Finished RTL Component Statistics
225 
---------------------------------------------------------------------------------
226 
---------------------------------------------------------------------------------
227 
Start RTL Hierarchical Component Statistics
228 
---------------------------------------------------------------------------------
229 
Hierarchical RTL Component report
230 
Module aes128_ecb_fpga_wrap
231 
Detailed RTL Component Info :
232 
+---Adders :
233 
           2 Input      2 Bit       Adders := 1
234 
+---Registers :
235 
                        2 Bit    Registers := 1
236 
Module aes128_enc
237 
Detailed RTL Component Info :
238 
+---Adders :
239 
           2 Input      4 Bit       Adders := 1
240 
+---XORs :
241 
           2 Input    128 Bit         XORs := 1
242 
           4 Input      8 Bit         XORs := 8
243 
           2 Input      8 Bit         XORs := 86
244 
           5 Input      8 Bit         XORs := 16
245 
           6 Input      8 Bit         XORs := 8
246 
           3 Input      8 Bit         XORs := 2
247 
+---Registers :
248 
                      128 Bit    Registers := 1
249 
                        8 Bit    Registers := 32
250 
                        4 Bit    Registers := 1
251 
                        1 Bit    Registers := 2
252 
+---Muxes :
253 
           2 Input    128 Bit        Muxes := 3
254 
           2 Input      8 Bit        Muxes := 80
255 
           2 Input      4 Bit        Muxes := 3
256 
           2 Input      1 Bit        Muxes := 3
257 
Module system_manager
258 
Detailed RTL Component Info :
259 
+---Adders :
260 
           2 Input      4 Bit       Adders := 1
261 
+---Registers :
262 
                      128 Bit    Registers := 3
263 
                       32 Bit    Registers := 1
264 
                        8 Bit    Registers := 2
265 
                        4 Bit    Registers := 5
266 
                        1 Bit    Registers := 17
267 
+---Muxes :
268 
           2 Input    128 Bit        Muxes := 12
269 
           4 Input    128 Bit        Muxes := 1
270 
           3 Input    128 Bit        Muxes := 1
271 
           5 Input    128 Bit        Muxes := 5
272 
           2 Input     32 Bit        Muxes := 4
273 
           6 Input     32 Bit        Muxes := 2
274 
           2 Input      8 Bit        Muxes := 5
275 
           6 Input      8 Bit        Muxes := 3
276 
           5 Input      8 Bit        Muxes := 2
277 
           2 Input      4 Bit        Muxes := 7
278 
           5 Input      4 Bit        Muxes := 2
279 
           6 Input      4 Bit        Muxes := 3
280 
           2 Input      3 Bit        Muxes := 1
281 
           7 Input      3 Bit        Muxes := 1
282 
           2 Input      1 Bit        Muxes := 27
283 
           6 Input      1 Bit        Muxes := 11
284 
           4 Input      1 Bit        Muxes := 3
285 
           5 Input      1 Bit        Muxes := 24
286 
           3 Input      1 Bit        Muxes := 1
287 
---------------------------------------------------------------------------------
288 
Finished RTL Hierarchical Component Statistics
289 
---------------------------------------------------------------------------------
290 
---------------------------------------------------------------------------------
291 
Start Part Resource Summary
292 
---------------------------------------------------------------------------------
293 
Part Resources:
294 
DSPs: 840 (col length:140)
295 
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
296 
---------------------------------------------------------------------------------
297 
Finished Part Resource Summary
298 
---------------------------------------------------------------------------------
299 
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 4 processes.
300 
---------------------------------------------------------------------------------
301 
Start Cross Boundary and Area Optimization
302 
---------------------------------------------------------------------------------
303 
INFO: [Synth 8-5545] ROM "startup_pause_complete" won't be mapped to RAM because address size (32) is larger than maximum supported(25)
304 
WARNING: [Synth 8-6014] Unused sequential element startup_pause_cnt_reg was removed.  [/home/user/aes128/src/wrap/system_manager.sv:145]
305 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[31]
306 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[30]
307 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[29]
308 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[28]
309 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[27]
310 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[26]
311 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[25]
312 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[24]
313 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[23]
314 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[22]
315 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[21]
316 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[20]
317 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[19]
318 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[18]
319 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[17]
320 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[16]
321 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[15]
322 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[14]
323 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[13]
324 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[12]
325 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[11]
326 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[10]
327 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[9]
328 
WARNING: [Synth 8-3331] design system_manager has unconnected port m_axi\.rdata[8]
329 
INFO: [Synth 8-3886] merging instance 'sys_mngr/addr_reg_reg[0]' (FDCE) to 'sys_mngr/addr_reg_reg[1]'
330 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sys_mngr/addr_reg_reg[1] )
331 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[19]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
332 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[18]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
333 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[17]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
334 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[23]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
335 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[22]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
336 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[21]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
337 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[20]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
338 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[29]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
339 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[28]' (FDCPE) to 'sys_mngr/axi_state_reg[31]'
340 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[31]' (FDCPE) to 'sys_mngr/axi_state_reg[30]'
341 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[30]' (FDCPE) to 'sys_mngr/axi_state_reg[27]'
342 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[25]' (FDCPE) to 'sys_mngr/axi_state_reg[27]'
343 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[24]' (FDCPE) to 'sys_mngr/axi_state_reg[27]'
344 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[27]' (FDCPE) to 'sys_mngr/axi_state_reg[26]'
345 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[26]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
346 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[5]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
347 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[3]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
348 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[4]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
349 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[9]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
350 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[8]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
351 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[7]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
352 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[6]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
353 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[14]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
354 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[13]' (FDCPE) to 'sys_mngr/axi_state_reg[16]'
355 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[16]' (FDCPE) to 'sys_mngr/axi_state_reg[15]'
356 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[15]' (FDCPE) to 'sys_mngr/axi_state_reg[12]'
357 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[12]' (FDCPE) to 'sys_mngr/axi_state_reg[11]'
358 
INFO: [Synth 8-3886] merging instance 'sys_mngr/axi_state_reg[11]' (FDCPE) to 'sys_mngr/axi_state_reg[10]'
359 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wstrb_reg[0]' (FDCE) to 'sys_mngr/m_axi\.wstrb_reg[3]'
360 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wstrb_reg[1]' (FDCE) to 'sys_mngr/m_axi\.wstrb_reg[3]'
361 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wstrb_reg[2]' (FDCE) to 'sys_mngr/m_axi\.wstrb_reg[3]'
362 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[8]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[9]'
363 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[9]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[10]'
364 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[10]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[11]'
365 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[11]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[12]'
366 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[12]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[13]'
367 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[13]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[14]'
368 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[14]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[15]'
369 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[15]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[16]'
370 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[16]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[17]'
371 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[17]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[18]'
372 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[18]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[19]'
373 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[19]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[20]'
374 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[20]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[21]'
375 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[21]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[22]'
376 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[22]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[23]'
377 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[23]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[24]'
378 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[24]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[25]'
379 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[25]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[26]'
380 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[26]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[27]'
381 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[27]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[28]'
382 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[28]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[29]'
383 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[29]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[30]'
384 
INFO: [Synth 8-3886] merging instance 'sys_mngr/m_axi\.wdata_reg[30]' (FDC) to 'sys_mngr/m_axi\.wdata_reg[31]'
385 
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\sys_mngr/m_axi\.wdata_reg[31] )
386 
---------------------------------------------------------------------------------
387 
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:01:32 . Memory (MB): peak = 1739.660 ; gain = 547.512 ; free physical = 300 ; free virtual = 4155
388 
---------------------------------------------------------------------------------
389 
 
390 
Report RTL Partitions:
391 
+------+--------------------------+------------+----------+
392 
|      |RTL Partition             |Replication |Instances |
393 
+------+--------------------------+------------+----------+
394 
|1     |aes128_enc__GB0           |           1|      8259|
395 
|2     |aes128_enc__GB1           |           1|      1218|
396 
|3     |aes128_enc__GB2           |           1|      1352|
397 
|4     |aes128_enc__GB3           |           1|      2182|
398 
|5     |aes128_enc__GB4           |           1|      2828|
399 
|6     |aes128_enc__GB5           |           1|      4060|
400 
|7     |aes128_ecb_fpga_wrap__GC0 |           1|      1924|
401 
+------+--------------------------+------------+----------+
402 
---------------------------------------------------------------------------------
403 
Start Applying XDC Timing Constraints
404 
---------------------------------------------------------------------------------
405 
INFO: [Synth 8-5578] Moved timing constraint from pin 'clkgen/clk_out1' to pin 'clkgen/bbstub_clk_out1/O'
406 
INFO: [Synth 8-5783] Moving clock source from hierarchical pin 'clkgen/clk_in1_p' to 'CLK_IN_P'
407 
INFO: [Synth 8-5819] Moved 2 constraints on hierarchical pins to their respective driving/loading pins
408 
---------------------------------------------------------------------------------
409 
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:45 ; elapsed = 00:01:40 . Memory (MB): peak = 1843.027 ; gain = 650.879 ; free physical = 170 ; free virtual = 4025
410 
---------------------------------------------------------------------------------
411 
---------------------------------------------------------------------------------
412 
Start Timing Optimization
413 
---------------------------------------------------------------------------------
414 
---------------------------------------------------------------------------------
415 
Finished Timing Optimization : Time (s): cpu = 00:01:13 ; elapsed = 00:02:08 . Memory (MB): peak = 2199.262 ; gain = 1007.113 ; free physical = 567 ; free virtual = 4111
416 
---------------------------------------------------------------------------------
417 
 
418 
Report RTL Partitions:
419 
+------+-------------------------+------------+----------+
420 
|      |RTL Partition            |Replication |Instances |
421 
+------+-------------------------+------------+----------+
422 
|1     |aes128_ecb_fpga_wrap_GT0 |           1|     21778|
423 
+------+-------------------------+------------+----------+
424 
---------------------------------------------------------------------------------
425 
Start Technology Mapping
426 
---------------------------------------------------------------------------------
427 
INFO: [Synth 8-3886] merging instance 'i_0/sys_mngr/cur_stat_reg_reg[0]' (FDCE) to 'i_0/sys_mngr/rx_fifo_valid_data_reg_reg'
428 
INFO: [Synth 8-3886] merging instance 'i_0/sys_mngr/m_axi\.wstrb_reg[3]' (FDCE) to 'i_0/sys_mngr/m_axi\.awvalid_reg'
429 
---------------------------------------------------------------------------------
430 
Finished Technology Mapping : Time (s): cpu = 00:01:13 ; elapsed = 00:02:20 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
431 
---------------------------------------------------------------------------------
432 
 
433 
Report RTL Partitions:
434 
+------+-------------------------+------------+----------+
435 
|      |RTL Partition            |Replication |Instances |
436 
+------+-------------------------+------------+----------+
437 
|1     |aes128_ecb_fpga_wrap_GT0 |           1|      4826|
438 
+------+-------------------------+------------+----------+
439 
---------------------------------------------------------------------------------
440 
Start IO Insertion
441 
---------------------------------------------------------------------------------
442 
---------------------------------------------------------------------------------
443 
Start Flattening Before IO Insertion
444 
---------------------------------------------------------------------------------
445 
---------------------------------------------------------------------------------
446 
Finished Flattening Before IO Insertion
447 
---------------------------------------------------------------------------------
448 
---------------------------------------------------------------------------------
449 
Start Final Netlist Cleanup
450 
---------------------------------------------------------------------------------
451 
---------------------------------------------------------------------------------
452 
Finished Final Netlist Cleanup
453 
---------------------------------------------------------------------------------
454 
---------------------------------------------------------------------------------
455 
Finished IO Insertion : Time (s): cpu = 00:01:14 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
456 
---------------------------------------------------------------------------------
457 
 
458 
Report Check Netlist:
459 
+------+------------------+-------+---------+-------+------------------+
460 
|      |Item              |Errors |Warnings |Status |Description       |
461 
+------+------------------+-------+---------+-------+------------------+
462 
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
463 
+------+------------------+-------+---------+-------+------------------+
464 
---------------------------------------------------------------------------------
465 
Start Renaming Generated Instances
466 
---------------------------------------------------------------------------------
467 
---------------------------------------------------------------------------------
468 
Finished Renaming Generated Instances : Time (s): cpu = 00:01:14 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
469 
---------------------------------------------------------------------------------
470 
 
471 
Report RTL Partitions:
472 
+-+--------------+------------+----------+
473 
| |RTL Partition |Replication |Instances |
474 
+-+--------------+------------+----------+
475 
+-+--------------+------------+----------+
476 
---------------------------------------------------------------------------------
477 
Start Rebuilding User Hierarchy
478 
---------------------------------------------------------------------------------
479 
---------------------------------------------------------------------------------
480 
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
481 
---------------------------------------------------------------------------------
482 
---------------------------------------------------------------------------------
483 
Start Renaming Generated Ports
484 
---------------------------------------------------------------------------------
485 
---------------------------------------------------------------------------------
486 
Finished Renaming Generated Ports : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 436 ; free virtual = 3982
487 
---------------------------------------------------------------------------------
488 
---------------------------------------------------------------------------------
489 
Start Handling Custom Attributes
490 
---------------------------------------------------------------------------------
491 
---------------------------------------------------------------------------------
492 
Finished Handling Custom Attributes : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 435 ; free virtual = 3980
493 
---------------------------------------------------------------------------------
494 
---------------------------------------------------------------------------------
495 
Start Renaming Generated Nets
496 
---------------------------------------------------------------------------------
497 
---------------------------------------------------------------------------------
498 
Finished Renaming Generated Nets : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 435 ; free virtual = 3980
499 
---------------------------------------------------------------------------------
500 
---------------------------------------------------------------------------------
501 
Start Writing Synthesis Report
502 
---------------------------------------------------------------------------------
503 
 
504 
Report BlackBoxes:
505 
+------+--------------------+----------+
506 
|      |BlackBox name       |Instances |
507 
+------+--------------------+----------+
508 
|1     |clk_gen             |         1|
509 
|2     |axi_uartlite_module |         1|
510 
+------+--------------------+----------+
511 
 
512 
Report Cell Usage:
513 
+------+--------------------+------+
514 
|      |Cell                |Count |
515 
+------+--------------------+------+
516 
|1     |axi_uartlite_module |     1|
517 
|2     |clk_gen             |     1|
518 
|3     |CARRY4              |     8|
519 
|4     |LUT1                |     3|
520 
|5     |LUT2                |   435|
521 
|6     |LUT3                |   306|
522 
|7     |LUT4                |   154|
523 
|8     |LUT5                |   220|
524 
|9     |LUT6                |  1930|
525 
|10    |MUXF7               |   637|
526 
|11    |MUXF8               |   270|
527 
|12    |FDCE                |   868|
528 
|13    |FDPE                |     4|
529 
|14    |LDC                 |     4|
530 
|15    |IBUF                |     2|
531 
|16    |OBUF                |     5|
532 
+------+--------------------+------+
533 
 
534 
Report Instance Areas:
535 
+------+-----------+---------------+------+
536 
|      |Instance   |Module         |Cells |
537 
+------+-----------+---------------+------+
538 
|1     |top        |               |  4891|
539 
|2     |  enc      |aes128_enc     |  2095|
540 
|3     |  sys_mngr |system_manager |  2740|
541 
+------+-----------+---------------+------+
542 
---------------------------------------------------------------------------------
543 
Finished Writing Synthesis Report : Time (s): cpu = 00:01:15 ; elapsed = 00:02:21 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 435 ; free virtual = 3980
544 
---------------------------------------------------------------------------------
545 
Synthesis finished with 0 errors, 0 critical warnings and 27 warnings.
546 
Synthesis Optimization Runtime : Time (s): cpu = 00:01:06 ; elapsed = 00:02:07 . Memory (MB): peak = 2211.188 ; gain = 636.977 ; free physical = 2600 ; free virtual = 6146
547 
Synthesis Optimization Complete : Time (s): cpu = 00:01:15 ; elapsed = 00:02:26 . Memory (MB): peak = 2211.188 ; gain = 1019.039 ; free physical = 2603 ; free virtual = 6146
548 
INFO: [Project 1-571] Translating synthesized netlist
549 
INFO: [Netlist 29-17] Analyzing 921 Unisim elements for replacement
550 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
551 
INFO: [Project 1-570] Preparing netlist for logic optimization
552 
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
553 
INFO: [Project 1-111] Unisim Transformation Summary:
554 
  A total of 4 instances were transformed.
555 
  LDC => LDCE: 4 instances
556 
 
557 
INFO: [Common 17-83] Releasing license: Synthesis
558 
120 Infos, 58 Warnings, 0 Critical Warnings and 0 Errors encountered.
559 
synth_design completed successfully
560 
synth_design: Time (s): cpu = 00:01:17 ; elapsed = 00:02:28 . Memory (MB): peak = 2223.273 ; gain = 1058.230 ; free physical = 2595 ; free virtual = 6139
561 
INFO: [Common 17-1381] The checkpoint '/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/aes128_ecb_fpga_wrap.dcp' has been generated.
562 
INFO: [runtcl-4] Executing : report_utilization -file aes128_ecb_fpga_wrap_utilization_synth.rpt -pb aes128_ecb_fpga_wrap_utilization_synth.pb
563 
report_utilization: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2247.285 ; gain = 0.000 ; free physical = 2593 ; free virtual = 6139
564 
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 13:54:39 2020...

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.