Subversion Repositories aes-128-ecb-encoder

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-- DO NOT MODIFY THIS FILE.

-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0

-- IP Revision: 19

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

COMPONENT axi_uartlite_module

  PORT (

    s_axi_aclk : IN STD_LOGIC;

    s_axi_aresetn : IN STD_LOGIC;

    interrupt : OUT STD_LOGIC;

    s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

    s_axi_awvalid : IN STD_LOGIC;

    s_axi_awready : OUT STD_LOGIC;

    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

    s_axi_wvalid : IN STD_LOGIC;

    s_axi_wready : OUT STD_LOGIC;

    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

    s_axi_bvalid : OUT STD_LOGIC;

    s_axi_bready : IN STD_LOGIC;

    s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

    s_axi_arvalid : IN STD_LOGIC;

    s_axi_arready : OUT STD_LOGIC;

    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

    s_axi_rvalid : OUT STD_LOGIC;

    s_axi_rready : IN STD_LOGIC;

    rx : IN STD_LOGIC;

    tx : OUT STD_LOGIC

  );

END COMPONENT;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : axi_uartlite_module

  PORT MAP (

    s_axi_aclk => s_axi_aclk,

    s_axi_aresetn => s_axi_aresetn,

    interrupt => interrupt,

    s_axi_awaddr => s_axi_awaddr,

    s_axi_awvalid => s_axi_awvalid,

    s_axi_awready => s_axi_awready,

    s_axi_wdata => s_axi_wdata,

    s_axi_wstrb => s_axi_wstrb,

    s_axi_wvalid => s_axi_wvalid,

    s_axi_wready => s_axi_wready,

    s_axi_bresp => s_axi_bresp,

    s_axi_bvalid => s_axi_bvalid,

    s_axi_bready => s_axi_bready,

    s_axi_araddr => s_axi_araddr,

    s_axi_arvalid => s_axi_arvalid,

    s_axi_arready => s_axi_arready,

    s_axi_rdata => s_axi_rdata,

    s_axi_rresp => s_axi_rresp,

    s_axi_rvalid => s_axi_rvalid,

    s_axi_rready => s_axi_rready,

    rx => rx,

    tx => tx

  );

-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file axi_uartlite_module.vhd when simulating

-- the core, axi_uartlite_module. When compiling the wrapper file, be sure to

-- reference the VHDL simulation library.