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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [axi_uartlite_module/] [axi_uartlite_module.xdc] - Blame information for rev 2

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# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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#
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# This file contains confidential and proprietary information
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# international copyright and other intellectual property
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#
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# DISCLAIMER
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# This disclaimer is not a license and does not grant any
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# otherwise provided in a valid license issued to you by
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# Xilinx, and to the maximum extent permitted by applicable
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# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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# (2) Xilinx shall not be liable (whether in contract or tort,
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set_false_path -to [get_pins -hier *cdc_to*/D]
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