1 |
2 |
vv_gulyaev |
2017.4:
|
2 |
|
|
* Version 2.0 (Rev. 19)
|
3 |
|
|
* Revision change in one or more subcores
|
4 |
|
|
|
5 |
|
|
2017.3:
|
6 |
|
|
* Version 2.0 (Rev. 18)
|
7 |
|
|
* General: Updated example design subcore version. No Functional changes
|
8 |
|
|
* Revision change in one or more subcores
|
9 |
|
|
|
10 |
|
|
2017.2:
|
11 |
|
|
* Version 2.0 (Rev. 17)
|
12 |
|
|
* Revision change in one or more subcores
|
13 |
|
|
|
14 |
|
|
2017.1:
|
15 |
|
|
* Version 2.0 (Rev. 16)
|
16 |
|
|
* General: Updated example design subcore version. No Functional changes
|
17 |
|
|
* Revision change in one or more subcores
|
18 |
|
|
|
19 |
|
|
2016.4:
|
20 |
|
|
* Version 2.0 (Rev. 15)
|
21 |
|
|
* Revision change in one or more subcores
|
22 |
|
|
|
23 |
|
|
2016.3:
|
24 |
|
|
* Version 2.0 (Rev. 14)
|
25 |
|
|
* Bug Fix: GUI related updates. GUI allows setting of only valid baud rate values.
|
26 |
|
|
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
|
27 |
|
|
* Revision change in one or more subcores
|
28 |
|
|
|
29 |
|
|
2016.2:
|
30 |
|
|
* Version 2.0 (Rev. 13)
|
31 |
|
|
* Revision change in one or more subcores
|
32 |
|
|
|
33 |
|
|
2016.1:
|
34 |
|
|
* Version 2.0 (Rev. 12)
|
35 |
|
|
* Updated example design subcore version.No functional changes
|
36 |
|
|
* Revision change in one or more subcores
|
37 |
|
|
|
38 |
|
|
2015.4.2:
|
39 |
|
|
* Version 2.0 (Rev. 11)
|
40 |
|
|
* No changes
|
41 |
|
|
|
42 |
|
|
2015.4.1:
|
43 |
|
|
* Version 2.0 (Rev. 11)
|
44 |
|
|
* No changes
|
45 |
|
|
|
46 |
|
|
2015.4:
|
47 |
|
|
* Version 2.0 (Rev. 11)
|
48 |
|
|
* Revision change in one or more subcores
|
49 |
|
|
|
50 |
|
|
2015.3:
|
51 |
|
|
* Version 2.0 (Rev. 10)
|
52 |
|
|
* Minor updates to example design. No functional changes.
|
53 |
|
|
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
|
54 |
|
|
* Revision change in one or more subcores
|
55 |
|
|
|
56 |
|
|
2015.2.1:
|
57 |
|
|
* Version 2.0 (Rev. 9)
|
58 |
|
|
* No changes
|
59 |
|
|
|
60 |
|
|
2015.2:
|
61 |
|
|
* Version 2.0 (Rev. 9)
|
62 |
|
|
* Minor updates to example design. No functional changes.
|
63 |
|
|
|
64 |
|
|
2015.1:
|
65 |
|
|
* Version 2.0 (Rev. 8)
|
66 |
|
|
* Supported devices and production status are now determined automatically, to simplify support for future devices
|
67 |
|
|
* Enhanced support for IP Integrator
|
68 |
|
|
|
69 |
|
|
2014.4.1:
|
70 |
|
|
* Version 2.0 (Rev. 7)
|
71 |
|
|
* No changes
|
72 |
|
|
|
73 |
|
|
2014.4:
|
74 |
|
|
* Version 2.0 (Rev. 7)
|
75 |
|
|
* Minor updates to example design. No functional changes.
|
76 |
|
|
|
77 |
|
|
2014.3:
|
78 |
|
|
* Version 2.0 (Rev. 6)
|
79 |
|
|
* axi uartlite is modified to use new sub-cores in place of proc_common. No functional changes.
|
80 |
|
|
* Updating core to use utils.tcl needed for board flow from common location
|
81 |
|
|
|
82 |
|
|
2014.2:
|
83 |
|
|
* Version 2.0 (Rev. 5)
|
84 |
|
|
* Example design XDC updated
|
85 |
|
|
* Minor GUI related updates, no functional changes
|
86 |
|
|
|
87 |
|
|
2014.1:
|
88 |
|
|
* Version 2.0 (Rev. 4)
|
89 |
|
|
* Internal device family name change, no functional changes
|
90 |
|
|
* Virtex UltraScale Pre-Production support.
|
91 |
|
|
|
92 |
|
|
2013.4:
|
93 |
|
|
* Version 2.0 (Rev. 3)
|
94 |
|
|
* Kintex UltraScale Pre-Production support
|
95 |
|
|
|
96 |
|
|
2013.3:
|
97 |
|
|
* Version 2.0 (Rev. 2)
|
98 |
|
|
* Added example design and demonstration testbench
|
99 |
|
|
* Reduced warnings in synthesis and simulation
|
100 |
|
|
* Enhanced support for IP Integrator
|
101 |
|
|
* Added support for Cadence IES and Synopsys VCS simulators
|
102 |
|
|
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
|
103 |
|
|
|
104 |
|
|
2013.2:
|
105 |
|
|
* Version 2.0 (Rev. 1)
|
106 |
|
|
* Enable support for future devices
|
107 |
|
|
|
108 |
|
|
2013.1:
|
109 |
|
|
* Version 2.0
|
110 |
|
|
* Native Vivado Release
|
111 |
|
|
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
|
112 |
|
|
|
113 |
|
|
(c) Copyright 2012 - 2017 Xilinx, Inc. All rights reserved.
|
114 |
|
|
|
115 |
|
|
This file contains confidential and proprietary information
|
116 |
|
|
of Xilinx, Inc. and is protected under U.S. and
|
117 |
|
|
international copyright and other intellectual property
|
118 |
|
|
laws.
|
119 |
|
|
|
120 |
|
|
DISCLAIMER
|
121 |
|
|
This disclaimer is not a license and does not grant any
|
122 |
|
|
rights to the materials distributed herewith. Except as
|
123 |
|
|
otherwise provided in a valid license issued to you by
|
124 |
|
|
Xilinx, and to the maximum extent permitted by applicable
|
125 |
|
|
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
126 |
|
|
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
127 |
|
|
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
128 |
|
|
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
129 |
|
|
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
130 |
|
|
(2) Xilinx shall not be liable (whether in contract or tort,
|
131 |
|
|
including negligence, or under any other theory of
|
132 |
|
|
liability) for any loss or damage of any kind or nature
|
133 |
|
|
related to, arising under or in connection with these
|
134 |
|
|
materials, including for any direct, or any indirect,
|
135 |
|
|
special, incidental, or consequential loss or damage
|
136 |
|
|
(including loss of data, profits, goodwill, or any type of
|
137 |
|
|
loss or damage suffered as a result of any action brought
|
138 |
|
|
by a third party) even if such damage or loss was
|
139 |
|
|
reasonably foreseeable or Xilinx had been advised of the
|
140 |
|
|
possibility of the same.
|
141 |
|
|
|
142 |
|
|
CRITICAL APPLICATIONS
|
143 |
|
|
Xilinx products are not designed or intended to be fail-
|
144 |
|
|
safe, or for use in any application requiring fail-safe
|
145 |
|
|
performance, such as life-support or safety devices or
|
146 |
|
|
systems, Class III medical devices, nuclear facilities,
|
147 |
|
|
applications related to the deployment of airbags, or any
|
148 |
|
|
other applications that could lead to death, personal
|
149 |
|
|
injury, or severe property or environmental damage
|
150 |
|
|
(individually and collectively, "Critical
|
151 |
|
|
Applications"). Customer assumes the sole risk and
|
152 |
|
|
liability of any use of Xilinx products in Critical
|
153 |
|
|
Applications, subject only to applicable laws and
|
154 |
|
|
regulations governing limitations on product liability.
|
155 |
|
|
|
156 |
|
|
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
157 |
|
|
PART OF THIS FILE AT ALL TIMES.
|