1 |
2 |
vv_gulyaev |
-- cntr_incr_decr_addn_f - entity / architecture pair
|
2 |
|
|
-------------------------------------------------------------------------------
|
3 |
|
|
--
|
4 |
|
|
-- *************************************************************************
|
5 |
|
|
-- ** **
|
6 |
|
|
-- ** DISCLAIMER OF LIABILITY **
|
7 |
|
|
-- ** **
|
8 |
|
|
-- ** This text/file contains proprietary, confidential **
|
9 |
|
|
-- ** information of Xilinx, Inc., is distributed under **
|
10 |
|
|
-- ** license from Xilinx, Inc., and may be used, copied **
|
11 |
|
|
-- ** and/or disclosed only pursuant to the terms of a valid **
|
12 |
|
|
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
|
13 |
|
|
-- ** grants you a license to use this text/file solely for **
|
14 |
|
|
-- ** design, simulation, implementation and creation of **
|
15 |
|
|
-- ** design files limited to Xilinx devices or technologies. **
|
16 |
|
|
-- ** Use with non-Xilinx devices or technologies is expressly **
|
17 |
|
|
-- ** prohibited and immediately terminates your license unless **
|
18 |
|
|
-- ** covered by a separate agreement. **
|
19 |
|
|
-- ** **
|
20 |
|
|
-- ** Xilinx is providing this design, code, or information **
|
21 |
|
|
-- ** "as-is" solely for use in developing programs and **
|
22 |
|
|
-- ** solutions for Xilinx devices, with no obligation on the **
|
23 |
|
|
-- ** part of Xilinx to provide support. By providing this design, **
|
24 |
|
|
-- ** code, or information as one possible implementation of **
|
25 |
|
|
-- ** this feature, application or standard, Xilinx is making no **
|
26 |
|
|
-- ** representation that this implementation is free from any **
|
27 |
|
|
-- ** claims of infringement. You are responsible for obtaining **
|
28 |
|
|
-- ** any rights you may require for your implementation. **
|
29 |
|
|
-- ** Xilinx expressly disclaims any warranty whatsoever with **
|
30 |
|
|
-- ** respect to the adequacy of the implementation, including **
|
31 |
|
|
-- ** but not limited to any warranties or representations that this **
|
32 |
|
|
-- ** implementation is free from claims of infringement, implied **
|
33 |
|
|
-- ** warranties of merchantability or fitness for a particular **
|
34 |
|
|
-- ** purpose. **
|
35 |
|
|
-- ** **
|
36 |
|
|
-- ** Xilinx products are not intended for use in life support **
|
37 |
|
|
-- ** appliances, devices, or systems. Use in such applications is **
|
38 |
|
|
-- ** expressly prohibited. **
|
39 |
|
|
-- ** **
|
40 |
|
|
-- ** Any modifications that are made to the Source Code are **
|
41 |
|
|
-- ** done at the user’s sole risk and will be unsupported. **
|
42 |
|
|
-- ** The Xilinx Support Hotline does not have access to source **
|
43 |
|
|
-- ** code and therefore cannot answer specific questions related **
|
44 |
|
|
-- ** to source HDL. The Xilinx Hotline support of original source **
|
45 |
|
|
-- ** code IP shall only address issues and questions related **
|
46 |
|
|
-- ** to the standard Netlist version of the core (and thus **
|
47 |
|
|
-- ** indirectly, the original core source). **
|
48 |
|
|
-- ** **
|
49 |
|
|
-- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. **
|
50 |
|
|
-- ** **
|
51 |
|
|
-- ** This copyright and support notice must be retained as part **
|
52 |
|
|
-- ** of this text at all times. **
|
53 |
|
|
-- ** **
|
54 |
|
|
-- *************************************************************************
|
55 |
|
|
--
|
56 |
|
|
-------------------------------------------------------------------------------
|
57 |
|
|
-- Filename: cntr_incr_decr_addn_f.vhd
|
58 |
|
|
--
|
59 |
|
|
-- Description: This counter can increment, decrement or skip ahead
|
60 |
|
|
-- by an arbitrary amount.
|
61 |
|
|
--
|
62 |
|
|
-- If Reset is active, the value Cnt synchronously resets
|
63 |
|
|
-- to all ones. (This reset value, different than the
|
64 |
|
|
-- customary reset value of zero, caters to the original
|
65 |
|
|
-- application of cntr_incr_decr_addn_f as the address
|
66 |
|
|
-- counter for srl_fifo_rbu_f.)
|
67 |
|
|
--
|
68 |
|
|
-- Otherwise, on each Clk, one is added to Cnt if Incr is
|
69 |
|
|
-- asserted and one is subtracted if Decr is asserted. (If
|
70 |
|
|
-- both are asserted, then there is no change to Cnt.)
|
71 |
|
|
--
|
72 |
|
|
-- If Decr is not asserted, then the input value,
|
73 |
|
|
-- Nm_to_add, is added. (Simultaneous assertion of Incr
|
74 |
|
|
-- would add one more.) If Decr is asserted, then
|
75 |
|
|
-- N_to_add, is ignored, i.e., it is possible to decrement
|
76 |
|
|
-- by one or add N, but not both, and Decr overrides.
|
77 |
|
|
--
|
78 |
|
|
-- The value that Cnt will take on at the next clock
|
79 |
|
|
-- is available as Cnt_p1.
|
80 |
|
|
--
|
81 |
|
|
--
|
82 |
|
|
-- VHDL-Standard: VHDL'93
|
83 |
|
|
-------------------------------------------------------------------------------
|
84 |
|
|
-- Structure:
|
85 |
|
|
-- cntr_incr_decr_addn_f.vhd
|
86 |
|
|
--
|
87 |
|
|
-------------------------------------------------------------------------------
|
88 |
|
|
--
|
89 |
|
|
-- History:
|
90 |
|
|
-- FLO 12/30/05 First Version.
|
91 |
|
|
--
|
92 |
|
|
-- ~~~~~~
|
93 |
|
|
-------------------------------------------------------------------------------
|
94 |
|
|
-- Naming Conventions:
|
95 |
|
|
-- active low signals: "*_n"
|
96 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
97 |
|
|
-- reset signals: "rst", "rst_n"
|
98 |
|
|
-- generics: "C_*"
|
99 |
|
|
-- user defined types: "*_TYPE"
|
100 |
|
|
-- state machine next state: "*_ns"
|
101 |
|
|
-- state machine current state: "*_cs"
|
102 |
|
|
-- combinatorial signals: "*_com"
|
103 |
|
|
-- pipelined or register delay signals: "*_d#"
|
104 |
|
|
-- predecessor value by # clks: "*_p#"
|
105 |
|
|
-- counter signals: "*cnt*"
|
106 |
|
|
-- clock enable signals: "*_ce"
|
107 |
|
|
-- internal version of output port "*_i"
|
108 |
|
|
-- device pins: "*_pin"
|
109 |
|
|
-- ports: - Names begin with Uppercase
|
110 |
|
|
-- processes: "*_PROCESS"
|
111 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
112 |
|
|
-------------------------------------------------------------------------------
|
113 |
|
|
|
114 |
|
|
|
115 |
|
|
library ieee;
|
116 |
|
|
use ieee.std_logic_1164.all;
|
117 |
|
|
--
|
118 |
|
|
entity cntr_incr_decr_addn_f is
|
119 |
|
|
generic (
|
120 |
|
|
C_SIZE : natural;
|
121 |
|
|
C_FAMILY : string := "nofamily"
|
122 |
|
|
);
|
123 |
|
|
port (
|
124 |
|
|
Clk : in std_logic;
|
125 |
|
|
Reset : in std_logic; -- Note: the counter resets to all ones!
|
126 |
|
|
Incr : in std_logic;
|
127 |
|
|
Decr : in std_logic;
|
128 |
|
|
N_to_add : in std_logic_vector(C_SIZE-1 downto 0);
|
129 |
|
|
Cnt : out std_logic_vector(C_SIZE-1 downto 0);
|
130 |
|
|
Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0)
|
131 |
|
|
);
|
132 |
|
|
end entity cntr_incr_decr_addn_f;
|
133 |
|
|
|
134 |
|
|
|
135 |
|
|
---(
|
136 |
|
|
library lib_srl_fifo_v1_0_2;
|
137 |
|
|
library ieee;
|
138 |
|
|
use ieee.numeric_std.UNSIGNED;
|
139 |
|
|
use ieee.numeric_std."+";
|
140 |
|
|
library unisim;
|
141 |
|
|
use unisim.all; -- Make unisim entities available for default binding.
|
142 |
|
|
--
|
143 |
|
|
architecture imp of cntr_incr_decr_addn_f is
|
144 |
|
|
|
145 |
|
|
|
146 |
|
|
-- constant COUNTER_PRIMS_AVAIL : boolean :=
|
147 |
|
|
-- supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS));
|
148 |
|
|
constant COUNTER_PRIMS_AVAIL : boolean := false;
|
149 |
|
|
|
150 |
|
|
|
151 |
|
|
signal cnt_i : std_logic_vector(Cnt'range);
|
152 |
|
|
signal cnt_i_p1 : std_logic_vector(Cnt'range);
|
153 |
|
|
|
154 |
|
|
----------------------------------------------------------------------------
|
155 |
|
|
-- Unisim components declared locally for maximum avoidance of default
|
156 |
|
|
-- binding and vcomponents version issues.
|
157 |
|
|
----------------------------------------------------------------------------
|
158 |
|
|
component MUXCY_L
|
159 |
|
|
port
|
160 |
|
|
(
|
161 |
|
|
LO : out std_ulogic;
|
162 |
|
|
CI : in std_ulogic;
|
163 |
|
|
DI : in std_ulogic;
|
164 |
|
|
S : in std_ulogic
|
165 |
|
|
);
|
166 |
|
|
end component;
|
167 |
|
|
|
168 |
|
|
component XORCY
|
169 |
|
|
port
|
170 |
|
|
(
|
171 |
|
|
O : out std_ulogic;
|
172 |
|
|
CI : in std_ulogic;
|
173 |
|
|
LI : in std_ulogic
|
174 |
|
|
);
|
175 |
|
|
end component;
|
176 |
|
|
|
177 |
|
|
component FDS
|
178 |
|
|
generic
|
179 |
|
|
(
|
180 |
|
|
INIT : bit := '1'
|
181 |
|
|
);
|
182 |
|
|
port
|
183 |
|
|
(
|
184 |
|
|
Q : out std_ulogic;
|
185 |
|
|
C : in std_ulogic;
|
186 |
|
|
D : in std_ulogic;
|
187 |
|
|
S : in std_ulogic
|
188 |
|
|
);
|
189 |
|
|
end component;
|
190 |
|
|
|
191 |
|
|
begin -- architecture imp
|
192 |
|
|
|
193 |
|
|
|
194 |
|
|
---(
|
195 |
|
|
INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate
|
196 |
|
|
--
|
197 |
|
|
CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr
|
198 |
|
|
) is
|
199 |
|
|
--
|
200 |
|
|
function qual_n_to_add(N_to_add : std_logic_vector;
|
201 |
|
|
Decr : std_logic
|
202 |
|
|
) return UNSIGNED is
|
203 |
|
|
variable r: UNSIGNED(N_to_add'range);
|
204 |
|
|
begin
|
205 |
|
|
for i in r'range loop
|
206 |
|
|
r(i) := N_to_add(i) or Decr;
|
207 |
|
|
end loop;
|
208 |
|
|
return r;
|
209 |
|
|
end;
|
210 |
|
|
--
|
211 |
|
|
function to_singleton_unsigned(s : std_logic) return unsigned is
|
212 |
|
|
variable r : unsigned(0 to 0) := (others => s);
|
213 |
|
|
begin
|
214 |
|
|
return r;
|
215 |
|
|
end;
|
216 |
|
|
--
|
217 |
|
|
begin
|
218 |
|
|
cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i)
|
219 |
|
|
+ qual_n_to_add(N_to_add, Decr)
|
220 |
|
|
+ to_singleton_unsigned(Incr)
|
221 |
|
|
);
|
222 |
|
|
end process;
|
223 |
|
|
--
|
224 |
|
|
CNT_I_PROC : process(Clk) is
|
225 |
|
|
begin
|
226 |
|
|
if Clk'event and Clk = '1' then
|
227 |
|
|
if Reset = '1' then
|
228 |
|
|
cnt_i <= (others => '1');
|
229 |
|
|
else
|
230 |
|
|
cnt_i <= cnt_i_p1;
|
231 |
|
|
end if;
|
232 |
|
|
end if;
|
233 |
|
|
end process;
|
234 |
|
|
--
|
235 |
|
|
end generate INFERRED_GEN;
|
236 |
|
|
---)
|
237 |
|
|
|
238 |
|
|
Cnt <= cnt_i;
|
239 |
|
|
Cnt_p1 <= cnt_i_p1;
|
240 |
|
|
|
241 |
|
|
end architecture imp;
|
242 |
|
|
---)
|
243 |
|
|
|
244 |
|
|
|
245 |
|
|
-- srl_fifo_rbu_f - entity / architecture pair
|
246 |
|
|
-------------------------------------------------------------------------------
|
247 |
|
|
--
|
248 |
|
|
-- *************************************************************************
|
249 |
|
|
-- ** **
|
250 |
|
|
-- ** DISCLAIMER OF LIABILITY **
|
251 |
|
|
-- ** **
|
252 |
|
|
-- ** This text/file contains proprietary, confidential **
|
253 |
|
|
-- ** information of Xilinx, Inc., is distributed under **
|
254 |
|
|
-- ** license from Xilinx, Inc., and may be used, copied **
|
255 |
|
|
-- ** and/or disclosed only pursuant to the terms of a valid **
|
256 |
|
|
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
|
257 |
|
|
-- ** grants you a license to use this text/file solely for **
|
258 |
|
|
-- ** design, simulation, implementation and creation of **
|
259 |
|
|
-- ** design files limited to Xilinx devices or technologies. **
|
260 |
|
|
-- ** Use with non-Xilinx devices or technologies is expressly **
|
261 |
|
|
-- ** prohibited and immediately terminates your license unless **
|
262 |
|
|
-- ** covered by a separate agreement. **
|
263 |
|
|
-- ** **
|
264 |
|
|
-- ** Xilinx is providing this design, code, or information **
|
265 |
|
|
-- ** "as-is" solely for use in developing programs and **
|
266 |
|
|
-- ** solutions for Xilinx devices, with no obligation on the **
|
267 |
|
|
-- ** part of Xilinx to provide support. By providing this design, **
|
268 |
|
|
-- ** code, or information as one possible implementation of **
|
269 |
|
|
-- ** this feature, application or standard, Xilinx is making no **
|
270 |
|
|
-- ** representation that this implementation is free from any **
|
271 |
|
|
-- ** claims of infringement. You are responsible for obtaining **
|
272 |
|
|
-- ** any rights you may require for your implementation. **
|
273 |
|
|
-- ** Xilinx expressly disclaims any warranty whatsoever with **
|
274 |
|
|
-- ** respect to the adequacy of the implementation, including **
|
275 |
|
|
-- ** but not limited to any warranties or representations that this **
|
276 |
|
|
-- ** implementation is free from claims of infringement, implied **
|
277 |
|
|
-- ** warranties of merchantability or fitness for a particular **
|
278 |
|
|
-- ** purpose. **
|
279 |
|
|
-- ** **
|
280 |
|
|
-- ** Xilinx products are not intended for use in life support **
|
281 |
|
|
-- ** appliances, devices, or systems. Use in such applications is **
|
282 |
|
|
-- ** expressly prohibited. **
|
283 |
|
|
-- ** **
|
284 |
|
|
-- ** Any modifications that are made to the Source Code are **
|
285 |
|
|
-- ** done at the user’s sole risk and will be unsupported. **
|
286 |
|
|
-- ** The Xilinx Support Hotline does not have access to source **
|
287 |
|
|
-- ** code and therefore cannot answer specific questions related **
|
288 |
|
|
-- ** to source HDL. The Xilinx Hotline support of original source **
|
289 |
|
|
-- ** code IP shall only address issues and questions related **
|
290 |
|
|
-- ** to the standard Netlist version of the core (and thus **
|
291 |
|
|
-- ** indirectly, the original core source). **
|
292 |
|
|
-- ** **
|
293 |
|
|
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
|
294 |
|
|
-- ** **
|
295 |
|
|
-- ** This copyright and support notice must be retained as part **
|
296 |
|
|
-- ** of this text at all times. **
|
297 |
|
|
-- ** **
|
298 |
|
|
-- *************************************************************************
|
299 |
|
|
--
|
300 |
|
|
-------------------------------------------------------------------------------
|
301 |
|
|
-- Filename: dynshreg_f.vhd
|
302 |
|
|
--
|
303 |
|
|
-- Description: This module implements a dynamic shift register with clock
|
304 |
|
|
-- enable. (Think, for example, of the function of the SRL16E.)
|
305 |
|
|
-- The width and depth of the shift register are selectable
|
306 |
|
|
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
|
307 |
|
|
-- allows the implementation to be tailored to the target
|
308 |
|
|
-- FPGA family. An inferred implementation is used if C_FAMILY
|
309 |
|
|
-- is "nofamily" (the default) or if synthesis will not produce
|
310 |
|
|
-- an optimal implementation. Otherwise, a structural
|
311 |
|
|
-- implementation will be generated.
|
312 |
|
|
--
|
313 |
|
|
-- There is no restriction on the values of C_WIDTH and
|
314 |
|
|
-- C_DEPTH and, in particular, the C_DEPTH does not have
|
315 |
|
|
-- to be a power of two.
|
316 |
|
|
--
|
317 |
|
|
--
|
318 |
|
|
-- VHDL-Standard: VHDL'93
|
319 |
|
|
-------------------------------------------------------------------------------
|
320 |
|
|
-- Structure:
|
321 |
|
|
--
|
322 |
|
|
-------------------------------------------------------------------------------
|
323 |
|
|
-- Author: Farrell Ostler
|
324 |
|
|
--
|
325 |
|
|
-- History:
|
326 |
|
|
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
|
327 |
|
|
--
|
328 |
|
|
-- ~~~~~~
|
329 |
|
|
-- FLO 06/07/15
|
330 |
|
|
-- ^^^^^^
|
331 |
|
|
-- -XST was observed in some cases to produce a suboptimal implementation when
|
332 |
|
|
-- the depth, C_DEPTH, is a power of two and less than the native depth
|
333 |
|
|
-- of the SRL. Now a structural implementation is used for these cases.
|
334 |
|
|
-- (The particular case where a problem was found was for C_DEPTH=4 and
|
335 |
|
|
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
|
336 |
|
|
-- made an implementation out of discrete FFs and LUTs.)
|
337 |
|
|
-- -Added Description.
|
338 |
|
|
-- ~~~~~~
|
339 |
|
|
-- FLO 07/12/12
|
340 |
|
|
-- ^^^^^^
|
341 |
|
|
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
|
342 |
|
|
-- ~~~~~~
|
343 |
|
|
--
|
344 |
|
|
-- DET 1/17/2008 v5_0
|
345 |
|
|
-- ~~~~~~
|
346 |
|
|
-- - Changed proc_common library version to v5_0
|
347 |
|
|
-- - Incorporated new disclaimer header
|
348 |
|
|
-- ^^^^^^
|
349 |
|
|
--
|
350 |
|
|
-------------------------------------------------------------------------------
|
351 |
|
|
-- Naming Conventions:
|
352 |
|
|
-- active low signals: "*_n"
|
353 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
354 |
|
|
-- reset signals: "rst", "rst_n"
|
355 |
|
|
-- generics: "C_*"
|
356 |
|
|
-- user defined types: "*_TYPE"
|
357 |
|
|
-- state machine next state: "*_ns"
|
358 |
|
|
-- state machine current state: "*_cs"
|
359 |
|
|
-- combinatorial signals: "*_com"
|
360 |
|
|
-- pipelined or register delay signals: "*_d#"
|
361 |
|
|
-- counter signals: "*cnt*"
|
362 |
|
|
-- clock enable signals: "*_ce"
|
363 |
|
|
-- internal version of output port "*_i"
|
364 |
|
|
-- device pins: "*_pin"
|
365 |
|
|
-- ports: - Names begin with Uppercase
|
366 |
|
|
-- processes: "*_PROCESS"
|
367 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
368 |
|
|
-------------------------------------------------------------------------------
|
369 |
|
|
-- predecessor value by # clks: "*_p#"
|
370 |
|
|
|
371 |
|
|
---(
|
372 |
|
|
library ieee;
|
373 |
|
|
use ieee.std_logic_1164.all;
|
374 |
|
|
use ieee.numeric_std.UNSIGNED;
|
375 |
|
|
use ieee.numeric_std.TO_INTEGER;
|
376 |
|
|
library lib_pkg_v1_0_2;
|
377 |
|
|
use lib_pkg_v1_0_2.lib_pkg.clog2;
|
378 |
|
|
|
379 |
|
|
entity dynshreg_f is
|
380 |
|
|
generic (
|
381 |
|
|
C_DEPTH : positive := 32;
|
382 |
|
|
C_DWIDTH : natural := 1;
|
383 |
|
|
C_FAMILY : string := "nofamily"
|
384 |
|
|
);
|
385 |
|
|
port (
|
386 |
|
|
Clk : in std_logic;
|
387 |
|
|
Clken : in std_logic;
|
388 |
|
|
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
|
389 |
|
|
Din : in std_logic_vector(0 to C_DWIDTH-1);
|
390 |
|
|
Dout : out std_logic_vector(0 to C_DWIDTH-1)
|
391 |
|
|
);
|
392 |
|
|
end dynshreg_f;
|
393 |
|
|
|
394 |
|
|
|
395 |
|
|
library unisim;
|
396 |
|
|
use unisim.all; -- Make unisim entities available for default binding.
|
397 |
|
|
architecture behavioral of dynshreg_f is
|
398 |
|
|
|
399 |
|
|
-- constant K_FAMILY : families_type := str2fam(C_FAMILY);
|
400 |
|
|
--
|
401 |
|
|
-- constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
|
402 |
|
|
-- (C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
|
403 |
|
|
-- constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
|
404 |
|
|
constant W32 : boolean := (C_DEPTH > 16);
|
405 |
|
|
constant W16 : boolean := (not W32);
|
406 |
|
|
-- XST faster if these two constants are declared here
|
407 |
|
|
-- instead of in STRUCTURAL_A_GEN. (I.25)
|
408 |
|
|
--
|
409 |
|
|
function power_of_2(n: positive) return boolean is
|
410 |
|
|
variable i: positive := 1;
|
411 |
|
|
begin
|
412 |
|
|
while n > i loop i := i*2; end loop;
|
413 |
|
|
return n = i;
|
414 |
|
|
end power_of_2;
|
415 |
|
|
--
|
416 |
|
|
-- constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
|
417 |
|
|
-- and ( (W16 and C_DEPTH >= 16)
|
418 |
|
|
-- or (W32 and C_DEPTH >= 32)
|
419 |
|
|
-- )
|
420 |
|
|
-- )
|
421 |
|
|
-- or (not W32 and not W16);
|
422 |
|
|
|
423 |
|
|
constant USE_INFERRED : boolean := true;
|
424 |
|
|
-- As of I.32, XST is not infering optimal dynamic shift registers for
|
425 |
|
|
-- depths not a power of two (by not taking advantage of don't care
|
426 |
|
|
-- at output when address not within the range of the depth)
|
427 |
|
|
-- or a power of two less than the native SRL depth (by building shift
|
428 |
|
|
-- register out of discrete FFs and LUTs instead of SRLs).
|
429 |
|
|
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
|
430 |
|
|
|
431 |
|
|
function min(a, b: natural) return natural is
|
432 |
|
|
begin
|
433 |
|
|
if a<b then return a; else return b; end if;
|
434 |
|
|
end min;
|
435 |
|
|
|
436 |
|
|
----------------------------------------------------------------------------
|
437 |
|
|
-- Unisim components declared locally for maximum avoidance of default
|
438 |
|
|
-- binding and vcomponents version issues.
|
439 |
|
|
----------------------------------------------------------------------------
|
440 |
|
|
component SRLC16E
|
441 |
|
|
generic
|
442 |
|
|
(
|
443 |
|
|
INIT : bit_vector := X"0000"
|
444 |
|
|
);
|
445 |
|
|
port
|
446 |
|
|
(
|
447 |
|
|
Q : out STD_ULOGIC;
|
448 |
|
|
Q15 : out STD_ULOGIC;
|
449 |
|
|
A0 : in STD_ULOGIC;
|
450 |
|
|
A1 : in STD_ULOGIC;
|
451 |
|
|
A2 : in STD_ULOGIC;
|
452 |
|
|
A3 : in STD_ULOGIC;
|
453 |
|
|
CE : in STD_ULOGIC;
|
454 |
|
|
CLK : in STD_ULOGIC;
|
455 |
|
|
D : in STD_ULOGIC
|
456 |
|
|
);
|
457 |
|
|
end component;
|
458 |
|
|
|
459 |
|
|
component SRLC32E
|
460 |
|
|
generic
|
461 |
|
|
(
|
462 |
|
|
INIT : bit_vector := X"00000000"
|
463 |
|
|
);
|
464 |
|
|
port
|
465 |
|
|
(
|
466 |
|
|
Q : out STD_ULOGIC;
|
467 |
|
|
Q31 : out STD_ULOGIC;
|
468 |
|
|
A : in STD_LOGIC_VECTOR (4 downto 0);
|
469 |
|
|
CE : in STD_ULOGIC;
|
470 |
|
|
CLK : in STD_ULOGIC;
|
471 |
|
|
D : in STD_ULOGIC
|
472 |
|
|
);
|
473 |
|
|
end component;
|
474 |
|
|
|
475 |
|
|
|
476 |
|
|
begin
|
477 |
|
|
|
478 |
|
|
---(
|
479 |
|
|
|
480 |
|
|
|
481 |
|
|
---(
|
482 |
|
|
INFERRED_GEN : if USE_INFERRED = true generate
|
483 |
|
|
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
|
484 |
|
|
signal data: dataType;
|
485 |
|
|
begin
|
486 |
|
|
process(Clk)
|
487 |
|
|
begin
|
488 |
|
|
if Clk'event and Clk = '1' then
|
489 |
|
|
if Clken = '1' then
|
490 |
|
|
data <= Din & data(0 to C_DEPTH-2);
|
491 |
|
|
end if;
|
492 |
|
|
end if;
|
493 |
|
|
end process;
|
494 |
|
|
|
495 |
|
|
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
|
496 |
|
|
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
|
497 |
|
|
else
|
498 |
|
|
(others => '-');
|
499 |
|
|
end generate INFERRED_GEN;
|
500 |
|
|
---)
|
501 |
|
|
|
502 |
|
|
end behavioral;
|
503 |
|
|
---)
|
504 |
|
|
|
505 |
|
|
|
506 |
|
|
-- srl_fifo_rbu_f - entity / architecture pair
|
507 |
|
|
-------------------------------------------------------------------------------
|
508 |
|
|
--
|
509 |
|
|
-- *************************************************************************
|
510 |
|
|
-- ** **
|
511 |
|
|
-- ** DISCLAIMER OF LIABILITY **
|
512 |
|
|
-- ** **
|
513 |
|
|
-- ** This text/file contains proprietary, confidential **
|
514 |
|
|
-- ** information of Xilinx, Inc., is distributed under **
|
515 |
|
|
-- ** license from Xilinx, Inc., and may be used, copied **
|
516 |
|
|
-- ** and/or disclosed only pursuant to the terms of a valid **
|
517 |
|
|
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
|
518 |
|
|
-- ** grants you a license to use this text/file solely for **
|
519 |
|
|
-- ** design, simulation, implementation and creation of **
|
520 |
|
|
-- ** design files limited to Xilinx devices or technologies. **
|
521 |
|
|
-- ** Use with non-Xilinx devices or technologies is expressly **
|
522 |
|
|
-- ** prohibited and immediately terminates your license unless **
|
523 |
|
|
-- ** covered by a separate agreement. **
|
524 |
|
|
-- ** **
|
525 |
|
|
-- ** Xilinx is providing this design, code, or information **
|
526 |
|
|
-- ** "as-is" solely for use in developing programs and **
|
527 |
|
|
-- ** solutions for Xilinx devices, with no obligation on the **
|
528 |
|
|
-- ** part of Xilinx to provide support. By providing this design, **
|
529 |
|
|
-- ** code, or information as one possible implementation of **
|
530 |
|
|
-- ** this feature, application or standard, Xilinx is making no **
|
531 |
|
|
-- ** representation that this implementation is free from any **
|
532 |
|
|
-- ** claims of infringement. You are responsible for obtaining **
|
533 |
|
|
-- ** any rights you may require for your implementation. **
|
534 |
|
|
-- ** Xilinx expressly disclaims any warranty whatsoever with **
|
535 |
|
|
-- ** respect to the adequacy of the implementation, including **
|
536 |
|
|
-- ** but not limited to any warranties or representations that this **
|
537 |
|
|
-- ** implementation is free from claims of infringement, implied **
|
538 |
|
|
-- ** warranties of merchantability or fitness for a particular **
|
539 |
|
|
-- ** purpose. **
|
540 |
|
|
-- ** **
|
541 |
|
|
-- ** Xilinx products are not intended for use in life support **
|
542 |
|
|
-- ** appliances, devices, or systems. Use in such applications is **
|
543 |
|
|
-- ** expressly prohibited. **
|
544 |
|
|
-- ** **
|
545 |
|
|
-- ** Any modifications that are made to the Source Code are **
|
546 |
|
|
-- ** done at the user’s sole risk and will be unsupported. **
|
547 |
|
|
-- ** The Xilinx Support Hotline does not have access to source **
|
548 |
|
|
-- ** code and therefore cannot answer specific questions related **
|
549 |
|
|
-- ** to source HDL. The Xilinx Hotline support of original source **
|
550 |
|
|
-- ** code IP shall only address issues and questions related **
|
551 |
|
|
-- ** to the standard Netlist version of the core (and thus **
|
552 |
|
|
-- ** indirectly, the original core source). **
|
553 |
|
|
-- ** **
|
554 |
|
|
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
|
555 |
|
|
-- ** **
|
556 |
|
|
-- ** This copyright and support notice must be retained as part **
|
557 |
|
|
-- ** of this text at all times. **
|
558 |
|
|
-- ** **
|
559 |
|
|
-- *************************************************************************
|
560 |
|
|
--
|
561 |
|
|
-------------------------------------------------------------------------------
|
562 |
|
|
-- Filename: srl_fifo_rbu_f.vhd
|
563 |
|
|
--
|
564 |
|
|
-- Description: A small-to-medium depth FIFO with optional
|
565 |
|
|
-- capability to back up and reread data. For
|
566 |
|
|
-- data storage, the SRL elements native to the
|
567 |
|
|
-- target FGPA family are used. If the FIFO depth
|
568 |
|
|
-- exceeds the available depth of the SRL elements,
|
569 |
|
|
-- then SRLs are cascaded and MUXFN elements are
|
570 |
|
|
-- used to select the output of the appropriate SRL stage.
|
571 |
|
|
--
|
572 |
|
|
-- Features:
|
573 |
|
|
-- - Width and depth are arbitrary, but each doubling of
|
574 |
|
|
-- depth, starting from the native SRL depth, adds
|
575 |
|
|
-- a level of MUXFN. Generally, in performance-oriented
|
576 |
|
|
-- applications, the fifo depth may need to be limited to
|
577 |
|
|
-- not exceed the SRL cascade depth supported by local
|
578 |
|
|
-- fast interconnect or the number of MUXFN levels.
|
579 |
|
|
-- However, deeper fifos will correctly build.
|
580 |
|
|
-- - Commands: read, write, and reread n.
|
581 |
|
|
-- - Flags: empty and full.
|
582 |
|
|
-- - The reread n command (executed by applying
|
583 |
|
|
-- a non-zero value, n, to signal Num_To_Reread
|
584 |
|
|
-- for one clock period) allows n
|
585 |
|
|
-- previously read elements to be restored to the FIFO,
|
586 |
|
|
-- limited, however, to the number of elements that have
|
587 |
|
|
-- not been overwritten. (It is the user's responsibility
|
588 |
|
|
-- to assure that the elements being restored are
|
589 |
|
|
-- actually in the FIFO storage; once the depth of the
|
590 |
|
|
-- FIFO has been written, the maximum number that can
|
591 |
|
|
-- be restored is equal to the vacancy.)
|
592 |
|
|
-- The reread capability does not cost extra LUTs or FFs.
|
593 |
|
|
-- - Commands may be asserted simultaneously.
|
594 |
|
|
-- However, if read and reread n are asserted
|
595 |
|
|
-- simultaneously, only the read is carried out.
|
596 |
|
|
-- - Overflow and underflow are detected and latched until
|
597 |
|
|
-- Reset. The state of the FIFO is undefined during
|
598 |
|
|
-- status of underflow or overflow.
|
599 |
|
|
-- Underflow can occur only by reading the FIFO when empty.
|
600 |
|
|
-- Overflow can occur either from a write, a reread n,
|
601 |
|
|
-- or a combination of both that would result in more
|
602 |
|
|
-- elements occupying the FIFO that its C_DEPTH.
|
603 |
|
|
-- - Any of the signals FIFO_Full, Underflow, or Overflow
|
604 |
|
|
-- left unconnected can be expected to be trimmed.
|
605 |
|
|
-- - The Addr output is always one less than the current
|
606 |
|
|
-- occupancy when the FIFO is non-empty, and is all ones
|
607 |
|
|
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
|
608 |
|
|
-- i.e. FIFO_Empty concatenated on the left with Addr--
|
609 |
|
|
-- when taken as a signed value, is one less than the
|
610 |
|
|
-- current occupancy.
|
611 |
|
|
-- This information can be used to generate additional
|
612 |
|
|
-- flags, if needed.
|
613 |
|
|
--
|
614 |
|
|
-- VHDL-Standard: VHDL'93
|
615 |
|
|
-------------------------------------------------------------------------------
|
616 |
|
|
-- Structure:
|
617 |
|
|
-- srl_fifo_rbu_f.vhd
|
618 |
|
|
-- dynshreg_f.vhd
|
619 |
|
|
-- cntr_incr_decr_addn_f.vhd
|
620 |
|
|
--
|
621 |
|
|
-------------------------------------------------------------------------------
|
622 |
|
|
-- Author: Farrell Ostler
|
623 |
|
|
--
|
624 |
|
|
-- History:
|
625 |
|
|
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
|
626 |
|
|
-- ~~~~~~
|
627 |
|
|
-- FLO 2007-12-12
|
628 |
|
|
-- ^^^^^^
|
629 |
|
|
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
|
630 |
|
|
-- ~~~~~~
|
631 |
|
|
--
|
632 |
|
|
-- DET 1/17/2008 v5_0
|
633 |
|
|
-- ~~~~~~
|
634 |
|
|
-- - Changed lib library version to v5_0
|
635 |
|
|
-- - Incorporated new disclaimer header
|
636 |
|
|
-- ^^^^^^
|
637 |
|
|
-- FLO 2008-11-25
|
638 |
|
|
-- ^^^^^^
|
639 |
|
|
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
|
640 |
|
|
-- steers the current XST toward a better implementation. CR 496211.
|
641 |
|
|
-- ~~~~~~
|
642 |
|
|
--
|
643 |
|
|
-------------------------------------------------------------------------------
|
644 |
|
|
-- Naming Conventions:
|
645 |
|
|
-- active low signals: "*_n"
|
646 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
647 |
|
|
-- reset signals: "rst", "rst_n"
|
648 |
|
|
-- generics: "C_*"
|
649 |
|
|
-- user defined types: "*_TYPE"
|
650 |
|
|
-- state machine next state: "*_ns"
|
651 |
|
|
-- state machine current state: "*_cs"
|
652 |
|
|
-- combinatorial signals: "*_com"
|
653 |
|
|
-- pipelined or register delay signals: "*_d#"
|
654 |
|
|
-- predecessor value by # clks: "*_p#"
|
655 |
|
|
-- counter signals: "*cnt*"
|
656 |
|
|
-- clock enable signals: "*_ce"
|
657 |
|
|
-- internal version of output port "*_i"
|
658 |
|
|
-- device pins: "*_pin"
|
659 |
|
|
-- ports: - Names begin with Uppercase
|
660 |
|
|
-- processes: "*_PROCESS"
|
661 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
662 |
|
|
-------------------------------------------------------------------------------
|
663 |
|
|
|
664 |
|
|
|
665 |
|
|
library ieee;
|
666 |
|
|
use ieee.std_logic_1164.all;
|
667 |
|
|
use ieee.numeric_std.UNSIGNED;
|
668 |
|
|
use ieee.numeric_std.">=";
|
669 |
|
|
use ieee.numeric_std.TO_UNSIGNED;
|
670 |
|
|
library lib_pkg_v1_0_2;
|
671 |
|
|
use lib_pkg_v1_0_2.lib_pkg.clog2;
|
672 |
|
|
library lib_srl_fifo_v1_0_2;
|
673 |
|
|
|
674 |
|
|
entity srl_fifo_rbu_f is
|
675 |
|
|
generic (
|
676 |
|
|
C_DWIDTH : natural;
|
677 |
|
|
C_DEPTH : positive := 16;
|
678 |
|
|
C_FAMILY : string := "nofamily"
|
679 |
|
|
);
|
680 |
|
|
port (
|
681 |
|
|
Clk : in std_logic;
|
682 |
|
|
Reset : in std_logic;
|
683 |
|
|
FIFO_Write : in std_logic;
|
684 |
|
|
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
|
685 |
|
|
FIFO_Read : in std_logic;
|
686 |
|
|
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
|
687 |
|
|
FIFO_Full : out std_logic;
|
688 |
|
|
FIFO_Empty : out std_logic;
|
689 |
|
|
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
|
690 |
|
|
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
|
691 |
|
|
Underflow : out std_logic;
|
692 |
|
|
Overflow : out std_logic
|
693 |
|
|
);
|
694 |
|
|
end entity srl_fifo_rbu_f;
|
695 |
|
|
|
696 |
|
|
|
697 |
|
|
architecture imp of srl_fifo_rbu_f is
|
698 |
|
|
|
699 |
|
|
function bitwise_or(s: std_logic_vector) return std_logic is
|
700 |
|
|
variable v: std_logic := '0';
|
701 |
|
|
begin
|
702 |
|
|
for i in s'range loop v := v or s(i); end loop;
|
703 |
|
|
return v;
|
704 |
|
|
end bitwise_or;
|
705 |
|
|
|
706 |
|
|
constant ADDR_BITS : integer := clog2(C_DEPTH);
|
707 |
|
|
|
708 |
|
|
-- An extra bit will be carried as the empty flag.
|
709 |
|
|
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
|
710 |
|
|
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
|
711 |
|
|
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
|
712 |
|
|
signal fifo_empty_i : std_logic;
|
713 |
|
|
signal overflow_i : std_logic;
|
714 |
|
|
signal underflow_i : std_logic;
|
715 |
|
|
signal fifo_full_p1 : std_logic;
|
716 |
|
|
|
717 |
|
|
begin
|
718 |
|
|
|
719 |
|
|
fifo_empty_i <= addr_i(ADDR_BITS);
|
720 |
|
|
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
|
721 |
|
|
FIFO_Empty <= fifo_empty_i;
|
722 |
|
|
|
723 |
|
|
num_to_reread_zeroext <= '0' & Num_To_Reread;
|
724 |
|
|
|
725 |
|
|
|
726 |
|
|
----------------------------------------------------------------------------
|
727 |
|
|
-- The FIFO address counter. Addresses the next element to be read.
|
728 |
|
|
-- All ones when the FIFO is empty.
|
729 |
|
|
----------------------------------------------------------------------------
|
730 |
|
|
CNTR_INCR_DECR_ADDN_F_I : entity lib_srl_fifo_v1_0_2.cntr_incr_decr_addn_f
|
731 |
|
|
generic map (
|
732 |
|
|
C_SIZE => ADDR_BITS + 1,
|
733 |
|
|
C_FAMILY => C_FAMILY
|
734 |
|
|
)
|
735 |
|
|
port map (
|
736 |
|
|
Clk => Clk,
|
737 |
|
|
Reset => Reset,
|
738 |
|
|
Incr => FIFO_Write,
|
739 |
|
|
Decr => FIFO_Read,
|
740 |
|
|
N_to_add => num_to_reread_zeroext,
|
741 |
|
|
Cnt => addr_i,
|
742 |
|
|
Cnt_p1 => addr_i_p1
|
743 |
|
|
);
|
744 |
|
|
|
745 |
|
|
|
746 |
|
|
----------------------------------------------------------------------------
|
747 |
|
|
-- The dynamic shift register that holds the FIFO elements.
|
748 |
|
|
----------------------------------------------------------------------------
|
749 |
|
|
DYNSHREG_F_I : entity lib_srl_fifo_v1_0_2.dynshreg_f
|
750 |
|
|
generic map (
|
751 |
|
|
C_DEPTH => C_DEPTH,
|
752 |
|
|
C_DWIDTH => C_DWIDTH,
|
753 |
|
|
C_FAMILY => C_FAMILY
|
754 |
|
|
)
|
755 |
|
|
port map (
|
756 |
|
|
Clk => Clk,
|
757 |
|
|
Clken => FIFO_Write,
|
758 |
|
|
Addr => addr_i(ADDR_BITS-1 downto 0),
|
759 |
|
|
Din => Data_In,
|
760 |
|
|
Dout => Data_Out
|
761 |
|
|
);
|
762 |
|
|
|
763 |
|
|
|
764 |
|
|
----------------------------------------------------------------------------
|
765 |
|
|
-- Full flag.
|
766 |
|
|
----------------------------------------------------------------------------
|
767 |
|
|
fifo_full_p1 <= '1' when ( addr_i_p1
|
768 |
|
|
= std_logic_vector(
|
769 |
|
|
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
|
770 |
|
|
)
|
771 |
|
|
)
|
772 |
|
|
else '0';
|
773 |
|
|
|
774 |
|
|
FULL_PROCESS: process (Clk)
|
775 |
|
|
begin
|
776 |
|
|
if Clk'event and Clk='1' then
|
777 |
|
|
if Reset='1' then
|
778 |
|
|
FIFO_Full <= '0';
|
779 |
|
|
else
|
780 |
|
|
FIFO_Full <= fifo_full_p1;
|
781 |
|
|
end if;
|
782 |
|
|
end if;
|
783 |
|
|
end process;
|
784 |
|
|
|
785 |
|
|
|
786 |
|
|
----------------------------------------------------------------------------
|
787 |
|
|
-- Underflow detection.
|
788 |
|
|
----------------------------------------------------------------------------
|
789 |
|
|
UNDERFLOW_PROCESS: process (Clk)
|
790 |
|
|
begin
|
791 |
|
|
if Clk'event and Clk='1' then
|
792 |
|
|
if Reset = '1' then
|
793 |
|
|
underflow_i <= '0';
|
794 |
|
|
elsif underflow_i = '1' then
|
795 |
|
|
underflow_i <= '1'; -- Underflow sticks until reset
|
796 |
|
|
else
|
797 |
|
|
underflow_i <= fifo_empty_i and FIFO_Read;
|
798 |
|
|
end if;
|
799 |
|
|
end if;
|
800 |
|
|
end process;
|
801 |
|
|
|
802 |
|
|
Underflow <= underflow_i;
|
803 |
|
|
|
804 |
|
|
|
805 |
|
|
----------------------------------------------------------------------------
|
806 |
|
|
-- Overflow detection.
|
807 |
|
|
-- The only case of non-erroneous operation for which addr_i (including
|
808 |
|
|
-- the high-order bit used as the empty flag) taken as an unsigned value
|
809 |
|
|
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
|
810 |
|
|
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
|
811 |
|
|
-- overriden in this case and the number elements can at most remain
|
812 |
|
|
-- unchanged (that being when there is a simultaneous FIFO_Write).
|
813 |
|
|
-- However, when there is no FIFO_Read and there is either a
|
814 |
|
|
-- FIFO_Write or a restoration of one or more read elements, or both, then
|
815 |
|
|
-- addr_i, extended by the carry-out bit, becoming greater than
|
816 |
|
|
-- or equal to C_DEPTH indicates an overflow.
|
817 |
|
|
----------------------------------------------------------------------------
|
818 |
|
|
OVERFLOW_PROCESS: process (Clk)
|
819 |
|
|
begin
|
820 |
|
|
if Clk'event and Clk='1' then
|
821 |
|
|
if Reset = '1' then
|
822 |
|
|
overflow_i <= '0';
|
823 |
|
|
elsif overflow_i = '1' then
|
824 |
|
|
overflow_i <= '1'; -- Overflow sticks until Reset
|
825 |
|
|
elsif FIFO_Read = '0' and
|
826 |
|
|
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
|
827 |
|
|
UNSIGNED(addr_i_p1) >= C_DEPTH then
|
828 |
|
|
overflow_i <= '1';
|
829 |
|
|
else
|
830 |
|
|
overflow_i <= '0';
|
831 |
|
|
end if;
|
832 |
|
|
end if;
|
833 |
|
|
end process;
|
834 |
|
|
|
835 |
|
|
Overflow <= overflow_i;
|
836 |
|
|
|
837 |
|
|
end architecture imp;
|
838 |
|
|
|
839 |
|
|
|
840 |
|
|
-- srl_fifo_f - entity / architecture pair
|
841 |
|
|
-------------------------------------------------------------------------------
|
842 |
|
|
--
|
843 |
|
|
-- *************************************************************************
|
844 |
|
|
-- ** **
|
845 |
|
|
-- ** DISCLAIMER OF LIABILITY **
|
846 |
|
|
-- ** **
|
847 |
|
|
-- ** This text/file contains proprietary, confidential **
|
848 |
|
|
-- ** information of Xilinx, Inc., is distributed under **
|
849 |
|
|
-- ** license from Xilinx, Inc., and may be used, copied **
|
850 |
|
|
-- ** and/or disclosed only pursuant to the terms of a valid **
|
851 |
|
|
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
|
852 |
|
|
-- ** grants you a license to use this text/file solely for **
|
853 |
|
|
-- ** design, simulation, implementation and creation of **
|
854 |
|
|
-- ** design files limited to Xilinx devices or technologies. **
|
855 |
|
|
-- ** Use with non-Xilinx devices or technologies is expressly **
|
856 |
|
|
-- ** prohibited and immediately terminates your license unless **
|
857 |
|
|
-- ** covered by a separate agreement. **
|
858 |
|
|
-- ** **
|
859 |
|
|
-- ** Xilinx is providing this design, code, or information **
|
860 |
|
|
-- ** "as-is" solely for use in developing programs and **
|
861 |
|
|
-- ** solutions for Xilinx devices, with no obligation on the **
|
862 |
|
|
-- ** part of Xilinx to provide support. By providing this design, **
|
863 |
|
|
-- ** code, or information as one possible implementation of **
|
864 |
|
|
-- ** this feature, application or standard, Xilinx is making no **
|
865 |
|
|
-- ** representation that this implementation is free from any **
|
866 |
|
|
-- ** claims of infringement. You are responsible for obtaining **
|
867 |
|
|
-- ** any rights you may require for your implementation. **
|
868 |
|
|
-- ** Xilinx expressly disclaims any warranty whatsoever with **
|
869 |
|
|
-- ** respect to the adequacy of the implementation, including **
|
870 |
|
|
-- ** but not limited to any warranties or representations that this **
|
871 |
|
|
-- ** implementation is free from claims of infringement, implied **
|
872 |
|
|
-- ** warranties of merchantability or fitness for a particular **
|
873 |
|
|
-- ** purpose. **
|
874 |
|
|
-- ** **
|
875 |
|
|
-- ** Xilinx products are not intended for use in life support **
|
876 |
|
|
-- ** appliances, devices, or systems. Use in such applications is **
|
877 |
|
|
-- ** expressly prohibited. **
|
878 |
|
|
-- ** **
|
879 |
|
|
-- ** Any modifications that are made to the Source Code are **
|
880 |
|
|
-- ** done at the user’s sole risk and will be unsupported. **
|
881 |
|
|
-- ** The Xilinx Support Hotline does not have access to source **
|
882 |
|
|
-- ** code and therefore cannot answer specific questions related **
|
883 |
|
|
-- ** to source HDL. The Xilinx Hotline support of original source **
|
884 |
|
|
-- ** code IP shall only address issues and questions related **
|
885 |
|
|
-- ** to the standard Netlist version of the core (and thus **
|
886 |
|
|
-- ** indirectly, the original core source). **
|
887 |
|
|
-- ** **
|
888 |
|
|
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
|
889 |
|
|
-- ** **
|
890 |
|
|
-- ** This copyright and support notice must be retained as part **
|
891 |
|
|
-- ** of this text at all times. **
|
892 |
|
|
-- ** **
|
893 |
|
|
-- *************************************************************************
|
894 |
|
|
--
|
895 |
|
|
-------------------------------------------------------------------------------
|
896 |
|
|
-- Filename: srl_fifo_f.vhd
|
897 |
|
|
--
|
898 |
|
|
-- Description: A small-to-medium depth FIFO. For
|
899 |
|
|
-- data storage, the SRL elements native to the
|
900 |
|
|
-- target FGPA family are used. If the FIFO depth
|
901 |
|
|
-- exceeds the available depth of the SRL elements,
|
902 |
|
|
-- then SRLs are cascaded and MUXFN elements are
|
903 |
|
|
-- used to select the output of the appropriate SRL stage.
|
904 |
|
|
--
|
905 |
|
|
-- Features:
|
906 |
|
|
-- - Width and depth are arbitrary, but each doubling of
|
907 |
|
|
-- depth, starting from the native SRL depth, adds
|
908 |
|
|
-- a level of MUXFN. Generally, in performance-oriented
|
909 |
|
|
-- applications, the fifo depth may need to be limited to
|
910 |
|
|
-- not exceed the SRL cascade depth supported by local
|
911 |
|
|
-- fast interconnect or the number of MUXFN levels.
|
912 |
|
|
-- However, deeper fifos will correctly build.
|
913 |
|
|
-- - Commands: read, write.
|
914 |
|
|
-- - Flags: empty and full.
|
915 |
|
|
-- - The Addr output is always one less than the current
|
916 |
|
|
-- occupancy when the FIFO is non-empty, and is all ones
|
917 |
|
|
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
|
918 |
|
|
-- i.e. FIFO_Empty concatenated on the left to Addr--
|
919 |
|
|
-- when taken as a signed value, is one less than the
|
920 |
|
|
-- current occupancy.
|
921 |
|
|
--
|
922 |
|
|
-- VHDL-Standard: VHDL'93
|
923 |
|
|
-------------------------------------------------------------------------------
|
924 |
|
|
-- Structure:
|
925 |
|
|
-- srl_fifo_f.vhd
|
926 |
|
|
-- srl_fifo_rbu_f.vhd
|
927 |
|
|
-- proc_common_pkg.vhd
|
928 |
|
|
--
|
929 |
|
|
-------------------------------------------------------------------------------
|
930 |
|
|
-- Author: Farrell Ostler
|
931 |
|
|
--
|
932 |
|
|
-- History:
|
933 |
|
|
-- FLO 12/13/05 First Version.
|
934 |
|
|
--
|
935 |
|
|
-- FLO 04/27/06
|
936 |
|
|
-- ^^^^^^
|
937 |
|
|
-- C_FAMILY made to default to "nofamily".
|
938 |
|
|
-- ~~~~~~
|
939 |
|
|
-- FLO 2007-12-12
|
940 |
|
|
-- ^^^^^^
|
941 |
|
|
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
|
942 |
|
|
-- ~~~~~~
|
943 |
|
|
--
|
944 |
|
|
-- DET 1/17/2008 v5_0
|
945 |
|
|
-- ~~~~~~
|
946 |
|
|
-- - Changed proc_common library version to v5_0
|
947 |
|
|
-- - Incorporated new disclaimer header
|
948 |
|
|
-- ^^^^^^
|
949 |
|
|
--
|
950 |
|
|
-------------------------------------------------------------------------------
|
951 |
|
|
-- Naming Conventions:
|
952 |
|
|
-- active low signals: "*_n"
|
953 |
|
|
-- clock signals: "clk", "clk_div#", "clk_#x"
|
954 |
|
|
-- reset signals: "rst", "rst_n"
|
955 |
|
|
-- generics: "C_*"
|
956 |
|
|
-- user defined types: "*_TYPE"
|
957 |
|
|
-- state machine next state: "*_ns"
|
958 |
|
|
-- state machine current state: "*_cs"
|
959 |
|
|
-- combinatorial signals: "*_com"
|
960 |
|
|
-- pipelined or register delay signals: "*_d#"
|
961 |
|
|
-- counter signals: "*cnt*"
|
962 |
|
|
-- clock enable signals: "*_ce"
|
963 |
|
|
-- internal version of output port "*_i"
|
964 |
|
|
-- device pins: "*_pin"
|
965 |
|
|
-- ports: - Names begin with Uppercase
|
966 |
|
|
-- processes: "*_PROCESS"
|
967 |
|
|
-- component instantiations: "<ENTITY_>I_<#|FUNC>
|
968 |
|
|
-------------------------------------------------------------------------------
|
969 |
|
|
-- predecessor value by # clks: "*_p#"
|
970 |
|
|
|
971 |
|
|
|
972 |
|
|
library ieee;
|
973 |
|
|
use ieee.std_logic_1164.all;
|
974 |
|
|
library lib_srl_fifo_v1_0_2;
|
975 |
|
|
library lib_pkg_v1_0_2;
|
976 |
|
|
use lib_pkg_v1_0_2.lib_pkg.clog2;
|
977 |
|
|
--
|
978 |
|
|
entity srl_fifo_f is
|
979 |
|
|
generic (
|
980 |
|
|
C_DWIDTH : natural;
|
981 |
|
|
C_DEPTH : positive := 16;
|
982 |
|
|
C_FAMILY : string := "nofamily"
|
983 |
|
|
);
|
984 |
|
|
port (
|
985 |
|
|
Clk : in std_logic;
|
986 |
|
|
Reset : in std_logic;
|
987 |
|
|
FIFO_Write : in std_logic;
|
988 |
|
|
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
|
989 |
|
|
FIFO_Read : in std_logic;
|
990 |
|
|
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
|
991 |
|
|
FIFO_Empty : out std_logic;
|
992 |
|
|
FIFO_Full : out std_logic;
|
993 |
|
|
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
|
994 |
|
|
);
|
995 |
|
|
|
996 |
|
|
end entity srl_fifo_f;
|
997 |
|
|
|
998 |
|
|
|
999 |
|
|
--
|
1000 |
|
|
architecture imp of srl_fifo_f is
|
1001 |
|
|
|
1002 |
|
|
attribute DowngradeIPIdentifiedWarnings: string;
|
1003 |
|
|
|
1004 |
|
|
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
|
1005 |
|
|
|
1006 |
|
|
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
|
1007 |
|
|
begin
|
1008 |
|
|
|
1009 |
|
|
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
|
1010 |
|
|
generic map (
|
1011 |
|
|
C_DWIDTH => C_DWIDTH,
|
1012 |
|
|
C_DEPTH => C_DEPTH,
|
1013 |
|
|
C_FAMILY => C_FAMILY
|
1014 |
|
|
)
|
1015 |
|
|
port map (
|
1016 |
|
|
Clk => Clk,
|
1017 |
|
|
Reset => Reset,
|
1018 |
|
|
FIFO_Write => FIFO_Write,
|
1019 |
|
|
Data_In => Data_In,
|
1020 |
|
|
FIFO_Read => FIFO_Read,
|
1021 |
|
|
Data_Out => Data_Out,
|
1022 |
|
|
FIFO_Full => FIFO_Full,
|
1023 |
|
|
FIFO_Empty => FIFO_Empty,
|
1024 |
|
|
Addr => Addr,
|
1025 |
|
|
Num_To_Reread => ZEROES,
|
1026 |
|
|
Underflow => open,
|
1027 |
|
|
Overflow => open
|
1028 |
|
|
);
|
1029 |
|
|
|
1030 |
|
|
end architecture imp;
|
1031 |
|
|
|
1032 |
|
|
|