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// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:axi_uartlite:2.0
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// IP Revision: 19
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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axi_uartlite_module_sim your_instance_name (
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.s_axi_aclk(s_axi_aclk), // input wire s_axi_aclk
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.s_axi_aresetn(s_axi_aresetn), // input wire s_axi_aresetn
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.interrupt(interrupt), // output wire interrupt
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.s_axi_awaddr(s_axi_awaddr), // input wire [3 : 0] s_axi_awaddr
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.s_axi_awvalid(s_axi_awvalid), // input wire s_axi_awvalid
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.s_axi_awready(s_axi_awready), // output wire s_axi_awready
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.s_axi_wdata(s_axi_wdata), // input wire [31 : 0] s_axi_wdata
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.s_axi_wstrb(s_axi_wstrb), // input wire [3 : 0] s_axi_wstrb
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.s_axi_wvalid(s_axi_wvalid), // input wire s_axi_wvalid
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.s_axi_wready(s_axi_wready), // output wire s_axi_wready
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.s_axi_bresp(s_axi_bresp), // output wire [1 : 0] s_axi_bresp
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.s_axi_bvalid(s_axi_bvalid), // output wire s_axi_bvalid
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.s_axi_bready(s_axi_bready), // input wire s_axi_bready
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.s_axi_araddr(s_axi_araddr), // input wire [3 : 0] s_axi_araddr
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.s_axi_arvalid(s_axi_arvalid), // input wire s_axi_arvalid
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.s_axi_arready(s_axi_arready), // output wire s_axi_arready
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.s_axi_rdata(s_axi_rdata), // output wire [31 : 0] s_axi_rdata
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.s_axi_rresp(s_axi_rresp), // output wire [1 : 0] s_axi_rresp
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.s_axi_rvalid(s_axi_rvalid), // output wire s_axi_rvalid
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.s_axi_rready(s_axi_rready), // input wire s_axi_rready
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.rx(rx), // input wire rx
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.tx(tx) // output wire tx
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file axi_uartlite_module_sim.v when simulating
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// the core, axi_uartlite_module_sim. When compiling the wrapper file, be sure to
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// reference the Verilog simulation library.
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