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Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [axi_uartlite_module_sim/] [axi_uartlite_module_sim.xml] - Blame information for rev 2

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  xilinx.com
  customized_ip
  axi_uartlite_module_sim
  1.0
  
    
      S_AXI
      S_AXI
      
      
      
      
        
          
            ARADDR
          
          
            s_axi_araddr
          
        
        
          
            ARREADY
          
          
            s_axi_arready
          
        
        
          
            ARVALID
          
          
            s_axi_arvalid
          
        
        
          
            AWADDR
          
          
            s_axi_awaddr
          
        
        
          
            AWREADY
          
          
            s_axi_awready
          
        
        
          
            AWVALID
          
          
            s_axi_awvalid
          
        
        
          
            BREADY
          
          
            s_axi_bready
          
        
        
          
            BRESP
          
          
            s_axi_bresp
          
        
        
          
            BVALID
          
          
            s_axi_bvalid
          
        
        
          
            RDATA
          
          
            s_axi_rdata
          
        
        
          
            RREADY
          
          
            s_axi_rready
          
        
        
          
            RRESP
          
          
            s_axi_rresp
          
        
        
          
            RVALID
          
          
            s_axi_rvalid
          
        
        
          
            WDATA
          
          
            s_axi_wdata
          
        
        
          
            WREADY
          
          
            s_axi_wready
          
        
        
          
            WSTRB
          
          
            s_axi_wstrb
          
        
        
          
            WVALID
          
          
            s_axi_wvalid
          
        
      
      
        
          DATA_WIDTH
          32
          
            
              none
            
          
        
        
          PROTOCOL
          AXI4LITE
          
            
              none
            
          
        
        
          FREQ_HZ
          100000000
          
            
              none
            
          
        
        
          ID_WIDTH
          0
          
            
              none
            
          
        
        
          ADDR_WIDTH
          4
          
            
              none
            
          
        
        
          AWUSER_WIDTH
          0
          
            
              none
            
          
        
        
          ARUSER_WIDTH
          0
          
            
              none
            
          
        
        
          WUSER_WIDTH
          0
          
            
              none
            
          
        
        
          RUSER_WIDTH
          0
          
            
              none
            
          
        
        
          BUSER_WIDTH
          0
          
            
              none
            
          
        
        
          READ_WRITE_MODE
          READ_WRITE
          
            
              none
            
          
        
        
          HAS_BURST
          0
          
            
              none
            
          
        
        
          HAS_LOCK
          0
          
            
              none
            
          
        
        
          HAS_PROT
          0
          
            
              none
            
          
        
        
          HAS_CACHE
          0
          
            
              none
            
          
        
        
          HAS_QOS
          0
          
            
              none
            
          
        
        
          HAS_REGION
          0
          
            
              none
            
          
        
        
          HAS_WSTRB
          1
          
            
              none
            
          
        
        
          HAS_BRESP
          1
          
            
              none
            
          
        
        
          HAS_RRESP
          1
          
            
              none
            
          
        
        
          SUPPORTS_NARROW_BURST
          0
          
            
              none
            
          
        
        
          NUM_READ_OUTSTANDING
          1
          
            
              none
            
          
        
        
          NUM_WRITE_OUTSTANDING
          1
          
            
              none
            
          
        
        
          MAX_BURST_LENGTH
          1
          
            
              none
            
          
        
        
          PHASE
          0.000
          
            
              none
            
          
        
        
          CLK_DOMAIN
          
          
            
              none
            
          
        
        
          NUM_READ_THREADS
          1
          
            
              none
            
          
        
        
          NUM_WRITE_THREADS
          1
          
            
              none
            
          
        
        
          RUSER_BITS_PER_BYTE
          0
          
            
              none
            
          
        
        
          WUSER_BITS_PER_BYTE
          0
          
            
              none
            
          
        
      
    
    
      ACLK
      aclk
      
      
      
      
        
          
            CLK
          
          
            s_axi_aclk
          
        
      
      
        
          ASSOCIATED_BUSIF
          S_AXI
        
        
          ASSOCIATED_RESET
          s_axi_aresetn
        
        
          FREQ_HZ
          100000000
          
            
              none
            
          
        
        
          PHASE
          0.000
          
            
              none
            
          
        
        
          CLK_DOMAIN
          
          
            
              none
            
          
        
      
    
    
      ARESETN
      aresetn
      
      
      
      
        
          
            RST
          
          
            s_axi_aresetn
          
        
      
      
        
          POLARITY
          ACTIVE_LOW
        
      
    
    
      INTERRUPT
      interrupt
      
      
      
      
        
          
            INTERRUPT
          
          
            interrupt
          
        
      
      
        
          SENSITIVITY
          EDGE_RISING
        
        
          PortWidth
          1
          
            
              none
            
          
        
      
    
    
      UART
      uart
      
      
      
      
        
          
            RxD
          
          
            rx
          
        
        
          
            TxD
          
          
            tx
          
        
      
      
        
          BOARD.ASSOCIATED_PARAM
          UARTLITE_BOARD_INTERFACE
          
            
              
                required
              
            
          
        
      
    
  
  
    
      S_AXI
      S_AXI_MEM
      Memory Map for S_AXI
      
        Reg
        Reg
        Register Block
        0
        4096
        32
        register
        read-write
        
          RX_FIFO
          RX FIFO
          Receive data FIFO
          0x0
          32
          true
          read-only
          
            0x0
          
          
            RX_DATA
            Receive Data
            UART Receive Data

            0
            8
            true
            read-only
            
              0
              0
            
            false
          
        
        
          TX_FIFO
          TX FIFO
          Transmit data FIFO
          0x4
          32
          true
          write-only
          
            0x0
          
          
            TX_DATA
            Transmit Data
            UART Transmit Data

            0
            8
            true
            write-only
            
              0
              0
            
            false
          
        
        
          CTRL_REG
          Control Register
          UART Lite control register
          0xC
          32
          true
          write-only
          
            0x0
          
          
            RST_TXFIFO
            Reset Tx FIFO
            Reset/clear the transmit FIFO
Writing a 1 to this bit position clears the transmit FIFO
 
  1 - Clear the transmit FIFO

            0
            1
            true
            write-only
            
              0
              0
            
            false
          
          
            RST_RXFIFO
            Reset Rx FIFO
            Reset/clear the receive FIFO
Writing a 1 to this bit position clears the receive FIFO
 
  1 - Clear the receive FIFO

            1
            1
            true
            write-only
            
              0
              0
            
            false
          
          
            Enable_Intr
            Enable interrupt
            Enable interrupt for the AXI UART Lite
 
  1 - Enable interrupt signal

            4
            1
            true
            write-only
            
              0
              0
            
            false
          
        
        
          STAT_REG
          Status Register
          UART Lite status register
          0x8
          32
          true
          read-only
          
            0x0
          
          
            RX_FIFO_Valid_Data
            RX FIFO Valid Data
            Indicates if the receive FIFO has data.
 
  1 - Receive FIFO has data

            0
            1
            true
            read-only
            
              0
              0
            
            false
          
          
            RX_FIFO_Full
            RX FIFO Full
            Indicates if the receive FIFO is full.
 
  1 - Receive FIFO is full

            1
            1
            true
            read-only
            
              0
              0
            
            false
          
          
            TX_FIFO_Empty
            TX FIFO Empty
            Indicates if the transmit FIFO is empty.
 
  1 - Transmit FIFO is empty

            2
            1
            true
            read-only
            
              0
              0
            
            false
          
          
            TX_FIFO_Full
            TX FIFO Full
            Indicates if the transmit FIFO is full.
 
  1 - Transmit FIFO is full

            3
            1
            true
            read-only
            
              0
              0
            
            false
          
          
            Intr_Enabled
            Interrupt Enabled
            Indicates that interrupts is enabled.
 
  1 - Interrupt is enabled

            4
            1
            true
            read-only
            
              0
              0
            
            false
          
          
            Overrun_Error
            Overrun Error
            Indicates that a overrun error has occurred after the last time the status register was read. Overrun is when a new character has been received but the receive FIFO is full. The received character is ignored and not written into the receive FIFO. This bit is cleared when the status register is read.      0 - No overrun error has occurred      1 - Overrun error has occurred

            5
            1
            true
            read-only
            
              0
              0
            
            false
          
          
            Frame_Error
            Frame Error
            Indicates that a frame error has occurred after the last time the status register was read. Frame error is defined as detection of a stop bit with the value 0. The receive character is ignored and not written to the receive FIFO. This bit is cleared when the status register is read.      0 - No frame error has occurred   1 - Frame error has occurred

            6
            1
            true
            read-only
            
              0
              0
            
            false
          
          
            Parity_Error
            Parity Error
            Indicates that a parity error has occurred after the last time the status register was read. If the UART is configured without any parity handling, this bit is always 0. The received character is written into the receive FIFO. This bit is cleared when the status register is read.      0 - No parity error has occurred      1 - Parity error has occurred

            7
            1
            true
            read-only
            
              0
              0
            
            false
          
        
      
    
  
  
    
      
        xilinx_veriloginstantiationtemplate
        Verilog Instantiation Template
        verilogSource:vivado.xilinx.com:synthesis.template
        verilog
        
          xilinx_veriloginstantiationtemplate_view_fileset
        
        
          
            GENtimestamp
            Tue Jul 28 08:34:41 UTC 2020
          
          
            outputProductCRC
            7:b1e5e5aa
          
        
      
      
        xilinx_vhdlsynthesis
        VHDL Synthesis
        vhdlSource:vivado.xilinx.com:synthesis
        vhdl
        
          xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset
        
        
          xilinx_vhdlsynthesis_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset
        
        
          xilinx_vhdlsynthesis_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset
        
        
          xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset
        
        
          xilinx_vhdlsynthesis_view_fileset
        
        
          
            GENtimestamp
            Tue Jul 28 08:34:41 UTC 2020
          
          
            outputProductCRC
            7:b1e5e5aa
          
        
      
      
        xilinx_vhdlsynthesiswrapper
        VHDL Synthesis Wrapper
        vhdlSource:vivado.xilinx.com:synthesis.wrapper
        vhdl
        
          xilinx_vhdlsynthesiswrapper_view_fileset
        
        
          
            GENtimestamp
            Tue Jul 28 08:34:41 UTC 2020
          
          
            outputProductCRC
            7:b1e5e5aa
          
        
      
      
        xilinx_vhdlbehavioralsimulation
        VHDL Simulation
        vhdlSource:vivado.xilinx.com:simulation
        vhdl
        
          xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset
        
        
          xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset
        
        
          xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset
        
        
          xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset
        
        
          xilinx_vhdlbehavioralsimulation_view_fileset
        
        
          
            GENtimestamp
            Tue Jul 28 08:34:41 UTC 2020
          
          
            outputProductCRC
            7:7c7dc27c
          
        
      
      
        xilinx_vhdlsimulationwrapper
        VHDL Simulation Wrapper
        vhdlSource:vivado.xilinx.com:simulation.wrapper
        vhdl
        
          xilinx_vhdlsimulationwrapper_view_fileset
        
        
          
            GENtimestamp
            Tue Jul 28 08:34:41 UTC 2020
          
          
            outputProductCRC
            7:7c7dc27c
          
        
      
      
        xilinx_implementation
        Implementation
        :vivado.xilinx.com:implementation
        
          xilinx_implementation_view_fileset
        
        
          
            GENtimestamp
            Tue Jul 28 08:34:41 UTC 2020
          
          
            outputProductCRC
            7:b1e5e5aa
          
        
      
      
        xilinx_versioninformation
        Version Information
        :vivado.xilinx.com:docs.versioninfo
        
          xilinx_versioninformation_view_fileset
        
        
          
            GENtimestamp
            Tue Jul 28 08:34:41 UTC 2020
          
          
            outputProductCRC
            7:b1e5e5aa
          
        
      
      
        xilinx_externalfiles
        External Files
        :vivado.xilinx.com:external.files
        
          xilinx_externalfiles_view_fileset
        
        
          
            GENtimestamp
            Tue Jul 28 08:34:42 UTC 2020
          
          
            outputProductCRC
            7:b1e5e5aa
          
        
      
    
    
      
        s_axi_aclk
        
          in
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_aresetn
        
          in
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            1
          
        
      
      
        interrupt
        
          out
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_awaddr
        
          in
          
            3
            0
          
          
            
              std_logic_vector
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_awvalid
        
          in
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_awready
        
          out
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_wdata
        
          in
          
            31
            0
          
          
            
              std_logic_vector
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_wstrb
        
          in
          
            3
            0
          
          
            
              std_logic_vector
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_wvalid
        
          in
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_wready
        
          out
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_bresp
        
          out
          
            1
            0
          
          
            
              std_logic_vector
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_bvalid
        
          out
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_bready
        
          in
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_araddr
        
          in
          
            3
            0
          
          
            
              std_logic_vector
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_arvalid
        
          in
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        s_axi_arready
        
          out
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_rdata
        
          out
          
            31
            0
          
          
            
              std_logic_vector
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_rresp
        
          out
          
            1
            0
          
          
            
              std_logic_vector
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_rvalid
        
          out
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
      
        s_axi_rready
        
          in
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        rx
        
          in
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
          
            0
          
        
      
      
        tx
        
          out
          
            
              std_logic
              xilinx_vhdlsynthesis
              xilinx_vhdlbehavioralsimulation
            
          
        
      
    
    
      
        C_FAMILY
        kintex7
      
      
        C_S_AXI_ACLK_FREQ_HZ
        AXI CLK Frequency
        100000000
      
      
        C_S_AXI_ADDR_WIDTH
        C S Axi Addr Width
        4
      
      
        C_S_AXI_DATA_WIDTH
        Axi Data Width
        32
      
      
        C_BAUDRATE
        Baudrate
        38400
      
      
        C_DATA_BITS
        Data Bits
        8
      
      
        C_USE_PARITY
        Use Parity
        0
      
      
        C_ODD_PARITY
        Odd Parity
        0
      
    
  
  
    
      choice_list_0739ee39
      Custom
      rs232_uart
    
    
      choice_list_3bbfa9f1
      No_Parity
      Odd
      Even
    
    
      choice_list_d4196e9f
      110
      300
      1200
      2400
      4800
      9600
      19200
      38400
      57600
      115200
      128000
      230400
    
  
  
    
      xilinx_veriloginstantiationtemplate_view_fileset
      
        axi_uartlite_module_sim.vho
        vhdlTemplate
      
      
        axi_uartlite_module_sim.veo
        verilogTemplate
      
    
    
      xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset
      
        hdl/axi_lite_ipif_v3_0_vh_rfs.vhd
        vhdlSource
        axi_lite_ipif_v3_0_4
      
      
        
          
            
          
        
      
    
    
      xilinx_vhdlsynthesis_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset
      
        hdl/lib_pkg_v1_0_rfs.vhd
        vhdlSource
        lib_pkg_v1_0_2
      
      
        
          
            
          
        
      
    
    
      xilinx_vhdlsynthesis_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset
      
        hdl/lib_srl_fifo_v1_0_rfs.vhd
        vhdlSource
        lib_srl_fifo_v1_0_2
      
      
        
          
            
          
        
      
    
    
      xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset
      
        hdl/lib_cdc_v1_0_rfs.vhd
        vhdlSource
        lib_cdc_v1_0_2
      
      
        
          
            
          
        
      
    
    
      xilinx_vhdlsynthesis_view_fileset
      
        axi_uartlite_module_sim_ooc.xdc
        xdc
        USED_IN_implementation
        USED_IN_out_of_context
        USED_IN_synthesis
      
      
        axi_uartlite_module_sim.xdc
        xdc
      
      
        hdl/axi_uartlite_v2_0_vh_rfs.vhd
        vhdlSource
        axi_uartlite_v2_0_19
      
    
    
      xilinx_vhdlsynthesiswrapper_view_fileset
      
        synth/axi_uartlite_module_sim.vhd
        vhdlSource
        xil_defaultlib
      
    
    
      xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset
      
        hdl/axi_lite_ipif_v3_0_vh_rfs.vhd
        vhdlSource
        USED_IN_ipstatic
        axi_lite_ipif_v3_0_4
      
      
        
          
            
          
        
      
    
    
      xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset
      
        hdl/lib_pkg_v1_0_rfs.vhd
        vhdlSource
        USED_IN_ipstatic
        lib_pkg_v1_0_2
      
      
        
          
            
          
        
      
    
    
      xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset
      
        hdl/lib_srl_fifo_v1_0_rfs.vhd
        vhdlSource
        USED_IN_ipstatic
        lib_srl_fifo_v1_0_2
      
      
        
          
            
          
        
      
    
    
      xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset
      
        hdl/lib_cdc_v1_0_rfs.vhd
        vhdlSource
        USED_IN_ipstatic
        lib_cdc_v1_0_2
      
      
        
          
            
          
        
      
    
    
      xilinx_vhdlbehavioralsimulation_view_fileset
      
        hdl/axi_uartlite_v2_0_vh_rfs.vhd
        vhdlSource
        USED_IN_ipstatic
        axi_uartlite_v2_0_19
      
    
    
      xilinx_vhdlsimulationwrapper_view_fileset
      
        sim/axi_uartlite_module_sim.vhd
        vhdlSource
        xil_defaultlib
      
    
    
      xilinx_implementation_view_fileset
      
        axi_uartlite_module_sim_board.xdc
        xdc
        USED_IN_board
        USED_IN_implementation
        USED_IN_synthesis
      
    
    
      xilinx_versioninformation_view_fileset
      
        doc/axi_uartlite_v2_0_changelog.txt
        text
      
    
    
      xilinx_externalfiles_view_fileset
      
        axi_uartlite_module_sim_sim_netlist.v
        verilogSource
        USED_IN_simulation
        USED_IN_single_language
        xil_defaultlib
      
      
        axi_uartlite_module_sim.dcp
        dcp
        USED_IN_implementation
        USED_IN_synthesis
        xil_defaultlib
      
      
        axi_uartlite_module_sim_sim_netlist.vhdl
        vhdlSource
        USED_IN_simulation
        USED_IN_single_language
        xil_defaultlib
      
      
        axi_uartlite_module_sim_stub.v
        verilogSource
        USED_IN_synth_blackbox_stub
        xil_defaultlib
      
      
        axi_uartlite_module_sim_stub.vhdl
        vhdlSource
        USED_IN_synth_blackbox_stub
        xil_defaultlib
      
    
  
  Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI Interface
  
    
      C_DATA_BITS
      Data Bits
      The number of data bits in the serial frame.
      8
    
    
      C_BAUDRATE
      Baudrate
      Baud rate of the AXI UART Lite in bits per second.
      38400
    
    
      C_S_AXI_ACLK_FREQ_HZ
      AXI CLK Frequency
      AXI4-Lite clock frequency range should be in between 10 to 300MHz.
      100000000
    
    
      C_S_AXI_ACLK_FREQ_HZ_d
      AXI CLK Frequency
      AXI4-Lite clock frequency range should be in between 10 to 300MHz.
      100
    
    
      Component_Name
      axi_uartlite_module_sim
    
    
      PARITY
      Parity
      No_Parity
    
    
      C_USE_PARITY
      Use Parity
      0
    
    
      C_ODD_PARITY
      Odd Parity
      0
    
    
      USE_BOARD_FLOW
      Generate Board based IO Constraints
      false
    
    
      UARTLITE_BOARD_INTERFACE
      Custom
    
  
  
    
      AXI Uartlite
      19
      
        
      
    
    
      2017.4
      
      
      
      
      
      
    
  


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Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [axi_uartlite_module_sim/] [axi_uartlite_module_sim.xml] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	vv_gulyaev
2
3			`xilinx.com`
4			`customized_ip`
5			`axi_uartlite_module_sim`
6			`1.0`
7
8
9			`S_AXI`
10			`S_AXI`
11
12
13
14
15
16
17			`ARADDR`
18
19
20			`s_axi_araddr`
21
22
23
24
25			`ARREADY`
26
27
28			`s_axi_arready`
29
30
31
32
33			`ARVALID`
34
35
36			`s_axi_arvalid`
37
38
39
40
41			`AWADDR`
42
43
44			`s_axi_awaddr`
45
46
47
48
49			`AWREADY`
50
51
52			`s_axi_awready`
53
54
55
56
57			`AWVALID`
58
59
60			`s_axi_awvalid`
61
62
63
64
65			`BREADY`
66
67
68			`s_axi_bready`
69
70
71
72
73			`BRESP`
74
75
76			`s_axi_bresp`
77
78
79
80
81			`BVALID`
82
83
84			`s_axi_bvalid`
85
86
87
88
89			`RDATA`
90
91
92			`s_axi_rdata`
93
94
95
96
97			`RREADY`
98
99
100			`s_axi_rready`
101
102
103
104
105			`RRESP`
106
107
108			`s_axi_rresp`
109
110
111
112
113			`RVALID`
114
115
116			`s_axi_rvalid`
117
118
119
120
121			`WDATA`
122
123
124			`s_axi_wdata`
125
126
127
128
129			`WREADY`
130
131
132			`s_axi_wready`
133
134
135
136
137			`WSTRB`
138
139
140			`s_axi_wstrb`
141
142
143
144
145			`WVALID`
146
147
148			`s_axi_wvalid`
149
150
151
152
153
154			`DATA_WIDTH`
155			`32`
156
157
158			`none`
159
160
161
162
163			`PROTOCOL`
164			`AXI4LITE`
165
166
167			`none`
168
169
170
171
172			`FREQ_HZ`
173			`100000000`
174
175
176			`none`
177
178
179
180
181			`ID_WIDTH`
182			`0`
183
184
185			`none`
186
187
188
189
190			`ADDR_WIDTH`
191			`4`
192
193
194			`none`
195
196
197
198
199			`AWUSER_WIDTH`
200			`0`
201
202
203			`none`
204
205
206
207
208			`ARUSER_WIDTH`
209			`0`
210
211
212			`none`
213
214
215
216
217			`WUSER_WIDTH`
218			`0`
219
220
221			`none`
222
223
224
225
226			`RUSER_WIDTH`
227			`0`
228
229
230			`none`
231
232
233
234
235			`BUSER_WIDTH`
236			`0`
237
238
239			`none`
240
241
242
243
244			`READ_WRITE_MODE`
245			`READ_WRITE`
246
247
248			`none`
249
250
251
252
253			`HAS_BURST`
254			`0`
255
256
257			`none`
258
259
260
261
262			`HAS_LOCK`
263			`0`
264
265
266			`none`
267
268
269
270
271			`HAS_PROT`
272			`0`
273
274
275			`none`
276
277
278
279
280			`HAS_CACHE`
281			`0`
282
283
284			`none`
285
286
287
288
289			`HAS_QOS`
290			`0`
291
292
293			`none`
294
295
296
297
298			`HAS_REGION`
299			`0`
300
301
302			`none`
303
304
305
306
307			`HAS_WSTRB`
308			`1`
309
310
311			`none`
312
313
314
315
316			`HAS_BRESP`
317			`1`
318
319
320			`none`
321
322
323
324
325			`HAS_RRESP`
326			`1`
327
328
329			`none`
330
331
332
333
334			`SUPPORTS_NARROW_BURST`
335			`0`
336
337
338			`none`
339
340
341
342
343			`NUM_READ_OUTSTANDING`
344			`1`
345
346
347			`none`
348
349
350
351
352			`NUM_WRITE_OUTSTANDING`
353			`1`
354
355
356			`none`
357
358
359
360
361			`MAX_BURST_LENGTH`
362			`1`
363
364
365			`none`
366
367
368
369
370			`PHASE`
371			`0.000`
372
373
374			`none`
375
376
377
378
379			`CLK_DOMAIN`
380
381
382
383			`none`
384
385
386
387
388			`NUM_READ_THREADS`
389			`1`
390
391
392			`none`
393
394
395
396
397			`NUM_WRITE_THREADS`
398			`1`
399
400
401			`none`
402
403
404
405
406			`RUSER_BITS_PER_BYTE`
407			`0`
408
409
410			`none`
411
412
413
414
415			`WUSER_BITS_PER_BYTE`
416			`0`
417
418
419			`none`
420
421
422
423
424
425
426			`ACLK`
427			`aclk`
428
429
430
431
432
433
434			`CLK`
435
436
437			`s_axi_aclk`
438
439
440
441
442
443			`ASSOCIATED_BUSIF`
444			`S_AXI`
445
446
447			`ASSOCIATED_RESET`
448			`s_axi_aresetn`
449
450
451			`FREQ_HZ`
452			`100000000`
453
454
455			`none`
456
457
458
459
460			`PHASE`
461			`0.000`
462
463
464			`none`
465
466
467
468
469			`CLK_DOMAIN`
470
471
472
473			`none`
474
475
476
477
478
479
480			`ARESETN`
481			`aresetn`
482
483
484
485
486
487
488			`RST`
489
490
491			`s_axi_aresetn`
492
493
494
495
496
497			`POLARITY`
498			`ACTIVE_LOW`
499
500
501
502
503			`INTERRUPT`
504			`interrupt`
505
506
507
508
509
510
511			`INTERRUPT`
512
513
514			`interrupt`
515
516
517
518
519
520			`SENSITIVITY`
521			`EDGE_RISING`
522
523
524			`PortWidth`
525			`1`
526
527
528			`none`
529
530
531
532
533
534
535			`UART`
536			`uart`
537
538
539
540
541
542
543			`RxD`
544
545
546			`rx`
547
548
549
550
551			`TxD`
552
553
554			`tx`
555
556
557
558
559
560			`BOARD.ASSOCIATED_PARAM`
561			`UARTLITE_BOARD_INTERFACE`
562
563
564
565			`required`
566
567
568
569
570
571
572
573
574
575			`S_AXI`
576			`S_AXI_MEM`
577			`Memory Map for S_AXI`
578
579			`Reg`
580			`Reg`
581			`Register Block`
582			`0`
583			`4096`
584			`32`
585			`register`
586			`read-write`
587
588			`RX_FIFO`
589			`RX FIFO`
590			`Receive data FIFO`
591			`0x0`
592			`32`
593			`true`
594			`read-only`
595
596			`0x0`
597
598
599			`RX_DATA`
600			`Receive Data`
601			`UART Receive Data`
602
603			`0`
604			`8`
605			`true`
606			`read-only`
607
608			`0`
609			`0`
610
611			`false`
612
613
614
615			`TX_FIFO`
616			`TX FIFO`
617			`Transmit data FIFO`
618			`0x4`
619			`32`
620			`true`
621			`write-only`
622
623			`0x0`
624
625
626			`TX_DATA`
627			`Transmit Data`
628			`UART Transmit Data`
629
630			`0`
631			`8`
632			`true`
633			`write-only`
634
635			`0`
636			`0`
637
638			`false`
639
640
641
642			`CTRL_REG`
643			`Control Register`
644			`UART Lite control register`
645			`0xC`
646			`32`
647			`true`
648			`write-only`
649
650			`0x0`
651
652
653			`RST_TXFIFO`
654			`Reset Tx FIFO`
655			`Reset/clear the transmit FIFO`
656			`Writing a 1 to this bit position clears the transmit FIFO`
657
658			`1 - Clear the transmit FIFO`
659
660			`0`
661			`1`
662			`true`
663			`write-only`
664
665			`0`
666			`0`
667
668			`false`
669
670
671			`RST_RXFIFO`
672			`Reset Rx FIFO`
673			`Reset/clear the receive FIFO`
674			`Writing a 1 to this bit position clears the receive FIFO`
675
676			`1 - Clear the receive FIFO`
677
678			`1`
679			`1`
680			`true`
681			`write-only`
682
683			`0`
684			`0`
685
686			`false`
687
688
689			`Enable_Intr`
690			`Enable interrupt`
691			`Enable interrupt for the AXI UART Lite`
692
693			`1 - Enable interrupt signal`
694
695			`4`
696			`1`
697			`true`
698			`write-only`
699
700			`0`
701			`0`
702
703			`false`
704
705
706
707			`STAT_REG`
708			`Status Register`
709			`UART Lite status register`
710			`0x8`
711			`32`
712			`true`
713			`read-only`
714
715			`0x0`
716
717
718			`RX_FIFO_Valid_Data`
719			`RX FIFO Valid Data`
720			`Indicates if the receive FIFO has data.`
721
722			`1 - Receive FIFO has data`
723
724			`0`
725			`1`
726			`true`
727			`read-only`
728
729			`0`
730			`0`
731
732			`false`
733
734
735			`RX_FIFO_Full`
736			`RX FIFO Full`
737			`Indicates if the receive FIFO is full.`
738
739			`1 - Receive FIFO is full`
740
741			`1`
742			`1`
743			`true`
744			`read-only`
745
746			`0`
747			`0`
748
749			`false`
750
751
752			`TX_FIFO_Empty`
753			`TX FIFO Empty`
754			`Indicates if the transmit FIFO is empty.`
755
756			`1 - Transmit FIFO is empty`
757
758			`2`
759			`1`
760			`true`
761			`read-only`
762
763			`0`
764			`0`
765
766			`false`
767
768
769			`TX_FIFO_Full`
770			`TX FIFO Full`
771			`Indicates if the transmit FIFO is full.`
772
773			`1 - Transmit FIFO is full`
774
775			`3`
776			`1`
777			`true`
778			`read-only`
779
780			`0`
781			`0`
782
783			`false`
784
785
786			`Intr_Enabled`
787			`Interrupt Enabled`
788			`Indicates that interrupts is enabled.`
789
790			`1 - Interrupt is enabled`
791
792			`4`
793			`1`
794			`true`
795			`read-only`
796
797			`0`
798			`0`
799
800			`false`
801
802
803			`Overrun_Error`
804			`Overrun Error`
805			`Indicates that a overrun error has occurred after the last time the status register was read. Overrun is when a new character has been received but the receive FIFO is full. The received character is ignored and not written into the receive FIFO. This bit is cleared when the status register is read. 0 - No overrun error has occurred 1 - Overrun error has occurred`
806
807			`5`
808			`1`
809			`true`
810			`read-only`
811
812			`0`
813			`0`
814
815			`false`
816
817
818			`Frame_Error`
819			`Frame Error`
820			`Indicates that a frame error has occurred after the last time the status register was read. Frame error is defined as detection of a stop bit with the value 0. The receive character is ignored and not written to the receive FIFO. This bit is cleared when the status register is read. 0 - No frame error has occurred 1 - Frame error has occurred`
821
822			`6`
823			`1`
824			`true`
825			`read-only`
826
827			`0`
828			`0`
829
830			`false`
831
832
833			`Parity_Error`
834			`Parity Error`
835			`Indicates that a parity error has occurred after the last time the status register was read. If the UART is configured without any parity handling, this bit is always 0. The received character is written into the receive FIFO. This bit is cleared when the status register is read. 0 - No parity error has occurred 1 - Parity error has occurred`
836
837			`7`
838			`1`
839			`true`
840			`read-only`
841
842			`0`
843			`0`
844
845			`false`
846
847
848
849
850
851
852
853
854			`xilinx_veriloginstantiationtemplate`
855			`Verilog Instantiation Template`
856			`verilogSource:vivado.xilinx.com:synthesis.template`
857			`verilog`
858
859			`xilinx_veriloginstantiationtemplate_view_fileset`
860
861
862
863			`GENtimestamp`
864			`Tue Jul 28 08:34:41 UTC 2020`
865
866
867			`outputProductCRC`
868			`7:b1e5e5aa`
869
870
871
872
873			`xilinx_vhdlsynthesis`
874			`VHDL Synthesis`
875			`vhdlSource:vivado.xilinx.com:synthesis`
876			`vhdl`
877
878			`xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset`
879
880
881			`xilinx_vhdlsynthesis_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset`
882
883
884			`xilinx_vhdlsynthesis_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset`
885
886
887			`xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset`
888
889
890			`xilinx_vhdlsynthesis_view_fileset`
891
892
893
894			`GENtimestamp`
895			`Tue Jul 28 08:34:41 UTC 2020`
896
897
898			`outputProductCRC`
899			`7:b1e5e5aa`
900
901
902
903
904			`xilinx_vhdlsynthesiswrapper`
905			`VHDL Synthesis Wrapper`
906			`vhdlSource:vivado.xilinx.com:synthesis.wrapper`
907			`vhdl`
908
909			`xilinx_vhdlsynthesiswrapper_view_fileset`
910
911
912
913			`GENtimestamp`
914			`Tue Jul 28 08:34:41 UTC 2020`
915
916
917			`outputProductCRC`
918			`7:b1e5e5aa`
919
920
921
922
923			`xilinx_vhdlbehavioralsimulation`
924			`VHDL Simulation`
925			`vhdlSource:vivado.xilinx.com:simulation`
926			`vhdl`
927
928			`xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset`
929
930
931			`xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset`
932
933
934			`xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset`
935
936
937			`xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset`
938
939
940			`xilinx_vhdlbehavioralsimulation_view_fileset`
941
942
943
944			`GENtimestamp`
945			`Tue Jul 28 08:34:41 UTC 2020`
946
947
948			`outputProductCRC`
949			`7:7c7dc27c`
950
951
952
953
954			`xilinx_vhdlsimulationwrapper`
955			`VHDL Simulation Wrapper`
956			`vhdlSource:vivado.xilinx.com:simulation.wrapper`
957			`vhdl`
958
959			`xilinx_vhdlsimulationwrapper_view_fileset`
960
961
962
963			`GENtimestamp`
964			`Tue Jul 28 08:34:41 UTC 2020`
965
966
967			`outputProductCRC`
968			`7:7c7dc27c`
969
970
971
972
973			`xilinx_implementation`
974			`Implementation`
975			`:vivado.xilinx.com:implementation`
976
977			`xilinx_implementation_view_fileset`
978
979
980
981			`GENtimestamp`
982			`Tue Jul 28 08:34:41 UTC 2020`
983
984
985			`outputProductCRC`
986			`7:b1e5e5aa`
987
988
989
990
991			`xilinx_versioninformation`
992			`Version Information`
993			`:vivado.xilinx.com:docs.versioninfo`
994
995			`xilinx_versioninformation_view_fileset`
996
997
998
999			`GENtimestamp`
1000			`Tue Jul 28 08:34:41 UTC 2020`
1001
1002
1003			`outputProductCRC`
1004			`7:b1e5e5aa`
1005
1006
1007
1008
1009			`xilinx_externalfiles`
1010			`External Files`
1011			`:vivado.xilinx.com:external.files`
1012
1013			`xilinx_externalfiles_view_fileset`
1014
1015
1016
1017			`GENtimestamp`
1018			`Tue Jul 28 08:34:42 UTC 2020`
1019
1020
1021			`outputProductCRC`
1022			`7:b1e5e5aa`
1023
1024
1025
1026
1027
1028
1029			`s_axi_aclk`
1030
1031			`in`
1032
1033
1034			`std_logic`
1035			`xilinx_vhdlsynthesis`
1036			`xilinx_vhdlbehavioralsimulation`
1037
1038
1039
1040			`0`
1041
1042
1043
1044
1045			`s_axi_aresetn`
1046
1047			`in`
1048
1049
1050			`std_logic`
1051			`xilinx_vhdlsynthesis`
1052			`xilinx_vhdlbehavioralsimulation`
1053
1054
1055
1056			`1`
1057
1058
1059
1060
1061			`interrupt`
1062
1063			`out`
1064
1065
1066			`std_logic`
1067			`xilinx_vhdlsynthesis`
1068			`xilinx_vhdlbehavioralsimulation`
1069
1070
1071
1072
1073
1074			`s_axi_awaddr`
1075
1076			`in`
1077
1078			`3`
1079			`0`
1080
1081
1082
1083			`std_logic_vector`
1084			`xilinx_vhdlsynthesis`
1085			`xilinx_vhdlbehavioralsimulation`
1086
1087
1088
1089			`0`
1090
1091
1092
1093
1094			`s_axi_awvalid`
1095
1096			`in`
1097
1098
1099			`std_logic`
1100			`xilinx_vhdlsynthesis`
1101			`xilinx_vhdlbehavioralsimulation`
1102
1103
1104
1105			`0`
1106
1107
1108
1109
1110			`s_axi_awready`
1111
1112			`out`
1113
1114
1115			`std_logic`
1116			`xilinx_vhdlsynthesis`
1117			`xilinx_vhdlbehavioralsimulation`
1118
1119
1120
1121
1122
1123			`s_axi_wdata`
1124
1125			`in`
1126
1127			`31`
1128			`0`
1129
1130
1131
1132			`std_logic_vector`
1133			`xilinx_vhdlsynthesis`
1134			`xilinx_vhdlbehavioralsimulation`
1135
1136
1137
1138			`0`
1139
1140
1141
1142
1143			`s_axi_wstrb`
1144
1145			`in`
1146
1147			`3`
1148			`0`
1149
1150
1151
1152			`std_logic_vector`
1153			`xilinx_vhdlsynthesis`
1154			`xilinx_vhdlbehavioralsimulation`
1155
1156
1157
1158			`0`
1159
1160
1161
1162
1163			`s_axi_wvalid`
1164
1165			`in`
1166
1167
1168			`std_logic`
1169			`xilinx_vhdlsynthesis`
1170			`xilinx_vhdlbehavioralsimulation`
1171
1172
1173
1174			`0`
1175
1176
1177
1178
1179			`s_axi_wready`
1180
1181			`out`
1182
1183
1184			`std_logic`
1185			`xilinx_vhdlsynthesis`
1186			`xilinx_vhdlbehavioralsimulation`
1187
1188
1189
1190
1191
1192			`s_axi_bresp`
1193
1194			`out`
1195
1196			`1`
1197			`0`
1198
1199
1200
1201			`std_logic_vector`
1202			`xilinx_vhdlsynthesis`
1203			`xilinx_vhdlbehavioralsimulation`
1204
1205
1206
1207
1208
1209			`s_axi_bvalid`
1210
1211			`out`
1212
1213
1214			`std_logic`
1215			`xilinx_vhdlsynthesis`
1216			`xilinx_vhdlbehavioralsimulation`
1217
1218
1219
1220
1221
1222			`s_axi_bready`
1223
1224			`in`
1225
1226
1227			`std_logic`
1228			`xilinx_vhdlsynthesis`
1229			`xilinx_vhdlbehavioralsimulation`
1230
1231
1232
1233			`0`
1234
1235
1236
1237
1238			`s_axi_araddr`
1239
1240			`in`
1241
1242			`3`
1243			`0`
1244
1245
1246
1247			`std_logic_vector`
1248			`xilinx_vhdlsynthesis`
1249			`xilinx_vhdlbehavioralsimulation`
1250
1251
1252
1253			`0`
1254
1255
1256
1257
1258			`s_axi_arvalid`
1259
1260			`in`
1261
1262
1263			`std_logic`
1264			`xilinx_vhdlsynthesis`
1265			`xilinx_vhdlbehavioralsimulation`
1266
1267
1268
1269			`0`
1270
1271
1272
1273
1274			`s_axi_arready`
1275
1276			`out`
1277
1278
1279			`std_logic`
1280			`xilinx_vhdlsynthesis`
1281			`xilinx_vhdlbehavioralsimulation`
1282
1283
1284
1285
1286
1287			`s_axi_rdata`
1288
1289			`out`
1290
1291			`31`
1292			`0`
1293
1294
1295
1296			`std_logic_vector`
1297			`xilinx_vhdlsynthesis`
1298			`xilinx_vhdlbehavioralsimulation`
1299
1300
1301
1302
1303
1304			`s_axi_rresp`
1305
1306			`out`
1307
1308			`1`
1309			`0`
1310
1311
1312
1313			`std_logic_vector`
1314			`xilinx_vhdlsynthesis`
1315			`xilinx_vhdlbehavioralsimulation`
1316
1317
1318
1319
1320
1321			`s_axi_rvalid`
1322
1323			`out`
1324
1325
1326			`std_logic`
1327			`xilinx_vhdlsynthesis`
1328			`xilinx_vhdlbehavioralsimulation`
1329
1330
1331
1332
1333
1334			`s_axi_rready`
1335
1336			`in`
1337
1338
1339			`std_logic`
1340			`xilinx_vhdlsynthesis`
1341			`xilinx_vhdlbehavioralsimulation`
1342
1343
1344
1345			`0`
1346
1347
1348
1349
1350			`rx`
1351
1352			`in`
1353
1354
1355			`std_logic`
1356			`xilinx_vhdlsynthesis`
1357			`xilinx_vhdlbehavioralsimulation`
1358
1359
1360
1361			`0`
1362
1363
1364
1365
1366			`tx`
1367
1368			`out`
1369
1370
1371			`std_logic`
1372			`xilinx_vhdlsynthesis`
1373			`xilinx_vhdlbehavioralsimulation`
1374
1375
1376
1377
1378
1379
1380
1381			`C_FAMILY`
1382			`kintex7`
1383
1384
1385			`C_S_AXI_ACLK_FREQ_HZ`
1386			`AXI CLK Frequency`
1387			`100000000`
1388
1389
1390			`C_S_AXI_ADDR_WIDTH`
1391			`C S Axi Addr Width`
1392			`4`
1393
1394
1395			`C_S_AXI_DATA_WIDTH`
1396			`Axi Data Width`
1397			`32`
1398
1399
1400			`C_BAUDRATE`
1401			`Baudrate`
1402			`38400`
1403
1404
1405			`C_DATA_BITS`
1406			`Data Bits`
1407			`8`
1408
1409
1410			`C_USE_PARITY`
1411			`Use Parity`
1412			`0`
1413
1414
1415			`C_ODD_PARITY`
1416			`Odd Parity`
1417			`0`
1418
1419
1420
1421
1422
1423			`choice_list_0739ee39`
1424			`Custom`
1425			`rs232_uart`
1426
1427
1428			`choice_list_3bbfa9f1`
1429			`No_Parity`
1430			`Odd`
1431			`Even`
1432
1433
1434			`choice_list_d4196e9f`
1435			`110`
1436			`300`
1437			`1200`
1438			`2400`
1439			`4800`
1440			`9600`
1441			`19200`
1442			`38400`
1443			`57600`
1444			`115200`
1445			`128000`
1446			`230400`
1447
1448
1449
1450
1451			`xilinx_veriloginstantiationtemplate_view_fileset`
1452
1453			`axi_uartlite_module_sim.vho`
1454			`vhdlTemplate`
1455
1456
1457			`axi_uartlite_module_sim.veo`
1458			`verilogTemplate`
1459
1460
1461
1462			`xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset`
1463
1464			`hdl/axi_lite_ipif_v3_0_vh_rfs.vhd`
1465			`vhdlSource`
1466			`axi_lite_ipif_v3_0_4`
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477			`xilinx_vhdlsynthesis_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset`
1478
1479			`hdl/lib_pkg_v1_0_rfs.vhd`
1480			`vhdlSource`
1481			`lib_pkg_v1_0_2`
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492			`xilinx_vhdlsynthesis_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset`
1493
1494			`hdl/lib_srl_fifo_v1_0_rfs.vhd`
1495			`vhdlSource`
1496			`lib_srl_fifo_v1_0_2`
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507			`xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset`
1508
1509			`hdl/lib_cdc_v1_0_rfs.vhd`
1510			`vhdlSource`
1511			`lib_cdc_v1_0_2`
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522			`xilinx_vhdlsynthesis_view_fileset`
1523
1524			`axi_uartlite_module_sim_ooc.xdc`
1525			`xdc`
1526			`USED_IN_implementation`
1527			`USED_IN_out_of_context`
1528			`USED_IN_synthesis`
1529
1530
1531			`axi_uartlite_module_sim.xdc`
1532			`xdc`
1533
1534
1535			`hdl/axi_uartlite_v2_0_vh_rfs.vhd`
1536			`vhdlSource`
1537			`axi_uartlite_v2_0_19`
1538
1539
1540
1541			`xilinx_vhdlsynthesiswrapper_view_fileset`
1542
1543			`synth/axi_uartlite_module_sim.vhd`
1544			`vhdlSource`
1545			`xil_defaultlib`
1546
1547
1548
1549			`xilinx_vhdlbehavioralsimulation_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset`
1550
1551			`hdl/axi_lite_ipif_v3_0_vh_rfs.vhd`
1552			`vhdlSource`
1553			`USED_IN_ipstatic`
1554			`axi_lite_ipif_v3_0_4`
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565			`xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset`
1566
1567			`hdl/lib_pkg_v1_0_rfs.vhd`
1568			`vhdlSource`
1569			`USED_IN_ipstatic`
1570			`lib_pkg_v1_0_2`
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581			`xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset`
1582
1583			`hdl/lib_srl_fifo_v1_0_rfs.vhd`
1584			`vhdlSource`
1585			`USED_IN_ipstatic`
1586			`lib_srl_fifo_v1_0_2`
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597			`xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset`
1598
1599			`hdl/lib_cdc_v1_0_rfs.vhd`
1600			`vhdlSource`
1601			`USED_IN_ipstatic`
1602			`lib_cdc_v1_0_2`
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613			`xilinx_vhdlbehavioralsimulation_view_fileset`
1614
1615			`hdl/axi_uartlite_v2_0_vh_rfs.vhd`
1616			`vhdlSource`
1617			`USED_IN_ipstatic`
1618			`axi_uartlite_v2_0_19`
1619
1620
1621
1622			`xilinx_vhdlsimulationwrapper_view_fileset`
1623
1624			`sim/axi_uartlite_module_sim.vhd`
1625			`vhdlSource`
1626			`xil_defaultlib`
1627
1628
1629
1630			`xilinx_implementation_view_fileset`
1631
1632			`axi_uartlite_module_sim_board.xdc`
1633			`xdc`
1634			`USED_IN_board`
1635			`USED_IN_implementation`
1636			`USED_IN_synthesis`
1637
1638
1639
1640			`xilinx_versioninformation_view_fileset`
1641
1642			`doc/axi_uartlite_v2_0_changelog.txt`
1643			`text`
1644
1645
1646
1647			`xilinx_externalfiles_view_fileset`
1648
1649			`axi_uartlite_module_sim_sim_netlist.v`
1650			`verilogSource`
1651			`USED_IN_simulation`
1652			`USED_IN_single_language`
1653			`xil_defaultlib`
1654
1655
1656			`axi_uartlite_module_sim.dcp`
1657			`dcp`
1658			`USED_IN_implementation`
1659			`USED_IN_synthesis`
1660			`xil_defaultlib`
1661
1662
1663			`axi_uartlite_module_sim_sim_netlist.vhdl`
1664			`vhdlSource`
1665			`USED_IN_simulation`
1666			`USED_IN_single_language`
1667			`xil_defaultlib`
1668
1669
1670			`axi_uartlite_module_sim_stub.v`
1671			`verilogSource`
1672			`USED_IN_synth_blackbox_stub`
1673			`xil_defaultlib`
1674
1675
1676			`axi_uartlite_module_sim_stub.vhdl`
1677			`vhdlSource`
1678			`USED_IN_synth_blackbox_stub`
1679			`xil_defaultlib`
1680
1681
1682
1683			`Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI Interface`
1684
1685
1686			`C_DATA_BITS`
1687			`Data Bits`
1688			`The number of data bits in the serial frame.`
1689			`8`
1690
1691
1692			`C_BAUDRATE`
1693			`Baudrate`
1694			`Baud rate of the AXI UART Lite in bits per second.`
1695			`38400`
1696
1697
1698			`C_S_AXI_ACLK_FREQ_HZ`
1699			`AXI CLK Frequency`
1700			`AXI4-Lite clock frequency range should be in between 10 to 300MHz.`
1701			`100000000`
1702
1703
1704			`C_S_AXI_ACLK_FREQ_HZ_d`
1705			`AXI CLK Frequency`
1706			`AXI4-Lite clock frequency range should be in between 10 to 300MHz.`
1707			`100`
1708
1709
1710			`Component_Name`
1711			`axi_uartlite_module_sim`
1712
1713
1714			`PARITY`
1715			`Parity`
1716			`No_Parity`
1717
1718
1719			`C_USE_PARITY`
1720			`Use Parity`
1721			`0`
1722
1723
1724			`C_ODD_PARITY`
1725			`Odd Parity`
1726			`0`
1727
1728
1729			`USE_BOARD_FLOW`
1730			`Generate Board based IO Constraints`
1731			`false`
1732
1733
1734			`UARTLITE_BOARD_INTERFACE`
1735			`Custom`
1736
1737
1738
1739
1740			`AXI Uartlite`
1741			`19`
1742
1743
1744
1745
1746
1747			`2017.4`
1748
1749
1750
1751
1752
1753
1754
1755
1756