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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [axi_uartlite_module_sim/] [axi_uartlite_module_sim_ooc.xdc] - Blame information for rev 2

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################################################################################
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# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
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#
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# This file contains confidential and proprietary information
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# of Xilinx, Inc. and is protected under U.S. and
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# international copyright and other intellectual property
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# laws.
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#
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# DISCLAIMER
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# This disclaimer is not a license and does not grant any
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# rights to the materials distributed herewith. Except as
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# otherwise provided in a valid license issued to you by
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# Xilinx, and to the maximum extent permitted by applicable
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# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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# by a third party) even if such damage or loss was
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# reasonably foreseeable or Xilinx had been advised of the
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# possibility of the same.
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#
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# CRITICAL APPLICATIONS
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# Xilinx products are not designed or intended to be fail-
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# safe, or for use in any application requiring fail-safe
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# performance, such as life-support or safety devices or
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# applications related to the deployment of airbags, or any
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# other applications that could lead to death, personal
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# Applications"). Customer assumes the sole risk and
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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# PART OF THIS FILE AT ALL TIMES.
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################################################################################
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# This XDC is used only for OOC mode of synthesis, implementation
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# User should update the correct clock period before proceeding further
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# This constraints file contains default clock frequencies to be used during
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# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
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# For best results the frequencies should be modified# to match the target
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# frequencies.
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# create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
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create_clock -name s_axi_clk -period 10.000 [get_ports s_axi_aclk]
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## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
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################################################################################

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