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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [axi_uartlite_module_sim/] [axi_uartlite_module_sim_sim_netlist.v] - Blame information for rev 2

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1 2 vv_gulyaev 
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
2 
// --------------------------------------------------------------------------------
3 
// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
4 
// Date        : Thu Jul 23 09:49:59 2020
5 
// Host        : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)
6 
// Command     : write_verilog -force -mode funcsim -rename_top axi_uartlite_module_sim -prefix
7 
//               axi_uartlite_module_sim_ axi_uartlite_module_sim_netlist.v
8 
// Design      : axi_uartlite_module
9 
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
10 
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
11 
// Device      : xc7k325tffg900-2
12 
// --------------------------------------------------------------------------------
13 
`timescale 1 ps / 1 ps
14 
 
15 
module axi_uartlite_module_sim_address_decoder
16 
   (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
17 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ,
18 
    enable_interrupts_reg,
19 
    reset_TX_FIFO,
20 
    reset_RX_FIFO,
21 
    D,
22 
    s_axi_awready,
23 
    s_axi_arready,
24 
    \s_axi_rdata_i_reg[7] ,
25 
    ip2bus_error,
26 
    \INFERRED_GEN.cnt_i_reg[2] ,
27 
    rx_Data_Present_Pre_reg,
28 
    FIFO_Full_reg,
29 
    bus2ip_rdce,
30 
    fifo_wr,
31 
    \INFERRED_GEN.cnt_i_reg[2]_0 ,
32 
    tx_Buffer_Empty_Pre_reg,
33 
    enable_interrupts_reg_0,
34 
    s_axi_rvalid_i_reg,
35 
    s_axi_bvalid_i_reg,
36 
    \s_axi_bresp_i_reg[1] ,
37 
    start2,
38 
    s_axi_aclk,
39 
    s_axi_wdata,
40 
    \state_reg[0] ,
41 
    Q,
42 
    s_axi_arvalid,
43 
    \state_reg[1] ,
44 
    s_axi_wvalid,
45 
    s_axi_aresetn,
46 
    \INFERRED_GEN.cnt_i_reg[4] ,
47 
    out,
48 
    rx_Buffer_Full,
49 
    \INFERRED_GEN.cnt_i_reg[4]_0 ,
50 
    tx_Buffer_Full,
51 
    enable_interrupts,
52 
    status_reg,
53 
    s_axi_rready,
54 
    s_axi_rvalid_i_reg_0,
55 
    s_axi_bready,
56 
    s_axi_bvalid_i_reg_0,
57 
    s_axi_bresp,
58 
    bus2ip_rnw_i,
59 
    \bus2ip_addr_i_reg[3] ,
60 
    \bus2ip_addr_i_reg[2] );
61 
  output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
62 
  output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ;
63 
  output enable_interrupts_reg;
64 
  output reset_TX_FIFO;
65 
  output reset_RX_FIFO;
66 
  output [1:0]D;
67 
  output s_axi_awready;
68 
  output s_axi_arready;
69 
  output [7:0]\s_axi_rdata_i_reg[7] ;
70 
  output ip2bus_error;
71 
  output \INFERRED_GEN.cnt_i_reg[2] ;
72 
  output rx_Data_Present_Pre_reg;
73 
  output FIFO_Full_reg;
74 
  output [0:0]bus2ip_rdce;
75 
  output fifo_wr;
76 
  output \INFERRED_GEN.cnt_i_reg[2]_0 ;
77 
  output tx_Buffer_Empty_Pre_reg;
78 
  output enable_interrupts_reg_0;
79 
  output s_axi_rvalid_i_reg;
80 
  output s_axi_bvalid_i_reg;
81 
  output \s_axi_bresp_i_reg[1] ;
82 
  input start2;
83 
  input s_axi_aclk;
84 
  input [2:0]s_axi_wdata;
85 
  input \state_reg[0] ;
86 
  input [1:0]Q;
87 
  input s_axi_arvalid;
88 
  input \state_reg[1] ;
89 
  input s_axi_wvalid;
90 
  input s_axi_aresetn;
91 
  input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
92 
  input [7:0]out;
93 
  input rx_Buffer_Full;
94 
  input [0:0]\INFERRED_GEN.cnt_i_reg[4]_0 ;
95 
  input tx_Buffer_Full;
96 
  input enable_interrupts;
97 
  input [1:0]status_reg;
98 
  input s_axi_rready;
99 
  input s_axi_rvalid_i_reg_0;
100 
  input s_axi_bready;
101 
  input s_axi_bvalid_i_reg_0;
102 
  input [0:0]s_axi_bresp;
103 
  input bus2ip_rnw_i;
104 
  input \bus2ip_addr_i_reg[3] ;
105 
  input \bus2ip_addr_i_reg[2] ;
106 
 
107 
  wire Bus_RNW_reg_i_1_n_0;
108 
  wire [1:0]D;
109 
  wire FIFO_Full_reg;
110 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
111 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ;
112 
  wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
113 
  wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
114 
  wire \INFERRED_GEN.cnt_i_reg[2] ;
115 
  wire \INFERRED_GEN.cnt_i_reg[2]_0 ;
116 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
117 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[4]_0 ;
118 
  wire [1:0]Q;
119 
  wire \bus2ip_addr_i_reg[2] ;
120 
  wire \bus2ip_addr_i_reg[3] ;
121 
  wire [0:0]bus2ip_rdce;
122 
  wire bus2ip_rnw_i;
123 
  wire ce_expnd_i_0;
124 
  wire ce_expnd_i_1;
125 
  wire ce_expnd_i_2;
126 
  wire ce_expnd_i_3;
127 
  wire cs_ce_clr;
128 
  wire enable_interrupts;
129 
  wire enable_interrupts_reg;
130 
  wire enable_interrupts_reg_0;
131 
  wire fifo_wr;
132 
  wire ip2bus_error;
133 
  wire [7:0]out;
134 
  wire reset_RX_FIFO;
135 
  wire reset_TX_FIFO;
136 
  wire rx_Buffer_Full;
137 
  wire rx_Data_Present_Pre_reg;
138 
  wire s_axi_aclk;
139 
  wire s_axi_aresetn;
140 
  wire s_axi_arready;
141 
  wire s_axi_arvalid;
142 
  wire s_axi_awready;
143 
  wire s_axi_bready;
144 
  wire [0:0]s_axi_bresp;
145 
  wire \s_axi_bresp_i_reg[1] ;
146 
  wire s_axi_bvalid_i_reg;
147 
  wire s_axi_bvalid_i_reg_0;
148 
  wire [7:0]\s_axi_rdata_i_reg[7] ;
149 
  wire s_axi_rready;
150 
  wire s_axi_rvalid_i_reg;
151 
  wire s_axi_rvalid_i_reg_0;
152 
  wire [2:0]s_axi_wdata;
153 
  wire s_axi_wvalid;
154 
  wire start2;
155 
  wire \state_reg[0] ;
156 
  wire \state_reg[1] ;
157 
  wire [1:0]status_reg;
158 
  wire tx_Buffer_Empty_Pre_reg;
159 
  wire tx_Buffer_Full;
160 
 
161 
  (* SOFT_HLUTNM = "soft_lutpair7" *)
162 
  LUT3 #(
163 
    .INIT(8'hB8))
164 
    Bus_RNW_reg_i_1
165 
       (.I0(bus2ip_rnw_i),
166 
        .I1(start2),
167 
        .I2(enable_interrupts_reg),
168 
        .O(Bus_RNW_reg_i_1_n_0));
169 
  FDRE Bus_RNW_reg_reg
170 
       (.C(s_axi_aclk),
171 
        .CE(1'b1),
172 
        .D(Bus_RNW_reg_i_1_n_0),
173 
        .Q(enable_interrupts_reg),
174 
        .R(1'b0));
175 
  FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
176 
       (.C(s_axi_aclk),
177 
        .CE(start2),
178 
        .D(ce_expnd_i_3),
179 
        .Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
180 
        .R(cs_ce_clr));
181 
  (* SOFT_HLUTNM = "soft_lutpair8" *)
182 
  LUT2 #(
183 
    .INIT(4'h2))
184 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
185 
       (.I0(\bus2ip_addr_i_reg[2] ),
186 
        .I1(\bus2ip_addr_i_reg[3] ),
187 
        .O(ce_expnd_i_2));
188 
  FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
189 
       (.C(s_axi_aclk),
190 
        .CE(start2),
191 
        .D(ce_expnd_i_2),
192 
        .Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
193 
        .R(cs_ce_clr));
194 
  FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
195 
       (.C(s_axi_aclk),
196 
        .CE(start2),
197 
        .D(ce_expnd_i_1),
198 
        .Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
199 
        .R(cs_ce_clr));
200 
  LUT5 #(
201 
    .INIT(32'hFFFEFFFF))
202 
    \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
203 
       (.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
204 
        .I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
205 
        .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
206 
        .I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
207 
        .I4(s_axi_aresetn),
208 
        .O(cs_ce_clr));
209 
  (* SOFT_HLUTNM = "soft_lutpair8" *)
210 
  LUT2 #(
211 
    .INIT(4'h8))
212 
    \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
213 
       (.I0(\bus2ip_addr_i_reg[3] ),
214 
        .I1(\bus2ip_addr_i_reg[2] ),
215 
        .O(ce_expnd_i_0));
216 
  FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
217 
       (.C(s_axi_aclk),
218 
        .CE(start2),
219 
        .D(ce_expnd_i_0),
220 
        .Q(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
221 
        .R(cs_ce_clr));
222 
  (* SOFT_HLUTNM = "soft_lutpair0" *)
223 
  LUT3 #(
224 
    .INIT(8'hF7))
225 
    \INFERRED_GEN.cnt_i[3]_i_2
226 
       (.I0(enable_interrupts_reg),
227 
        .I1(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
228 
        .I2(\INFERRED_GEN.cnt_i_reg[4] ),
229 
        .O(\INFERRED_GEN.cnt_i_reg[2] ));
230 
  (* SOFT_HLUTNM = "soft_lutpair1" *)
231 
  LUT2 #(
232 
    .INIT(4'h7))
233 
    \INFERRED_GEN.cnt_i[4]_i_3
234 
       (.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
235 
        .I1(enable_interrupts_reg),
236 
        .O(FIFO_Full_reg));
237 
  (* SOFT_HLUTNM = "soft_lutpair6" *)
238 
  LUT3 #(
239 
    .INIT(8'hFD))
240 
    \INFERRED_GEN.cnt_i[4]_i_5
241 
       (.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
242 
        .I1(enable_interrupts_reg),
243 
        .I2(tx_Buffer_Full),
244 
        .O(\INFERRED_GEN.cnt_i_reg[2]_0 ));
245 
  (* SOFT_HLUTNM = "soft_lutpair4" *)
246 
  LUT3 #(
247 
    .INIT(8'h10))
248 
    \INFERRED_GEN.data_reg[15][7]_srl16_i_1
249 
       (.I0(tx_Buffer_Full),
250 
        .I1(enable_interrupts_reg),
251 
        .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
252 
        .O(fifo_wr));
253 
  axi_uartlite_module_sim_pselect_f \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I
254 
       (.\bus2ip_addr_i_reg[2] (\bus2ip_addr_i_reg[2] ),
255 
        .\bus2ip_addr_i_reg[3] (\bus2ip_addr_i_reg[3] ),
256 
        .ce_expnd_i_3(ce_expnd_i_3));
257 
  axi_uartlite_module_sim_pselect_f__parameterized1 \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I
258 
       (.\bus2ip_addr_i_reg[2] (\bus2ip_addr_i_reg[2] ),
259 
        .\bus2ip_addr_i_reg[3] (\bus2ip_addr_i_reg[3] ),
260 
        .ce_expnd_i_1(ce_expnd_i_1));
261 
  (* SOFT_HLUTNM = "soft_lutpair2" *)
262 
  LUT2 #(
263 
    .INIT(4'h8))
264 
    clr_Status_i_1
265 
       (.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
266 
        .I1(enable_interrupts_reg),
267 
        .O(bus2ip_rdce));
268 
  (* SOFT_HLUTNM = "soft_lutpair5" *)
269 
  LUT4 #(
270 
    .INIT(16'hFB08))
271 
    enable_interrupts_i_1
272 
       (.I0(s_axi_wdata[2]),
273 
        .I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
274 
        .I2(enable_interrupts_reg),
275 
        .I3(enable_interrupts),
276 
        .O(enable_interrupts_reg_0));
277 
  (* SOFT_HLUTNM = "soft_lutpair7" *)
278 
  LUT3 #(
279 
    .INIT(8'h40))
280 
    reset_RX_FIFO_i_1
281 
       (.I0(enable_interrupts_reg),
282 
        .I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
283 
        .I2(s_axi_wdata[1]),
284 
        .O(reset_RX_FIFO));
285 
  (* SOFT_HLUTNM = "soft_lutpair5" *)
286 
  LUT3 #(
287 
    .INIT(8'h40))
288 
    reset_TX_FIFO_i_1
289 
       (.I0(enable_interrupts_reg),
290 
        .I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
291 
        .I2(s_axi_wdata[0]),
292 
        .O(reset_TX_FIFO));
293 
  LUT4 #(
294 
    .INIT(16'h0444))
295 
    rx_Data_Present_Pre_i_1
296 
       (.I0(\INFERRED_GEN.cnt_i_reg[4] ),
297 
        .I1(s_axi_aresetn),
298 
        .I2(enable_interrupts_reg),
299 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
300 
        .O(rx_Data_Present_Pre_reg));
301 
  (* SOFT_HLUTNM = "soft_lutpair3" *)
302 
  LUT5 #(
303 
    .INIT(32'hF0F0F0E0))
304 
    s_axi_arready_INST_0
305 
       (.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
306 
        .I1(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
307 
        .I2(enable_interrupts_reg),
308 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
309 
        .I4(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
310 
        .O(s_axi_arready));
311 
  LUT4 #(
312 
    .INIT(16'hFB08))
313 
    \s_axi_bresp_i[1]_i_1
314 
       (.I0(ip2bus_error),
315 
        .I1(Q[1]),
316 
        .I2(Q[0]),
317 
        .I3(s_axi_bresp),
318 
        .O(\s_axi_bresp_i_reg[1] ));
319 
  LUT5 #(
320 
    .INIT(32'h40FF4040))
321 
    s_axi_bvalid_i_i_1
322 
       (.I0(Q[0]),
323 
        .I1(Q[1]),
324 
        .I2(s_axi_awready),
325 
        .I3(s_axi_bready),
326 
        .I4(s_axi_bvalid_i_reg_0),
327 
        .O(s_axi_bvalid_i_reg));
328 
  (* SOFT_HLUTNM = "soft_lutpair0" *)
329 
  LUT5 #(
330 
    .INIT(32'h5050C000))
331 
    \s_axi_rdata_i[0]_i_1
332 
       (.I0(\INFERRED_GEN.cnt_i_reg[4] ),
333 
        .I1(out[0]),
334 
        .I2(enable_interrupts_reg),
335 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
336 
        .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
337 
        .O(\s_axi_rdata_i_reg[7] [0]));
338 
  (* SOFT_HLUTNM = "soft_lutpair1" *)
339 
  LUT5 #(
340 
    .INIT(32'hA0A0C000))
341 
    \s_axi_rdata_i[1]_i_1
342 
       (.I0(rx_Buffer_Full),
343 
        .I1(out[1]),
344 
        .I2(enable_interrupts_reg),
345 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
346 
        .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
347 
        .O(\s_axi_rdata_i_reg[7] [1]));
348 
  (* SOFT_HLUTNM = "soft_lutpair2" *)
349 
  LUT5 #(
350 
    .INIT(32'hA0A0C000))
351 
    \s_axi_rdata_i[2]_i_1
352 
       (.I0(\INFERRED_GEN.cnt_i_reg[4]_0 ),
353 
        .I1(out[2]),
354 
        .I2(enable_interrupts_reg),
355 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
356 
        .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
357 
        .O(\s_axi_rdata_i_reg[7] [2]));
358 
  LUT5 #(
359 
    .INIT(32'hA0A0C000))
360 
    \s_axi_rdata_i[3]_i_1
361 
       (.I0(tx_Buffer_Full),
362 
        .I1(out[3]),
363 
        .I2(enable_interrupts_reg),
364 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
365 
        .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
366 
        .O(\s_axi_rdata_i_reg[7] [3]));
367 
  LUT5 #(
368 
    .INIT(32'hA0A0C000))
369 
    \s_axi_rdata_i[4]_i_1
370 
       (.I0(enable_interrupts),
371 
        .I1(out[4]),
372 
        .I2(enable_interrupts_reg),
373 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
374 
        .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
375 
        .O(\s_axi_rdata_i_reg[7] [4]));
376 
  LUT5 #(
377 
    .INIT(32'hA0A0C000))
378 
    \s_axi_rdata_i[5]_i_1
379 
       (.I0(status_reg[0]),
380 
        .I1(out[5]),
381 
        .I2(enable_interrupts_reg),
382 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
383 
        .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
384 
        .O(\s_axi_rdata_i_reg[7] [5]));
385 
  LUT5 #(
386 
    .INIT(32'hA0A0C000))
387 
    \s_axi_rdata_i[6]_i_1
388 
       (.I0(status_reg[1]),
389 
        .I1(out[6]),
390 
        .I2(enable_interrupts_reg),
391 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
392 
        .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
393 
        .O(\s_axi_rdata_i_reg[7] [6]));
394 
  LUT4 #(
395 
    .INIT(16'h4000))
396 
    \s_axi_rdata_i[7]_i_2
397 
       (.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
398 
        .I1(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
399 
        .I2(enable_interrupts_reg),
400 
        .I3(out[7]),
401 
        .O(\s_axi_rdata_i_reg[7] [7]));
402 
  (* SOFT_HLUTNM = "soft_lutpair4" *)
403 
  LUT5 #(
404 
    .INIT(32'hF0880088))
405 
    \s_axi_rresp_i[1]_i_1
406 
       (.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
407 
        .I1(tx_Buffer_Full),
408 
        .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
409 
        .I3(enable_interrupts_reg),
410 
        .I4(\INFERRED_GEN.cnt_i_reg[4] ),
411 
        .O(ip2bus_error));
412 
  LUT5 #(
413 
    .INIT(32'h40FF4040))
414 
    s_axi_rvalid_i_i_1
415 
       (.I0(Q[1]),
416 
        .I1(Q[0]),
417 
        .I2(s_axi_arready),
418 
        .I3(s_axi_rready),
419 
        .I4(s_axi_rvalid_i_reg_0),
420 
        .O(s_axi_rvalid_i_reg));
421 
  (* SOFT_HLUTNM = "soft_lutpair3" *)
422 
  LUT5 #(
423 
    .INIT(32'h0F0F0F0E))
424 
    s_axi_wready_INST_0
425 
       (.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
426 
        .I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
427 
        .I2(enable_interrupts_reg),
428 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
429 
        .I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
430 
        .O(s_axi_awready));
431 
  LUT5 #(
432 
    .INIT(32'hCFEFCFEC))
433 
    \state[0]_i_1
434 
       (.I0(s_axi_awready),
435 
        .I1(\state_reg[0] ),
436 
        .I2(Q[1]),
437 
        .I3(Q[0]),
438 
        .I4(s_axi_arvalid),
439 
        .O(D[0]));
440 
  LUT6 #(
441 
    .INIT(64'hCFECCFECCFEFCFEC))
442 
    \state[1]_i_1
443 
       (.I0(s_axi_arready),
444 
        .I1(\state_reg[1] ),
445 
        .I2(Q[0]),
446 
        .I3(Q[1]),
447 
        .I4(s_axi_wvalid),
448 
        .I5(s_axi_arvalid),
449 
        .O(D[1]));
450 
  (* SOFT_HLUTNM = "soft_lutpair6" *)
451 
  LUT4 #(
452 
    .INIT(16'h8808))
453 
    tx_Buffer_Empty_Pre_i_1
454 
       (.I0(s_axi_aresetn),
455 
        .I1(\INFERRED_GEN.cnt_i_reg[4]_0 ),
456 
        .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
457 
        .I3(enable_interrupts_reg),
458 
        .O(tx_Buffer_Empty_Pre_reg));
459 
endmodule
460 
 
461 
module axi_uartlite_module_sim_axi_lite_ipif
462 
   (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
463 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
464 
    s_axi_rresp,
465 
    Bus_RNW_reg,
466 
    s_axi_rvalid,
467 
    s_axi_bvalid,
468 
    s_axi_bresp,
469 
    reset_TX_FIFO,
470 
    reset_RX_FIFO,
471 
    s_axi_awready,
472 
    s_axi_arready,
473 
    \INFERRED_GEN.cnt_i_reg[2] ,
474 
    rx_Data_Present_Pre_reg,
475 
    FIFO_Full_reg,
476 
    bus2ip_rdce,
477 
    fifo_wr,
478 
    \INFERRED_GEN.cnt_i_reg[2]_0 ,
479 
    tx_Buffer_Empty_Pre_reg,
480 
    enable_interrupts_reg,
481 
    s_axi_rdata,
482 
    bus2ip_reset,
483 
    s_axi_aclk,
484 
    s_axi_wdata,
485 
    s_axi_arvalid,
486 
    s_axi_aresetn,
487 
    Q,
488 
    out,
489 
    rx_Buffer_Full,
490 
    \INFERRED_GEN.cnt_i_reg[4] ,
491 
    tx_Buffer_Full,
492 
    enable_interrupts,
493 
    status_reg,
494 
    s_axi_awvalid,
495 
    s_axi_wvalid,
496 
    s_axi_rready,
497 
    s_axi_bready,
498 
    s_axi_awaddr,
499 
    s_axi_araddr);
500 
  output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
501 
  output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
502 
  output [0:0]s_axi_rresp;
503 
  output Bus_RNW_reg;
504 
  output s_axi_rvalid;
505 
  output s_axi_bvalid;
506 
  output [0:0]s_axi_bresp;
507 
  output reset_TX_FIFO;
508 
  output reset_RX_FIFO;
509 
  output s_axi_awready;
510 
  output s_axi_arready;
511 
  output \INFERRED_GEN.cnt_i_reg[2] ;
512 
  output rx_Data_Present_Pre_reg;
513 
  output FIFO_Full_reg;
514 
  output [0:0]bus2ip_rdce;
515 
  output fifo_wr;
516 
  output \INFERRED_GEN.cnt_i_reg[2]_0 ;
517 
  output tx_Buffer_Empty_Pre_reg;
518 
  output enable_interrupts_reg;
519 
  output [7:0]s_axi_rdata;
520 
  input bus2ip_reset;
521 
  input s_axi_aclk;
522 
  input [2:0]s_axi_wdata;
523 
  input s_axi_arvalid;
524 
  input s_axi_aresetn;
525 
  input [0:0]Q;
526 
  input [7:0]out;
527 
  input rx_Buffer_Full;
528 
  input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
529 
  input tx_Buffer_Full;
530 
  input enable_interrupts;
531 
  input [1:0]status_reg;
532 
  input s_axi_awvalid;
533 
  input s_axi_wvalid;
534 
  input s_axi_rready;
535 
  input s_axi_bready;
536 
  input [1:0]s_axi_awaddr;
537 
  input [1:0]s_axi_araddr;
538 
 
539 
  wire Bus_RNW_reg;
540 
  wire FIFO_Full_reg;
541 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
542 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
543 
  wire \INFERRED_GEN.cnt_i_reg[2] ;
544 
  wire \INFERRED_GEN.cnt_i_reg[2]_0 ;
545 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
546 
  wire [0:0]Q;
547 
  wire [0:0]bus2ip_rdce;
548 
  wire bus2ip_reset;
549 
  wire enable_interrupts;
550 
  wire enable_interrupts_reg;
551 
  wire fifo_wr;
552 
  wire [7:0]out;
553 
  wire reset_RX_FIFO;
554 
  wire reset_TX_FIFO;
555 
  wire rx_Buffer_Full;
556 
  wire rx_Data_Present_Pre_reg;
557 
  wire s_axi_aclk;
558 
  wire [1:0]s_axi_araddr;
559 
  wire s_axi_aresetn;
560 
  wire s_axi_arready;
561 
  wire s_axi_arvalid;
562 
  wire [1:0]s_axi_awaddr;
563 
  wire s_axi_awready;
564 
  wire s_axi_awvalid;
565 
  wire s_axi_bready;
566 
  wire [0:0]s_axi_bresp;
567 
  wire s_axi_bvalid;
568 
  wire [7:0]s_axi_rdata;
569 
  wire s_axi_rready;
570 
  wire [0:0]s_axi_rresp;
571 
  wire s_axi_rvalid;
572 
  wire [2:0]s_axi_wdata;
573 
  wire s_axi_wvalid;
574 
  wire [1:0]status_reg;
575 
  wire tx_Buffer_Empty_Pre_reg;
576 
  wire tx_Buffer_Full;
577 
 
578 
  axi_uartlite_module_sim_slave_attachment I_SLAVE_ATTACHMENT
579 
       (.FIFO_Full_reg(FIFO_Full_reg),
580 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
581 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
582 
        .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
583 
        .\INFERRED_GEN.cnt_i_reg[2]_0 (\INFERRED_GEN.cnt_i_reg[2]_0 ),
584 
        .\INFERRED_GEN.cnt_i_reg[4] (\INFERRED_GEN.cnt_i_reg[4] ),
585 
        .Q(Q),
586 
        .bus2ip_rdce(bus2ip_rdce),
587 
        .bus2ip_reset(bus2ip_reset),
588 
        .enable_interrupts(enable_interrupts),
589 
        .enable_interrupts_reg(Bus_RNW_reg),
590 
        .enable_interrupts_reg_0(enable_interrupts_reg),
591 
        .fifo_wr(fifo_wr),
592 
        .out(out),
593 
        .reset_RX_FIFO(reset_RX_FIFO),
594 
        .reset_TX_FIFO(reset_TX_FIFO),
595 
        .rx_Buffer_Full(rx_Buffer_Full),
596 
        .rx_Data_Present_Pre_reg(rx_Data_Present_Pre_reg),
597 
        .s_axi_aclk(s_axi_aclk),
598 
        .s_axi_araddr(s_axi_araddr),
599 
        .s_axi_aresetn(s_axi_aresetn),
600 
        .s_axi_arready(s_axi_arready),
601 
        .s_axi_arvalid(s_axi_arvalid),
602 
        .s_axi_awaddr(s_axi_awaddr),
603 
        .s_axi_awready(s_axi_awready),
604 
        .s_axi_awvalid(s_axi_awvalid),
605 
        .s_axi_bready(s_axi_bready),
606 
        .s_axi_bresp(s_axi_bresp),
607 
        .s_axi_bvalid(s_axi_bvalid),
608 
        .s_axi_rdata(s_axi_rdata),
609 
        .s_axi_rready(s_axi_rready),
610 
        .s_axi_rresp(s_axi_rresp),
611 
        .s_axi_rvalid(s_axi_rvalid),
612 
        .s_axi_wdata(s_axi_wdata),
613 
        .s_axi_wvalid(s_axi_wvalid),
614 
        .status_reg(status_reg),
615 
        .tx_Buffer_Empty_Pre_reg(tx_Buffer_Empty_Pre_reg),
616 
        .tx_Buffer_Full(tx_Buffer_Full));
617 
endmodule
618 
 
619 
(* C_BAUDRATE = "38400" *) (* C_DATA_BITS = "8" *) (* C_FAMILY = "kintex7" *)
620 
(* C_ODD_PARITY = "0" *) (* C_S_AXI_ACLK_FREQ_HZ = "100000000" *) (* C_S_AXI_ADDR_WIDTH = "4" *)
621 
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_USE_PARITY = "0" *) (* downgradeipidentifiedwarnings = "yes" *)
622 
module axi_uartlite_module_sim_axi_uartlite
623 
   (s_axi_aclk,
624 
    s_axi_aresetn,
625 
    interrupt,
626 
    s_axi_awaddr,
627 
    s_axi_awvalid,
628 
    s_axi_awready,
629 
    s_axi_wdata,
630 
    s_axi_wstrb,
631 
    s_axi_wvalid,
632 
    s_axi_wready,
633 
    s_axi_bresp,
634 
    s_axi_bvalid,
635 
    s_axi_bready,
636 
    s_axi_araddr,
637 
    s_axi_arvalid,
638 
    s_axi_arready,
639 
    s_axi_rdata,
640 
    s_axi_rresp,
641 
    s_axi_rvalid,
642 
    s_axi_rready,
643 
    rx,
644 
    tx);
645 
  (* max_fanout = "10000" *) input s_axi_aclk;
646 
  (* max_fanout = "10000" *) input s_axi_aresetn;
647 
  output interrupt;
648 
  input [3:0]s_axi_awaddr;
649 
  input s_axi_awvalid;
650 
  output s_axi_awready;
651 
  input [31:0]s_axi_wdata;
652 
  input [3:0]s_axi_wstrb;
653 
  input s_axi_wvalid;
654 
  output s_axi_wready;
655 
  output [1:0]s_axi_bresp;
656 
  output s_axi_bvalid;
657 
  input s_axi_bready;
658 
  input [3:0]s_axi_araddr;
659 
  input s_axi_arvalid;
660 
  output s_axi_arready;
661 
  output [31:0]s_axi_rdata;
662 
  output [1:0]s_axi_rresp;
663 
  output s_axi_rvalid;
664 
  input s_axi_rready;
665 
  input rx;
666 
  output tx;
667 
 
668 
  wire \<const0> ;
669 
  wire AXI_LITE_IPIF_I_n_11;
670 
  wire AXI_LITE_IPIF_I_n_12;
671 
  wire AXI_LITE_IPIF_I_n_13;
672 
  wire AXI_LITE_IPIF_I_n_16;
673 
  wire AXI_LITE_IPIF_I_n_17;
674 
  wire AXI_LITE_IPIF_I_n_18;
675 
  wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
676 
  wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
677 
  wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
678 
  wire \UARTLITE_RX_I/rx_Data_Empty ;
679 
  wire \UARTLITE_TX_I/fifo_wr ;
680 
  wire [1:1]bus2ip_rdce;
681 
  wire bus2ip_reset;
682 
  wire enable_interrupts;
683 
  wire interrupt;
684 
  wire reset_RX_FIFO;
685 
  wire reset_TX_FIFO;
686 
  wire rx;
687 
  wire rx_Buffer_Full;
688 
  wire [0:7]rx_Data;
689 
  (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) wire s_axi_aclk;
690 
  wire [3:0]s_axi_araddr;
691 
  (* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) wire s_axi_aresetn;
692 
  wire s_axi_arready;
693 
  wire s_axi_arvalid;
694 
  wire [3:0]s_axi_awaddr;
695 
  wire s_axi_awready;
696 
  wire s_axi_awvalid;
697 
  wire s_axi_bready;
698 
  wire [1:1]\^s_axi_bresp ;
699 
  wire s_axi_bvalid;
700 
  wire [7:0]\^s_axi_rdata ;
701 
  wire s_axi_rready;
702 
  wire [1:1]\^s_axi_rresp ;
703 
  wire s_axi_rvalid;
704 
  wire [31:0]s_axi_wdata;
705 
  wire s_axi_wvalid;
706 
  wire [1:2]status_reg;
707 
  wire tx;
708 
  wire tx_Buffer_Empty;
709 
  wire tx_Buffer_Full;
710 
 
711 
  assign s_axi_bresp[1] = \^s_axi_bresp [1];
712 
  assign s_axi_bresp[0] = \<const0> ;
713 
  assign s_axi_rdata[31] = \<const0> ;
714 
  assign s_axi_rdata[30] = \<const0> ;
715 
  assign s_axi_rdata[29] = \<const0> ;
716 
  assign s_axi_rdata[28] = \<const0> ;
717 
  assign s_axi_rdata[27] = \<const0> ;
718 
  assign s_axi_rdata[26] = \<const0> ;
719 
  assign s_axi_rdata[25] = \<const0> ;
720 
  assign s_axi_rdata[24] = \<const0> ;
721 
  assign s_axi_rdata[23] = \<const0> ;
722 
  assign s_axi_rdata[22] = \<const0> ;
723 
  assign s_axi_rdata[21] = \<const0> ;
724 
  assign s_axi_rdata[20] = \<const0> ;
725 
  assign s_axi_rdata[19] = \<const0> ;
726 
  assign s_axi_rdata[18] = \<const0> ;
727 
  assign s_axi_rdata[17] = \<const0> ;
728 
  assign s_axi_rdata[16] = \<const0> ;
729 
  assign s_axi_rdata[15] = \<const0> ;
730 
  assign s_axi_rdata[14] = \<const0> ;
731 
  assign s_axi_rdata[13] = \<const0> ;
732 
  assign s_axi_rdata[12] = \<const0> ;
733 
  assign s_axi_rdata[11] = \<const0> ;
734 
  assign s_axi_rdata[10] = \<const0> ;
735 
  assign s_axi_rdata[9] = \<const0> ;
736 
  assign s_axi_rdata[8] = \<const0> ;
737 
  assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
738 
  assign s_axi_rresp[1] = \^s_axi_rresp [1];
739 
  assign s_axi_rresp[0] = \<const0> ;
740 
  assign s_axi_wready = s_axi_awready;
741 
  axi_uartlite_module_sim_axi_lite_ipif AXI_LITE_IPIF_I
742 
       (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
743 
        .FIFO_Full_reg(AXI_LITE_IPIF_I_n_13),
744 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
745 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
746 
        .\INFERRED_GEN.cnt_i_reg[2] (AXI_LITE_IPIF_I_n_11),
747 
        .\INFERRED_GEN.cnt_i_reg[2]_0 (AXI_LITE_IPIF_I_n_16),
748 
        .\INFERRED_GEN.cnt_i_reg[4] (tx_Buffer_Empty),
749 
        .Q(\UARTLITE_RX_I/rx_Data_Empty ),
750 
        .bus2ip_rdce(bus2ip_rdce),
751 
        .bus2ip_reset(bus2ip_reset),
752 
        .enable_interrupts(enable_interrupts),
753 
        .enable_interrupts_reg(AXI_LITE_IPIF_I_n_18),
754 
        .fifo_wr(\UARTLITE_TX_I/fifo_wr ),
755 
        .out({rx_Data[0],rx_Data[1],rx_Data[2],rx_Data[3],rx_Data[4],rx_Data[5],rx_Data[6],rx_Data[7]}),
756 
        .reset_RX_FIFO(reset_RX_FIFO),
757 
        .reset_TX_FIFO(reset_TX_FIFO),
758 
        .rx_Buffer_Full(rx_Buffer_Full),
759 
        .rx_Data_Present_Pre_reg(AXI_LITE_IPIF_I_n_12),
760 
        .s_axi_aclk(s_axi_aclk),
761 
        .s_axi_araddr(s_axi_araddr[3:2]),
762 
        .s_axi_aresetn(s_axi_aresetn),
763 
        .s_axi_arready(s_axi_arready),
764 
        .s_axi_arvalid(s_axi_arvalid),
765 
        .s_axi_awaddr(s_axi_awaddr[3:2]),
766 
        .s_axi_awready(s_axi_awready),
767 
        .s_axi_awvalid(s_axi_awvalid),
768 
        .s_axi_bready(s_axi_bready),
769 
        .s_axi_bresp(\^s_axi_bresp ),
770 
        .s_axi_bvalid(s_axi_bvalid),
771 
        .s_axi_rdata(\^s_axi_rdata ),
772 
        .s_axi_rready(s_axi_rready),
773 
        .s_axi_rresp(\^s_axi_rresp ),
774 
        .s_axi_rvalid(s_axi_rvalid),
775 
        .s_axi_wdata({s_axi_wdata[4],s_axi_wdata[1:0]}),
776 
        .s_axi_wvalid(s_axi_wvalid),
777 
        .status_reg({status_reg[1],status_reg[2]}),
778 
        .tx_Buffer_Empty_Pre_reg(AXI_LITE_IPIF_I_n_17),
779 
        .tx_Buffer_Full(tx_Buffer_Full));
780 
  GND GND
781 
       (.G(\<const0> ));
782 
  axi_uartlite_module_sim_uartlite_core UARTLITE_CORE_I
783 
       (.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
784 
        .Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_11),
785 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
786 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (AXI_LITE_IPIF_I_n_13),
787 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
788 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (AXI_LITE_IPIF_I_n_16),
789 
        .\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] (AXI_LITE_IPIF_I_n_18),
790 
        .\INFERRED_GEN.cnt_i_reg[2] (tx_Buffer_Empty),
791 
        .\INFERRED_GEN.cnt_i_reg[4] (AXI_LITE_IPIF_I_n_17),
792 
        .\INFERRED_GEN.cnt_i_reg[4]_0 (AXI_LITE_IPIF_I_n_12),
793 
        .Q(\UARTLITE_RX_I/rx_Data_Empty ),
794 
        .bus2ip_rdce(bus2ip_rdce),
795 
        .bus2ip_reset(bus2ip_reset),
796 
        .enable_interrupts(enable_interrupts),
797 
        .fifo_wr(\UARTLITE_TX_I/fifo_wr ),
798 
        .interrupt(interrupt),
799 
        .out({rx_Data[0],rx_Data[1],rx_Data[2],rx_Data[3],rx_Data[4],rx_Data[5],rx_Data[6],rx_Data[7]}),
800 
        .reset_RX_FIFO(reset_RX_FIFO),
801 
        .reset_TX_FIFO(reset_TX_FIFO),
802 
        .rx(rx),
803 
        .rx_Buffer_Full(rx_Buffer_Full),
804 
        .s_axi_aclk(s_axi_aclk),
805 
        .s_axi_aresetn(s_axi_aresetn),
806 
        .s_axi_wdata(s_axi_wdata[7:0]),
807 
        .status_reg({status_reg[1],status_reg[2]}),
808 
        .tx(tx),
809 
        .tx_Buffer_Full(tx_Buffer_Full));
810 
endmodule
811 
 
812 
(* CHECK_LICENSE_TYPE = "axi_uartlite_module,axi_uartlite,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_uartlite,Vivado 2017.4" *)
813 
(* NotValidForBitStream *)
814 
module axi_uartlite_module_sim
815 
   (s_axi_aclk,
816 
    s_axi_aresetn,
817 
    interrupt,
818 
    s_axi_awaddr,
819 
    s_axi_awvalid,
820 
    s_axi_awready,
821 
    s_axi_wdata,
822 
    s_axi_wstrb,
823 
    s_axi_wvalid,
824 
    s_axi_wready,
825 
    s_axi_bresp,
826 
    s_axi_bvalid,
827 
    s_axi_bready,
828 
    s_axi_araddr,
829 
    s_axi_arvalid,
830 
    s_axi_arready,
831 
    s_axi_rdata,
832 
    s_axi_rresp,
833 
    s_axi_rvalid,
834 
    s_axi_rready,
835 
    rx,
836 
    tx);
837 
  (* x_interface_info = "xilinx.com:signal:clock:1.0 ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000" *) input s_axi_aclk;
838 
  (* x_interface_info = "xilinx.com:signal:reset:1.0 ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW" *) input s_axi_aresetn;
839 
  (* x_interface_info = "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME INTERRUPT, SENSITIVITY EDGE_RISING, PortWidth 1" *) output interrupt;
840 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [3:0]s_axi_awaddr;
841 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
842 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
843 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
844 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
845 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
846 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
847 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
848 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
849 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
850 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [3:0]s_axi_araddr;
851 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
852 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
853 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
854 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
855 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
856 
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
857 
  (* x_interface_info = "xilinx.com:interface:uart:1.0 UART RxD" *) (* x_interface_parameter = "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UARTLITE_BOARD_INTERFACE" *) input rx;
858 
  (* x_interface_info = "xilinx.com:interface:uart:1.0 UART TxD" *) output tx;
859 
 
860 
  wire interrupt;
861 
  wire rx;
862 
  wire s_axi_aclk;
863 
  wire [3:0]s_axi_araddr;
864 
  wire s_axi_aresetn;
865 
  wire s_axi_arready;
866 
  wire s_axi_arvalid;
867 
  wire [3:0]s_axi_awaddr;
868 
  wire s_axi_awready;
869 
  wire s_axi_awvalid;
870 
  wire s_axi_bready;
871 
  wire [1:0]s_axi_bresp;
872 
  wire s_axi_bvalid;
873 
  wire [31:0]s_axi_rdata;
874 
  wire s_axi_rready;
875 
  wire [1:0]s_axi_rresp;
876 
  wire s_axi_rvalid;
877 
  wire [31:0]s_axi_wdata;
878 
  wire s_axi_wready;
879 
  wire [3:0]s_axi_wstrb;
880 
  wire s_axi_wvalid;
881 
  wire tx;
882 
 
883 
  (* C_BAUDRATE = "38400" *)
884 
  (* C_DATA_BITS = "8" *)
885 
  (* C_FAMILY = "kintex7" *)
886 
  (* C_ODD_PARITY = "0" *)
887 
  (* C_S_AXI_ACLK_FREQ_HZ = "100000000" *)
888 
  (* C_S_AXI_ADDR_WIDTH = "4" *)
889 
  (* C_S_AXI_DATA_WIDTH = "32" *)
890 
  (* C_USE_PARITY = "0" *)
891 
  (* downgradeipidentifiedwarnings = "yes" *)
892 
  axi_uartlite_module_sim_axi_uartlite U0
893 
       (.interrupt(interrupt),
894 
        .rx(rx),
895 
        .s_axi_aclk(s_axi_aclk),
896 
        .s_axi_araddr(s_axi_araddr),
897 
        .s_axi_aresetn(s_axi_aresetn),
898 
        .s_axi_arready(s_axi_arready),
899 
        .s_axi_arvalid(s_axi_arvalid),
900 
        .s_axi_awaddr(s_axi_awaddr),
901 
        .s_axi_awready(s_axi_awready),
902 
        .s_axi_awvalid(s_axi_awvalid),
903 
        .s_axi_bready(s_axi_bready),
904 
        .s_axi_bresp(s_axi_bresp),
905 
        .s_axi_bvalid(s_axi_bvalid),
906 
        .s_axi_rdata(s_axi_rdata),
907 
        .s_axi_rready(s_axi_rready),
908 
        .s_axi_rresp(s_axi_rresp),
909 
        .s_axi_rvalid(s_axi_rvalid),
910 
        .s_axi_wdata(s_axi_wdata),
911 
        .s_axi_wready(s_axi_wready),
912 
        .s_axi_wstrb(s_axi_wstrb),
913 
        .s_axi_wvalid(s_axi_wvalid),
914 
        .tx(tx));
915 
endmodule
916 
 
917 
module axi_uartlite_module_sim_baudrate
918 
   (en_16x_Baud,
919 
    SR,
920 
    s_axi_aclk);
921 
  output en_16x_Baud;
922 
  input [0:0]SR;
923 
  input s_axi_aclk;
924 
 
925 
  wire EN_16x_Baud;
926 
  wire [0:0]SR;
927 
  wire [7:0]count;
928 
  wire \count[2]_i_2_n_0 ;
929 
  wire \count[3]_i_2_n_0 ;
930 
  wire \count[4]_i_2_n_0 ;
931 
  wire \count[7]_i_2_n_0 ;
932 
  wire [7:0]count_0;
933 
  wire en_16x_Baud;
934 
  wire s_axi_aclk;
935 
 
936 
  (* SOFT_HLUTNM = "soft_lutpair12" *)
937 
  LUT4 #(
938 
    .INIT(16'h0001))
939 
    EN_16x_Baud_i_1
940 
       (.I0(count[7]),
941 
        .I1(count[5]),
942 
        .I2(count[6]),
943 
        .I3(\count[7]_i_2_n_0 ),
944 
        .O(EN_16x_Baud));
945 
  FDRE EN_16x_Baud_reg
946 
       (.C(s_axi_aclk),
947 
        .CE(1'b1),
948 
        .D(EN_16x_Baud),
949 
        .Q(en_16x_Baud),
950 
        .R(SR));
951 
  LUT6 #(
952 
    .INIT(64'h0000FFFF0000FFFE))
953 
    \count[0]_i_1
954 
       (.I0(count[3]),
955 
        .I1(\count[2]_i_2_n_0 ),
956 
        .I2(count[4]),
957 
        .I3(count[2]),
958 
        .I4(count[0]),
959 
        .I5(count[1]),
960 
        .O(count_0[0]));
961 
  (* SOFT_HLUTNM = "soft_lutpair13" *)
962 
  LUT2 #(
963 
    .INIT(4'h9))
964 
    \count[1]_i_1
965 
       (.I0(count[1]),
966 
        .I1(count[0]),
967 
        .O(count_0[1]));
968 
  LUT6 #(
969 
    .INIT(64'hE1E1E1E1E1E1E1E0))
970 
    \count[2]_i_1
971 
       (.I0(count[1]),
972 
        .I1(count[0]),
973 
        .I2(count[2]),
974 
        .I3(count[4]),
975 
        .I4(\count[2]_i_2_n_0 ),
976 
        .I5(count[3]),
977 
        .O(count_0[2]));
978 
  (* SOFT_HLUTNM = "soft_lutpair10" *)
979 
  LUT3 #(
980 
    .INIT(8'hFE))
981 
    \count[2]_i_2
982 
       (.I0(count[6]),
983 
        .I1(count[5]),
984 
        .I2(count[7]),
985 
        .O(\count[2]_i_2_n_0 ));
986 
  LUT6 #(
987 
    .INIT(64'h9999999999999998))
988 
    \count[3]_i_1
989 
       (.I0(\count[3]_i_2_n_0 ),
990 
        .I1(count[3]),
991 
        .I2(count[7]),
992 
        .I3(count[5]),
993 
        .I4(count[6]),
994 
        .I5(count[4]),
995 
        .O(count_0[3]));
996 
  (* SOFT_HLUTNM = "soft_lutpair13" *)
997 
  LUT3 #(
998 
    .INIT(8'hFE))
999 
    \count[3]_i_2
1000 
       (.I0(count[1]),
1001 
        .I1(count[0]),
1002 
        .I2(count[2]),
1003 
        .O(\count[3]_i_2_n_0 ));
1004 
  (* SOFT_HLUTNM = "soft_lutpair10" *)
1005 
  LUT5 #(
1006 
    .INIT(32'h99999998))
1007 
    \count[4]_i_1
1008 
       (.I0(\count[4]_i_2_n_0 ),
1009 
        .I1(count[4]),
1010 
        .I2(count[6]),
1011 
        .I3(count[5]),
1012 
        .I4(count[7]),
1013 
        .O(count_0[4]));
1014 
  (* SOFT_HLUTNM = "soft_lutpair11" *)
1015 
  LUT4 #(
1016 
    .INIT(16'hFFFE))
1017 
    \count[4]_i_2
1018 
       (.I0(count[2]),
1019 
        .I1(count[0]),
1020 
        .I2(count[1]),
1021 
        .I3(count[3]),
1022 
        .O(\count[4]_i_2_n_0 ));
1023 
  LUT6 #(
1024 
    .INIT(64'hAAAAAAAAAAAAAAA9))
1025 
    \count[5]_i_1
1026 
       (.I0(count[5]),
1027 
        .I1(count[3]),
1028 
        .I2(count[1]),
1029 
        .I3(count[0]),
1030 
        .I4(count[2]),
1031 
        .I5(count[4]),
1032 
        .O(count_0[5]));
1033 
  (* SOFT_HLUTNM = "soft_lutpair12" *)
1034 
  LUT4 #(
1035 
    .INIT(16'hC9C8))
1036 
    \count[6]_i_1
1037 
       (.I0(\count[7]_i_2_n_0 ),
1038 
        .I1(count[6]),
1039 
        .I2(count[5]),
1040 
        .I3(count[7]),
1041 
        .O(count_0[6]));
1042 
  LUT4 #(
1043 
    .INIT(16'hFE01))
1044 
    \count[7]_i_1
1045 
       (.I0(\count[7]_i_2_n_0 ),
1046 
        .I1(count[6]),
1047 
        .I2(count[5]),
1048 
        .I3(count[7]),
1049 
        .O(count_0[7]));
1050 
  (* SOFT_HLUTNM = "soft_lutpair11" *)
1051 
  LUT5 #(
1052 
    .INIT(32'hFFFFFFFE))
1053 
    \count[7]_i_2
1054 
       (.I0(count[3]),
1055 
        .I1(count[1]),
1056 
        .I2(count[0]),
1057 
        .I3(count[2]),
1058 
        .I4(count[4]),
1059 
        .O(\count[7]_i_2_n_0 ));
1060 
  FDRE \count_reg[0]
1061 
       (.C(s_axi_aclk),
1062 
        .CE(1'b1),
1063 
        .D(count_0[0]),
1064 
        .Q(count[0]),
1065 
        .R(SR));
1066 
  FDRE \count_reg[1]
1067 
       (.C(s_axi_aclk),
1068 
        .CE(1'b1),
1069 
        .D(count_0[1]),
1070 
        .Q(count[1]),
1071 
        .R(SR));
1072 
  FDRE \count_reg[2]
1073 
       (.C(s_axi_aclk),
1074 
        .CE(1'b1),
1075 
        .D(count_0[2]),
1076 
        .Q(count[2]),
1077 
        .R(SR));
1078 
  FDRE \count_reg[3]
1079 
       (.C(s_axi_aclk),
1080 
        .CE(1'b1),
1081 
        .D(count_0[3]),
1082 
        .Q(count[3]),
1083 
        .R(SR));
1084 
  FDRE \count_reg[4]
1085 
       (.C(s_axi_aclk),
1086 
        .CE(1'b1),
1087 
        .D(count_0[4]),
1088 
        .Q(count[4]),
1089 
        .R(SR));
1090 
  FDRE \count_reg[5]
1091 
       (.C(s_axi_aclk),
1092 
        .CE(1'b1),
1093 
        .D(count_0[5]),
1094 
        .Q(count[5]),
1095 
        .R(SR));
1096 
  FDRE \count_reg[6]
1097 
       (.C(s_axi_aclk),
1098 
        .CE(1'b1),
1099 
        .D(count_0[6]),
1100 
        .Q(count[6]),
1101 
        .R(SR));
1102 
  FDRE \count_reg[7]
1103 
       (.C(s_axi_aclk),
1104 
        .CE(1'b1),
1105 
        .D(count_0[7]),
1106 
        .Q(count[7]),
1107 
        .R(SR));
1108 
endmodule
1109 
 
1110 
module axi_uartlite_module_sim_cdc_sync
1111 
   (p_26_out,
1112 
    scndry_out,
1113 
    start_Edge_Detected,
1114 
    EN_16x_Baud_reg,
1115 
    s_axi_aresetn,
1116 
    in,
1117 
    rx,
1118 
    s_axi_aclk);
1119 
  output p_26_out;
1120 
  output scndry_out;
1121 
  input start_Edge_Detected;
1122 
  input EN_16x_Baud_reg;
1123 
  input s_axi_aresetn;
1124 
  input [0:0]in;
1125 
  input rx;
1126 
  input s_axi_aclk;
1127 
 
1128 
  wire EN_16x_Baud_reg;
1129 
  wire [0:0]in;
1130 
  wire p_26_out;
1131 
  wire rx;
1132 
  wire s_axi_aclk;
1133 
  wire s_axi_aresetn;
1134 
  wire s_level_out_d1_cdc_to;
1135 
  wire s_level_out_d2;
1136 
  wire s_level_out_d3;
1137 
  wire scndry_out;
1138 
  wire start_Edge_Detected;
1139 
 
1140 
  (* ASYNC_REG *)
1141 
  (* XILINX_LEGACY_PRIM = "FDR" *)
1142 
  (* box_type = "PRIMITIVE" *)
1143 
  FDRE #(
1144 
    .INIT(1'b0))
1145 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
1146 
       (.C(s_axi_aclk),
1147 
        .CE(1'b1),
1148 
        .D(rx),
1149 
        .Q(s_level_out_d1_cdc_to),
1150 
        .R(1'b0));
1151 
  (* ASYNC_REG *)
1152 
  (* XILINX_LEGACY_PRIM = "FDR" *)
1153 
  (* box_type = "PRIMITIVE" *)
1154 
  FDRE #(
1155 
    .INIT(1'b0))
1156 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
1157 
       (.C(s_axi_aclk),
1158 
        .CE(1'b1),
1159 
        .D(s_level_out_d1_cdc_to),
1160 
        .Q(s_level_out_d2),
1161 
        .R(1'b0));
1162 
  (* ASYNC_REG *)
1163 
  (* XILINX_LEGACY_PRIM = "FDR" *)
1164 
  (* box_type = "PRIMITIVE" *)
1165 
  FDRE #(
1166 
    .INIT(1'b0))
1167 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
1168 
       (.C(s_axi_aclk),
1169 
        .CE(1'b1),
1170 
        .D(s_level_out_d2),
1171 
        .Q(s_level_out_d3),
1172 
        .R(1'b0));
1173 
  (* ASYNC_REG *)
1174 
  (* XILINX_LEGACY_PRIM = "FDR" *)
1175 
  (* box_type = "PRIMITIVE" *)
1176 
  FDRE #(
1177 
    .INIT(1'b0))
1178 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
1179 
       (.C(s_axi_aclk),
1180 
        .CE(1'b1),
1181 
        .D(s_level_out_d3),
1182 
        .Q(scndry_out),
1183 
        .R(1'b0));
1184 
  LUT5 #(
1185 
    .INIT(32'hFE00CE00))
1186 
    \SERIAL_TO_PARALLEL[1].fifo_din[1]_i_1
1187 
       (.I0(scndry_out),
1188 
        .I1(start_Edge_Detected),
1189 
        .I2(EN_16x_Baud_reg),
1190 
        .I3(s_axi_aresetn),
1191 
        .I4(in),
1192 
        .O(p_26_out));
1193 
endmodule
1194 
 
1195 
module axi_uartlite_module_sim_cntr_incr_decr_addn_f
1196 
   (SS,
1197 
    Q,
1198 
    fifo_full_p1,
1199 
    tx_Start0,
1200 
    reset_TX_FIFO_reg,
1201 
    s_axi_aresetn,
1202 
    fifo_Read,
1203 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
1204 
    tx_Buffer_Full,
1205 
    Bus_RNW_reg,
1206 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
1207 
    tx_Data_Enable_reg,
1208 
    tx_DataBits,
1209 
    tx_Start,
1210 
    s_axi_aclk);
1211 
  output [0:0]SS;
1212 
  output [4:0]Q;
1213 
  output fifo_full_p1;
1214 
  output tx_Start0;
1215 
  input reset_TX_FIFO_reg;
1216 
  input s_axi_aresetn;
1217 
  input fifo_Read;
1218 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
1219 
  input tx_Buffer_Full;
1220 
  input Bus_RNW_reg;
1221 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
1222 
  input tx_Data_Enable_reg;
1223 
  input tx_DataBits;
1224 
  input tx_Start;
1225 
  input s_axi_aclk;
1226 
 
1227 
  wire Bus_RNW_reg;
1228 
  wire FIFO_Full_i_2__0_n_0;
1229 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
1230 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
1231 
  wire \INFERRED_GEN.cnt_i[3]_i_2__0_n_0 ;
1232 
  wire \INFERRED_GEN.cnt_i[4]_i_3__0_n_0 ;
1233 
  wire \INFERRED_GEN.cnt_i[4]_i_4__0_n_0 ;
1234 
  wire [4:0]Q;
1235 
  wire [0:0]SS;
1236 
  wire [4:0]addr_i_p1;
1237 
  wire fifo_Read;
1238 
  wire fifo_full_p1;
1239 
  wire reset_TX_FIFO_reg;
1240 
  wire s_axi_aclk;
1241 
  wire s_axi_aresetn;
1242 
  wire tx_Buffer_Full;
1243 
  wire tx_DataBits;
1244 
  wire tx_Data_Enable_reg;
1245 
  wire tx_Start;
1246 
  wire tx_Start0;
1247 
 
1248 
  LUT6 #(
1249 
    .INIT(64'h0000000004090000))
1250 
    FIFO_Full_i_1__0
1251 
       (.I0(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
1252 
        .I1(Q[0]),
1253 
        .I2(Q[4]),
1254 
        .I3(fifo_Read),
1255 
        .I4(Q[3]),
1256 
        .I5(FIFO_Full_i_2__0_n_0),
1257 
        .O(fifo_full_p1));
1258 
  LUT2 #(
1259 
    .INIT(4'h7))
1260 
    FIFO_Full_i_2__0
1261 
       (.I0(Q[1]),
1262 
        .I1(Q[2]),
1263 
        .O(FIFO_Full_i_2__0_n_0));
1264 
  LUT6 #(
1265 
    .INIT(64'hBBB4BBBB444B4444))
1266 
    \INFERRED_GEN.cnt_i[0]_i_1__0
1267 
       (.I0(Q[4]),
1268 
        .I1(fifo_Read),
1269 
        .I2(tx_Buffer_Full),
1270 
        .I3(Bus_RNW_reg),
1271 
        .I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
1272 
        .I5(Q[0]),
1273 
        .O(addr_i_p1[0]));
1274 
  (* SOFT_HLUTNM = "soft_lutpair19" *)
1275 
  LUT5 #(
1276 
    .INIT(32'hAA9A65AA))
1277 
    \INFERRED_GEN.cnt_i[1]_i_1__0
1278 
       (.I0(Q[1]),
1279 
        .I1(Q[4]),
1280 
        .I2(fifo_Read),
1281 
        .I3(Q[0]),
1282 
        .I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
1283 
        .O(addr_i_p1[1]));
1284 
  LUT6 #(
1285 
    .INIT(64'hF4FF0B00FFBF0040))
1286 
    \INFERRED_GEN.cnt_i[2]_i_1__0
1287 
       (.I0(Q[4]),
1288 
        .I1(fifo_Read),
1289 
        .I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
1290 
        .I3(Q[0]),
1291 
        .I4(Q[2]),
1292 
        .I5(Q[1]),
1293 
        .O(addr_i_p1[2]));
1294 
  LUT6 #(
1295 
    .INIT(64'hAAAA6AAAAAA9AAAA))
1296 
    \INFERRED_GEN.cnt_i[3]_i_1__0
1297 
       (.I0(Q[3]),
1298 
        .I1(Q[1]),
1299 
        .I2(Q[2]),
1300 
        .I3(\INFERRED_GEN.cnt_i[3]_i_2__0_n_0 ),
1301 
        .I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
1302 
        .I5(Q[0]),
1303 
        .O(addr_i_p1[3]));
1304 
  (* SOFT_HLUTNM = "soft_lutpair19" *)
1305 
  LUT2 #(
1306 
    .INIT(4'hB))
1307 
    \INFERRED_GEN.cnt_i[3]_i_2__0
1308 
       (.I0(Q[4]),
1309 
        .I1(fifo_Read),
1310 
        .O(\INFERRED_GEN.cnt_i[3]_i_2__0_n_0 ));
1311 
  LUT2 #(
1312 
    .INIT(4'hB))
1313 
    \INFERRED_GEN.cnt_i[4]_i_1__0
1314 
       (.I0(reset_TX_FIFO_reg),
1315 
        .I1(s_axi_aresetn),
1316 
        .O(SS));
1317 
  LUT6 #(
1318 
    .INIT(64'hF0F0FAFAF003F0F0))
1319 
    \INFERRED_GEN.cnt_i[4]_i_2__0
1320 
       (.I0(\INFERRED_GEN.cnt_i[4]_i_3__0_n_0 ),
1321 
        .I1(fifo_Read),
1322 
        .I2(Q[4]),
1323 
        .I3(\INFERRED_GEN.cnt_i[4]_i_4__0_n_0 ),
1324 
        .I4(Q[0]),
1325 
        .I5(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
1326 
        .O(addr_i_p1[4]));
1327 
  (* SOFT_HLUTNM = "soft_lutpair20" *)
1328 
  LUT4 #(
1329 
    .INIT(16'h0004))
1330 
    \INFERRED_GEN.cnt_i[4]_i_3__0
1331 
       (.I0(Q[3]),
1332 
        .I1(fifo_Read),
1333 
        .I2(Q[2]),
1334 
        .I3(Q[1]),
1335 
        .O(\INFERRED_GEN.cnt_i[4]_i_3__0_n_0 ));
1336 
  (* SOFT_HLUTNM = "soft_lutpair20" *)
1337 
  LUT3 #(
1338 
    .INIT(8'h7F))
1339 
    \INFERRED_GEN.cnt_i[4]_i_4__0
1340 
       (.I0(Q[2]),
1341 
        .I1(Q[1]),
1342 
        .I2(Q[3]),
1343 
        .O(\INFERRED_GEN.cnt_i[4]_i_4__0_n_0 ));
1344 
  FDSE \INFERRED_GEN.cnt_i_reg[0]
1345 
       (.C(s_axi_aclk),
1346 
        .CE(1'b1),
1347 
        .D(addr_i_p1[0]),
1348 
        .Q(Q[0]),
1349 
        .S(SS));
1350 
  FDSE \INFERRED_GEN.cnt_i_reg[1]
1351 
       (.C(s_axi_aclk),
1352 
        .CE(1'b1),
1353 
        .D(addr_i_p1[1]),
1354 
        .Q(Q[1]),
1355 
        .S(SS));
1356 
  FDSE \INFERRED_GEN.cnt_i_reg[2]
1357 
       (.C(s_axi_aclk),
1358 
        .CE(1'b1),
1359 
        .D(addr_i_p1[2]),
1360 
        .Q(Q[2]),
1361 
        .S(SS));
1362 
  FDSE \INFERRED_GEN.cnt_i_reg[3]
1363 
       (.C(s_axi_aclk),
1364 
        .CE(1'b1),
1365 
        .D(addr_i_p1[3]),
1366 
        .Q(Q[3]),
1367 
        .S(SS));
1368 
  FDSE \INFERRED_GEN.cnt_i_reg[4]
1369 
       (.C(s_axi_aclk),
1370 
        .CE(1'b1),
1371 
        .D(addr_i_p1[4]),
1372 
        .Q(Q[4]),
1373 
        .S(SS));
1374 
  LUT4 #(
1375 
    .INIT(16'h0F02))
1376 
    tx_Start_i_1
1377 
       (.I0(tx_Data_Enable_reg),
1378 
        .I1(Q[4]),
1379 
        .I2(tx_DataBits),
1380 
        .I3(tx_Start),
1381 
        .O(tx_Start0));
1382 
endmodule
1383 
 
1384 
(* ORIG_REF_NAME = "cntr_incr_decr_addn_f" *)
1385 
module axi_uartlite_module_sim_cntr_incr_decr_addn_f_2
1386 
   (SS,
1387 
    fifo_full_p1,
1388 
    Q,
1389 
    Interrupt0,
1390 
    reset_RX_FIFO_reg,
1391 
    s_axi_aresetn,
1392 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
1393 
    Bus_RNW_reg,
1394 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
1395 
    Bus_RNW_reg_reg,
1396 
    fifo_Write,
1397 
    FIFO_Full_reg,
1398 
    valid_rx,
1399 
    rx_Data_Present_Pre,
1400 
    enable_interrupts,
1401 
    \INFERRED_GEN.cnt_i_reg[4]_0 ,
1402 
    tx_Buffer_Empty_Pre,
1403 
    s_axi_aclk);
1404 
  output [0:0]SS;
1405 
  output fifo_full_p1;
1406 
  output [4:0]Q;
1407 
  output Interrupt0;
1408 
  input reset_RX_FIFO_reg;
1409 
  input s_axi_aresetn;
1410 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
1411 
  input Bus_RNW_reg;
1412 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
1413 
  input Bus_RNW_reg_reg;
1414 
  input fifo_Write;
1415 
  input FIFO_Full_reg;
1416 
  input valid_rx;
1417 
  input rx_Data_Present_Pre;
1418 
  input enable_interrupts;
1419 
  input [0:0]\INFERRED_GEN.cnt_i_reg[4]_0 ;
1420 
  input tx_Buffer_Empty_Pre;
1421 
  input s_axi_aclk;
1422 
 
1423 
  wire Bus_RNW_reg;
1424 
  wire Bus_RNW_reg_reg;
1425 
  wire FIFO_Full_i_2_n_0;
1426 
  wire FIFO_Full_reg;
1427 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
1428 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
1429 
  wire \INFERRED_GEN.cnt_i[4]_i_4_n_0 ;
1430 
  wire \INFERRED_GEN.cnt_i[4]_i_5__0_n_0 ;
1431 
  wire \INFERRED_GEN.cnt_i[4]_i_6_n_0 ;
1432 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[4]_0 ;
1433 
  wire Interrupt0;
1434 
  wire [4:0]Q;
1435 
  wire [0:0]SS;
1436 
  wire [4:0]addr_i_p1;
1437 
  wire enable_interrupts;
1438 
  wire fifo_Write;
1439 
  wire fifo_full_p1;
1440 
  wire reset_RX_FIFO_reg;
1441 
  wire rx_Data_Present_Pre;
1442 
  wire s_axi_aclk;
1443 
  wire s_axi_aresetn;
1444 
  wire tx_Buffer_Empty_Pre;
1445 
  wire valid_rx;
1446 
 
1447 
  LUT6 #(
1448 
    .INIT(64'h0000000009040000))
1449 
    FIFO_Full_i_1
1450 
       (.I0(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
1451 
        .I1(Q[0]),
1452 
        .I2(Q[4]),
1453 
        .I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
1454 
        .I4(Q[3]),
1455 
        .I5(FIFO_Full_i_2_n_0),
1456 
        .O(fifo_full_p1));
1457 
  (* SOFT_HLUTNM = "soft_lutpair17" *)
1458 
  LUT2 #(
1459 
    .INIT(4'h7))
1460 
    FIFO_Full_i_2
1461 
       (.I0(Q[1]),
1462 
        .I1(Q[2]),
1463 
        .O(FIFO_Full_i_2_n_0));
1464 
  LUT5 #(
1465 
    .INIT(32'hF70808F7))
1466 
    \INFERRED_GEN.cnt_i[0]_i_1
1467 
       (.I0(Bus_RNW_reg),
1468 
        .I1(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
1469 
        .I2(Q[4]),
1470 
        .I3(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
1471 
        .I4(Q[0]),
1472 
        .O(addr_i_p1[0]));
1473 
  LUT6 #(
1474 
    .INIT(64'hAAAAAA6A5595AAAA))
1475 
    \INFERRED_GEN.cnt_i[1]_i_1
1476 
       (.I0(Q[1]),
1477 
        .I1(Bus_RNW_reg),
1478 
        .I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
1479 
        .I3(Q[4]),
1480 
        .I4(Q[0]),
1481 
        .I5(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
1482 
        .O(addr_i_p1[1]));
1483 
  (* SOFT_HLUTNM = "soft_lutpair17" *)
1484 
  LUT5 #(
1485 
    .INIT(32'hFE017F80))
1486 
    \INFERRED_GEN.cnt_i[2]_i_1
1487 
       (.I0(Q[0]),
1488 
        .I1(Bus_RNW_reg_reg),
1489 
        .I2(Q[1]),
1490 
        .I3(Q[2]),
1491 
        .I4(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
1492 
        .O(addr_i_p1[2]));
1493 
  LUT6 #(
1494 
    .INIT(64'hF0F0F0E178F0F0F0))
1495 
    \INFERRED_GEN.cnt_i[3]_i_1
1496 
       (.I0(Q[0]),
1497 
        .I1(Bus_RNW_reg_reg),
1498 
        .I2(Q[3]),
1499 
        .I3(Q[1]),
1500 
        .I4(Q[2]),
1501 
        .I5(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
1502 
        .O(addr_i_p1[3]));
1503 
  LUT2 #(
1504 
    .INIT(4'hB))
1505 
    \INFERRED_GEN.cnt_i[4]_i_1
1506 
       (.I0(reset_RX_FIFO_reg),
1507 
        .I1(s_axi_aresetn),
1508 
        .O(SS));
1509 
  LUT6 #(
1510 
    .INIT(64'hF0F0F4F4F00AF0F0))
1511 
    \INFERRED_GEN.cnt_i[4]_i_2
1512 
       (.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
1513 
        .I1(\INFERRED_GEN.cnt_i[4]_i_4_n_0 ),
1514 
        .I2(Q[4]),
1515 
        .I3(\INFERRED_GEN.cnt_i[4]_i_5__0_n_0 ),
1516 
        .I4(Q[0]),
1517 
        .I5(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
1518 
        .O(addr_i_p1[4]));
1519 
  (* SOFT_HLUTNM = "soft_lutpair18" *)
1520 
  LUT3 #(
1521 
    .INIT(8'h01))
1522 
    \INFERRED_GEN.cnt_i[4]_i_4
1523 
       (.I0(Q[2]),
1524 
        .I1(Q[1]),
1525 
        .I2(Q[3]),
1526 
        .O(\INFERRED_GEN.cnt_i[4]_i_4_n_0 ));
1527 
  (* SOFT_HLUTNM = "soft_lutpair18" *)
1528 
  LUT3 #(
1529 
    .INIT(8'h7F))
1530 
    \INFERRED_GEN.cnt_i[4]_i_5__0
1531 
       (.I0(Q[2]),
1532 
        .I1(Q[1]),
1533 
        .I2(Q[3]),
1534 
        .O(\INFERRED_GEN.cnt_i[4]_i_5__0_n_0 ));
1535 
  LUT3 #(
1536 
    .INIT(8'hDF))
1537 
    \INFERRED_GEN.cnt_i[4]_i_6
1538 
       (.I0(fifo_Write),
1539 
        .I1(FIFO_Full_reg),
1540 
        .I2(valid_rx),
1541 
        .O(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ));
1542 
  FDSE \INFERRED_GEN.cnt_i_reg[0]
1543 
       (.C(s_axi_aclk),
1544 
        .CE(1'b1),
1545 
        .D(addr_i_p1[0]),
1546 
        .Q(Q[0]),
1547 
        .S(SS));
1548 
  FDSE \INFERRED_GEN.cnt_i_reg[1]
1549 
       (.C(s_axi_aclk),
1550 
        .CE(1'b1),
1551 
        .D(addr_i_p1[1]),
1552 
        .Q(Q[1]),
1553 
        .S(SS));
1554 
  FDSE \INFERRED_GEN.cnt_i_reg[2]
1555 
       (.C(s_axi_aclk),
1556 
        .CE(1'b1),
1557 
        .D(addr_i_p1[2]),
1558 
        .Q(Q[2]),
1559 
        .S(SS));
1560 
  FDSE \INFERRED_GEN.cnt_i_reg[3]
1561 
       (.C(s_axi_aclk),
1562 
        .CE(1'b1),
1563 
        .D(addr_i_p1[3]),
1564 
        .Q(Q[3]),
1565 
        .S(SS));
1566 
  FDSE \INFERRED_GEN.cnt_i_reg[4]
1567 
       (.C(s_axi_aclk),
1568 
        .CE(1'b1),
1569 
        .D(addr_i_p1[4]),
1570 
        .Q(Q[4]),
1571 
        .S(SS));
1572 
  LUT5 #(
1573 
    .INIT(32'h1010F010))
1574 
    Interrupt_i_2
1575 
       (.I0(rx_Data_Present_Pre),
1576 
        .I1(Q[4]),
1577 
        .I2(enable_interrupts),
1578 
        .I3(\INFERRED_GEN.cnt_i_reg[4]_0 ),
1579 
        .I4(tx_Buffer_Empty_Pre),
1580 
        .O(Interrupt0));
1581 
endmodule
1582 
 
1583 
module axi_uartlite_module_sim_dynshreg_f
1584 
   (mux_Out,
1585 
    p_4_in,
1586 
    \mux_sel_reg[2] ,
1587 
    \mux_sel_reg[0] ,
1588 
    fifo_wr,
1589 
    s_axi_wdata,
1590 
    Q,
1591 
    s_axi_aclk);
1592 
  output mux_Out;
1593 
  input p_4_in;
1594 
  input \mux_sel_reg[2] ;
1595 
  input \mux_sel_reg[0] ;
1596 
  input fifo_wr;
1597 
  input [7:0]s_axi_wdata;
1598 
  input [3:0]Q;
1599 
  input s_axi_aclk;
1600 
 
1601 
  wire [3:0]Q;
1602 
  wire [0:7]fifo_DOut;
1603 
  wire fifo_wr;
1604 
  wire mux_Out;
1605 
  wire \mux_sel_reg[0] ;
1606 
  wire \mux_sel_reg[2] ;
1607 
  wire p_4_in;
1608 
  wire s_axi_aclk;
1609 
  wire [7:0]s_axi_wdata;
1610 
  wire serial_Data_i_2_n_0;
1611 
  wire serial_Data_i_3_n_0;
1612 
  wire serial_Data_i_4_n_0;
1613 
  wire serial_Data_i_5_n_0;
1614 
 
1615 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1616 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 " *)
1617 
  SRL16E #(
1618 
    .INIT(16'h0000))
1619 
    \INFERRED_GEN.data_reg[15][0]_srl16
1620 
       (.A0(Q[0]),
1621 
        .A1(Q[1]),
1622 
        .A2(Q[2]),
1623 
        .A3(Q[3]),
1624 
        .CE(fifo_wr),
1625 
        .CLK(s_axi_aclk),
1626 
        .D(s_axi_wdata[7]),
1627 
        .Q(fifo_DOut[0]));
1628 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1629 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 " *)
1630 
  SRL16E #(
1631 
    .INIT(16'h0000))
1632 
    \INFERRED_GEN.data_reg[15][1]_srl16
1633 
       (.A0(Q[0]),
1634 
        .A1(Q[1]),
1635 
        .A2(Q[2]),
1636 
        .A3(Q[3]),
1637 
        .CE(fifo_wr),
1638 
        .CLK(s_axi_aclk),
1639 
        .D(s_axi_wdata[6]),
1640 
        .Q(fifo_DOut[1]));
1641 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1642 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 " *)
1643 
  SRL16E #(
1644 
    .INIT(16'h0000))
1645 
    \INFERRED_GEN.data_reg[15][2]_srl16
1646 
       (.A0(Q[0]),
1647 
        .A1(Q[1]),
1648 
        .A2(Q[2]),
1649 
        .A3(Q[3]),
1650 
        .CE(fifo_wr),
1651 
        .CLK(s_axi_aclk),
1652 
        .D(s_axi_wdata[5]),
1653 
        .Q(fifo_DOut[2]));
1654 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1655 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 " *)
1656 
  SRL16E #(
1657 
    .INIT(16'h0000))
1658 
    \INFERRED_GEN.data_reg[15][3]_srl16
1659 
       (.A0(Q[0]),
1660 
        .A1(Q[1]),
1661 
        .A2(Q[2]),
1662 
        .A3(Q[3]),
1663 
        .CE(fifo_wr),
1664 
        .CLK(s_axi_aclk),
1665 
        .D(s_axi_wdata[4]),
1666 
        .Q(fifo_DOut[3]));
1667 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1668 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 " *)
1669 
  SRL16E #(
1670 
    .INIT(16'h0000))
1671 
    \INFERRED_GEN.data_reg[15][4]_srl16
1672 
       (.A0(Q[0]),
1673 
        .A1(Q[1]),
1674 
        .A2(Q[2]),
1675 
        .A3(Q[3]),
1676 
        .CE(fifo_wr),
1677 
        .CLK(s_axi_aclk),
1678 
        .D(s_axi_wdata[3]),
1679 
        .Q(fifo_DOut[4]));
1680 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1681 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 " *)
1682 
  SRL16E #(
1683 
    .INIT(16'h0000))
1684 
    \INFERRED_GEN.data_reg[15][5]_srl16
1685 
       (.A0(Q[0]),
1686 
        .A1(Q[1]),
1687 
        .A2(Q[2]),
1688 
        .A3(Q[3]),
1689 
        .CE(fifo_wr),
1690 
        .CLK(s_axi_aclk),
1691 
        .D(s_axi_wdata[2]),
1692 
        .Q(fifo_DOut[5]));
1693 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1694 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 " *)
1695 
  SRL16E #(
1696 
    .INIT(16'h0000))
1697 
    \INFERRED_GEN.data_reg[15][6]_srl16
1698 
       (.A0(Q[0]),
1699 
        .A1(Q[1]),
1700 
        .A2(Q[2]),
1701 
        .A3(Q[3]),
1702 
        .CE(fifo_wr),
1703 
        .CLK(s_axi_aclk),
1704 
        .D(s_axi_wdata[1]),
1705 
        .Q(fifo_DOut[6]));
1706 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1707 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 " *)
1708 
  SRL16E #(
1709 
    .INIT(16'h0000))
1710 
    \INFERRED_GEN.data_reg[15][7]_srl16
1711 
       (.A0(Q[0]),
1712 
        .A1(Q[1]),
1713 
        .A2(Q[2]),
1714 
        .A3(Q[3]),
1715 
        .CE(fifo_wr),
1716 
        .CLK(s_axi_aclk),
1717 
        .D(s_axi_wdata[0]),
1718 
        .Q(fifo_DOut[7]));
1719 
  LUT4 #(
1720 
    .INIT(16'hFFFE))
1721 
    serial_Data_i_1
1722 
       (.I0(serial_Data_i_2_n_0),
1723 
        .I1(serial_Data_i_3_n_0),
1724 
        .I2(serial_Data_i_4_n_0),
1725 
        .I3(serial_Data_i_5_n_0),
1726 
        .O(mux_Out));
1727 
  LUT5 #(
1728 
    .INIT(32'h44400040))
1729 
    serial_Data_i_2
1730 
       (.I0(\mux_sel_reg[2] ),
1731 
        .I1(p_4_in),
1732 
        .I2(fifo_DOut[2]),
1733 
        .I3(\mux_sel_reg[0] ),
1734 
        .I4(fifo_DOut[6]),
1735 
        .O(serial_Data_i_2_n_0));
1736 
  LUT5 #(
1737 
    .INIT(32'h88800080))
1738 
    serial_Data_i_3
1739 
       (.I0(\mux_sel_reg[0] ),
1740 
        .I1(\mux_sel_reg[2] ),
1741 
        .I2(fifo_DOut[5]),
1742 
        .I3(p_4_in),
1743 
        .I4(fifo_DOut[7]),
1744 
        .O(serial_Data_i_3_n_0));
1745 
  LUT5 #(
1746 
    .INIT(32'h44400040))
1747 
    serial_Data_i_4
1748 
       (.I0(\mux_sel_reg[0] ),
1749 
        .I1(\mux_sel_reg[2] ),
1750 
        .I2(fifo_DOut[1]),
1751 
        .I3(p_4_in),
1752 
        .I4(fifo_DOut[3]),
1753 
        .O(serial_Data_i_4_n_0));
1754 
  LUT5 #(
1755 
    .INIT(32'h000A000C))
1756 
    serial_Data_i_5
1757 
       (.I0(fifo_DOut[4]),
1758 
        .I1(fifo_DOut[0]),
1759 
        .I2(p_4_in),
1760 
        .I3(\mux_sel_reg[2] ),
1761 
        .I4(\mux_sel_reg[0] ),
1762 
        .O(serial_Data_i_5_n_0));
1763 
endmodule
1764 
 
1765 
(* ORIG_REF_NAME = "dynshreg_f" *)
1766 
module axi_uartlite_module_sim_dynshreg_f_3
1767 
   (out,
1768 
    valid_rx,
1769 
    FIFO_Full_reg,
1770 
    fifo_Write,
1771 
    in,
1772 
    Q,
1773 
    s_axi_aclk);
1774 
  output [7:0]out;
1775 
  input valid_rx;
1776 
  input FIFO_Full_reg;
1777 
  input fifo_Write;
1778 
  input [0:7]in;
1779 
  input [3:0]Q;
1780 
  input s_axi_aclk;
1781 
 
1782 
  wire FIFO_Full_reg;
1783 
  wire [3:0]Q;
1784 
  wire fifo_Write;
1785 
  wire fifo_wr;
1786 
  wire [0:7]in;
1787 
  wire [7:0]out;
1788 
  wire s_axi_aclk;
1789 
  wire valid_rx;
1790 
 
1791 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1792 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 " *)
1793 
  SRL16E #(
1794 
    .INIT(16'h0000))
1795 
    \INFERRED_GEN.data_reg[15][0]_srl16
1796 
       (.A0(Q[0]),
1797 
        .A1(Q[1]),
1798 
        .A2(Q[2]),
1799 
        .A3(Q[3]),
1800 
        .CE(fifo_wr),
1801 
        .CLK(s_axi_aclk),
1802 
        .D(in[0]),
1803 
        .Q(out[7]));
1804 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1805 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 " *)
1806 
  SRL16E #(
1807 
    .INIT(16'h0000))
1808 
    \INFERRED_GEN.data_reg[15][1]_srl16
1809 
       (.A0(Q[0]),
1810 
        .A1(Q[1]),
1811 
        .A2(Q[2]),
1812 
        .A3(Q[3]),
1813 
        .CE(fifo_wr),
1814 
        .CLK(s_axi_aclk),
1815 
        .D(in[1]),
1816 
        .Q(out[6]));
1817 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1818 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 " *)
1819 
  SRL16E #(
1820 
    .INIT(16'h0000))
1821 
    \INFERRED_GEN.data_reg[15][2]_srl16
1822 
       (.A0(Q[0]),
1823 
        .A1(Q[1]),
1824 
        .A2(Q[2]),
1825 
        .A3(Q[3]),
1826 
        .CE(fifo_wr),
1827 
        .CLK(s_axi_aclk),
1828 
        .D(in[2]),
1829 
        .Q(out[5]));
1830 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1831 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 " *)
1832 
  SRL16E #(
1833 
    .INIT(16'h0000))
1834 
    \INFERRED_GEN.data_reg[15][3]_srl16
1835 
       (.A0(Q[0]),
1836 
        .A1(Q[1]),
1837 
        .A2(Q[2]),
1838 
        .A3(Q[3]),
1839 
        .CE(fifo_wr),
1840 
        .CLK(s_axi_aclk),
1841 
        .D(in[3]),
1842 
        .Q(out[4]));
1843 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1844 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 " *)
1845 
  SRL16E #(
1846 
    .INIT(16'h0000))
1847 
    \INFERRED_GEN.data_reg[15][4]_srl16
1848 
       (.A0(Q[0]),
1849 
        .A1(Q[1]),
1850 
        .A2(Q[2]),
1851 
        .A3(Q[3]),
1852 
        .CE(fifo_wr),
1853 
        .CLK(s_axi_aclk),
1854 
        .D(in[4]),
1855 
        .Q(out[3]));
1856 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1857 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 " *)
1858 
  SRL16E #(
1859 
    .INIT(16'h0000))
1860 
    \INFERRED_GEN.data_reg[15][5]_srl16
1861 
       (.A0(Q[0]),
1862 
        .A1(Q[1]),
1863 
        .A2(Q[2]),
1864 
        .A3(Q[3]),
1865 
        .CE(fifo_wr),
1866 
        .CLK(s_axi_aclk),
1867 
        .D(in[5]),
1868 
        .Q(out[2]));
1869 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1870 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 " *)
1871 
  SRL16E #(
1872 
    .INIT(16'h0000))
1873 
    \INFERRED_GEN.data_reg[15][6]_srl16
1874 
       (.A0(Q[0]),
1875 
        .A1(Q[1]),
1876 
        .A2(Q[2]),
1877 
        .A3(Q[3]),
1878 
        .CE(fifo_wr),
1879 
        .CLK(s_axi_aclk),
1880 
        .D(in[6]),
1881 
        .Q(out[1]));
1882 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
1883 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 " *)
1884 
  SRL16E #(
1885 
    .INIT(16'h0000))
1886 
    \INFERRED_GEN.data_reg[15][7]_srl16
1887 
       (.A0(Q[0]),
1888 
        .A1(Q[1]),
1889 
        .A2(Q[2]),
1890 
        .A3(Q[3]),
1891 
        .CE(fifo_wr),
1892 
        .CLK(s_axi_aclk),
1893 
        .D(in[7]),
1894 
        .Q(out[0]));
1895 
  LUT3 #(
1896 
    .INIT(8'h20))
1897 
    \INFERRED_GEN.data_reg[15][7]_srl16_i_1__0
1898 
       (.I0(valid_rx),
1899 
        .I1(FIFO_Full_reg),
1900 
        .I2(fifo_Write),
1901 
        .O(fifo_wr));
1902 
endmodule
1903 
 
1904 
module axi_uartlite_module_sim_dynshreg_i_f
1905 
   (p_20_out,
1906 
    \SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ,
1907 
    p_17_out,
1908 
    p_14_out,
1909 
    p_11_out,
1910 
    p_8_out,
1911 
    p_5_out,
1912 
    p_2_out,
1913 
    status_reg_reg0,
1914 
    fifo_Write0,
1915 
    stop_Bit_Position_reg,
1916 
    frame_err_ocrd_reg,
1917 
    running_reg,
1918 
    en_16x_Baud,
1919 
    s_axi_aclk,
1920 
    in,
1921 
    start_Edge_Detected,
1922 
    s_axi_aresetn,
1923 
    stop_Bit_Position_reg_0,
1924 
    scndry_out,
1925 
    status_reg,
1926 
    clr_Status,
1927 
    valid_rx,
1928 
    frame_err_ocrd,
1929 
    running_reg_0);
1930 
  output p_20_out;
1931 
  output \SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ;
1932 
  output p_17_out;
1933 
  output p_14_out;
1934 
  output p_11_out;
1935 
  output p_8_out;
1936 
  output p_5_out;
1937 
  output p_2_out;
1938 
  output status_reg_reg0;
1939 
  output fifo_Write0;
1940 
  output stop_Bit_Position_reg;
1941 
  output frame_err_ocrd_reg;
1942 
  output running_reg;
1943 
  input en_16x_Baud;
1944 
  input s_axi_aclk;
1945 
  input [0:7]in;
1946 
  input start_Edge_Detected;
1947 
  input s_axi_aresetn;
1948 
  input stop_Bit_Position_reg_0;
1949 
  input scndry_out;
1950 
  input [0:0]status_reg;
1951 
  input clr_Status;
1952 
  input valid_rx;
1953 
  input frame_err_ocrd;
1954 
  input running_reg_0;
1955 
 
1956 
  wire \INFERRED_GEN.data_reg[14][0]_srl15_n_0 ;
1957 
  wire \INFERRED_GEN.data_reg[15] ;
1958 
  wire \SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ;
1959 
  wire clr_Status;
1960 
  wire en_16x_Baud;
1961 
  wire fifo_Write0;
1962 
  wire frame_err_ocrd;
1963 
  wire frame_err_ocrd_reg;
1964 
  wire [0:7]in;
1965 
  wire p_11_out;
1966 
  wire p_14_out;
1967 
  wire p_17_out;
1968 
  wire p_20_out;
1969 
  wire p_2_out;
1970 
  wire p_5_out;
1971 
  wire p_8_out;
1972 
  wire recycle;
1973 
  wire running_reg;
1974 
  wire running_reg_0;
1975 
  wire s_axi_aclk;
1976 
  wire s_axi_aresetn;
1977 
  wire scndry_out;
1978 
  wire start_Edge_Detected;
1979 
  wire [0:0]status_reg;
1980 
  wire \status_reg[1]_i_2_n_0 ;
1981 
  wire status_reg_reg0;
1982 
  wire stop_Bit_Position_reg;
1983 
  wire stop_Bit_Position_reg_0;
1984 
  wire valid_rx;
1985 
 
1986 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14] " *)
1987 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15 " *)
1988 
  SRL16E #(
1989 
    .INIT(16'h0000))
1990 
    \INFERRED_GEN.data_reg[14][0]_srl15
1991 
       (.A0(1'b0),
1992 
        .A1(1'b1),
1993 
        .A2(1'b1),
1994 
        .A3(1'b1),
1995 
        .CE(en_16x_Baud),
1996 
        .CLK(s_axi_aclk),
1997 
        .D(recycle),
1998 
        .Q(\INFERRED_GEN.data_reg[14][0]_srl15_n_0 ));
1999 
  (* SOFT_HLUTNM = "soft_lutpair16" *)
2000 
  LUT4 #(
2001 
    .INIT(16'h4440))
2002 
    \INFERRED_GEN.data_reg[14][0]_srl15_i_1
2003 
       (.I0(stop_Bit_Position_reg_0),
2004 
        .I1(valid_rx),
2005 
        .I2(\INFERRED_GEN.data_reg[15] ),
2006 
        .I3(start_Edge_Detected),
2007 
        .O(recycle));
2008 
  FDRE #(
2009 
    .INIT(1'b0))
2010 
    \INFERRED_GEN.data_reg[15][0]
2011 
       (.C(s_axi_aclk),
2012 
        .CE(en_16x_Baud),
2013 
        .D(\INFERRED_GEN.data_reg[14][0]_srl15_n_0 ),
2014 
        .Q(\INFERRED_GEN.data_reg[15] ),
2015 
        .R(1'b0));
2016 
  LUT5 #(
2017 
    .INIT(32'h0A000C00))
2018 
    \SERIAL_TO_PARALLEL[2].fifo_din[2]_i_1
2019 
       (.I0(in[1]),
2020 
        .I1(in[0]),
2021 
        .I2(start_Edge_Detected),
2022 
        .I3(s_axi_aresetn),
2023 
        .I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
2024 
        .O(p_20_out));
2025 
  LUT5 #(
2026 
    .INIT(32'h0A000C00))
2027 
    \SERIAL_TO_PARALLEL[3].fifo_din[3]_i_1
2028 
       (.I0(in[2]),
2029 
        .I1(in[1]),
2030 
        .I2(start_Edge_Detected),
2031 
        .I3(s_axi_aresetn),
2032 
        .I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
2033 
        .O(p_17_out));
2034 
  LUT5 #(
2035 
    .INIT(32'h0A000C00))
2036 
    \SERIAL_TO_PARALLEL[4].fifo_din[4]_i_1
2037 
       (.I0(in[3]),
2038 
        .I1(in[2]),
2039 
        .I2(start_Edge_Detected),
2040 
        .I3(s_axi_aresetn),
2041 
        .I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
2042 
        .O(p_14_out));
2043 
  LUT5 #(
2044 
    .INIT(32'h0A000C00))
2045 
    \SERIAL_TO_PARALLEL[5].fifo_din[5]_i_1
2046 
       (.I0(in[4]),
2047 
        .I1(in[3]),
2048 
        .I2(start_Edge_Detected),
2049 
        .I3(s_axi_aresetn),
2050 
        .I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
2051 
        .O(p_11_out));
2052 
  LUT5 #(
2053 
    .INIT(32'h0A000C00))
2054 
    \SERIAL_TO_PARALLEL[6].fifo_din[6]_i_1
2055 
       (.I0(in[5]),
2056 
        .I1(in[4]),
2057 
        .I2(start_Edge_Detected),
2058 
        .I3(s_axi_aresetn),
2059 
        .I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
2060 
        .O(p_8_out));
2061 
  LUT5 #(
2062 
    .INIT(32'h0A000C00))
2063 
    \SERIAL_TO_PARALLEL[7].fifo_din[7]_i_1
2064 
       (.I0(in[6]),
2065 
        .I1(in[5]),
2066 
        .I2(start_Edge_Detected),
2067 
        .I3(s_axi_aresetn),
2068 
        .I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
2069 
        .O(p_5_out));
2070 
  LUT5 #(
2071 
    .INIT(32'h0A000C00))
2072 
    \SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1
2073 
       (.I0(in[7]),
2074 
        .I1(in[6]),
2075 
        .I2(start_Edge_Detected),
2076 
        .I3(s_axi_aresetn),
2077 
        .I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
2078 
        .O(p_2_out));
2079 
  (* SOFT_HLUTNM = "soft_lutpair14" *)
2080 
  LUT3 #(
2081 
    .INIT(8'hF7))
2082 
    \SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2
2083 
       (.I0(en_16x_Baud),
2084 
        .I1(\INFERRED_GEN.data_reg[15] ),
2085 
        .I2(stop_Bit_Position_reg_0),
2086 
        .O(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ));
2087 
  (* SOFT_HLUTNM = "soft_lutpair15" *)
2088 
  LUT4 #(
2089 
    .INIT(16'h8000))
2090 
    fifo_Write_i_1
2091 
       (.I0(\INFERRED_GEN.data_reg[15] ),
2092 
        .I1(en_16x_Baud),
2093 
        .I2(stop_Bit_Position_reg_0),
2094 
        .I3(scndry_out),
2095 
        .O(fifo_Write0));
2096 
  (* SOFT_HLUTNM = "soft_lutpair15" *)
2097 
  LUT5 #(
2098 
    .INIT(32'h00FF0080))
2099 
    frame_err_ocrd_i_1
2100 
       (.I0(\INFERRED_GEN.data_reg[15] ),
2101 
        .I1(en_16x_Baud),
2102 
        .I2(stop_Bit_Position_reg_0),
2103 
        .I3(scndry_out),
2104 
        .I4(frame_err_ocrd),
2105 
        .O(frame_err_ocrd_reg));
2106 
  (* SOFT_HLUTNM = "soft_lutpair14" *)
2107 
  LUT5 #(
2108 
    .INIT(32'hBFFFA0A0))
2109 
    running_i_1
2110 
       (.I0(start_Edge_Detected),
2111 
        .I1(\INFERRED_GEN.data_reg[15] ),
2112 
        .I2(en_16x_Baud),
2113 
        .I3(stop_Bit_Position_reg_0),
2114 
        .I4(running_reg_0),
2115 
        .O(running_reg));
2116 
  LUT5 #(
2117 
    .INIT(32'h0000F200))
2118 
    \status_reg[1]_i_1
2119 
       (.I0(\status_reg[1]_i_2_n_0 ),
2120 
        .I1(scndry_out),
2121 
        .I2(status_reg),
2122 
        .I3(s_axi_aresetn),
2123 
        .I4(clr_Status),
2124 
        .O(status_reg_reg0));
2125 
  (* SOFT_HLUTNM = "soft_lutpair16" *)
2126 
  LUT3 #(
2127 
    .INIT(8'h80))
2128 
    \status_reg[1]_i_2
2129 
       (.I0(stop_Bit_Position_reg_0),
2130 
        .I1(en_16x_Baud),
2131 
        .I2(\INFERRED_GEN.data_reg[15] ),
2132 
        .O(\status_reg[1]_i_2_n_0 ));
2133 
  LUT4 #(
2134 
    .INIT(16'h2CCC))
2135 
    stop_Bit_Position_i_1
2136 
       (.I0(in[7]),
2137 
        .I1(stop_Bit_Position_reg_0),
2138 
        .I2(en_16x_Baud),
2139 
        .I3(\INFERRED_GEN.data_reg[15] ),
2140 
        .O(stop_Bit_Position_reg));
2141 
endmodule
2142 
 
2143 
(* ORIG_REF_NAME = "dynshreg_i_f" *)
2144 
module axi_uartlite_module_sim_dynshreg_i_f__parameterized0
2145 
   (tx_Data_Enable_reg,
2146 
    en_16x_Baud,
2147 
    s_axi_aclk,
2148 
    tx_Data_Enable_reg_0);
2149 
  output tx_Data_Enable_reg;
2150 
  input en_16x_Baud;
2151 
  input s_axi_aclk;
2152 
  input tx_Data_Enable_reg_0;
2153 
 
2154 
  wire \INFERRED_GEN.data_reg[14][0]_srl15_n_0 ;
2155 
  wire \INFERRED_GEN.data_reg_n_0_[15][0] ;
2156 
  wire en_16x_Baud;
2157 
  wire s_axi_aclk;
2158 
  wire tx_Data_Enable_reg;
2159 
  wire tx_Data_Enable_reg_0;
2160 
 
2161 
  (* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14] " *)
2162 
  (* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15 " *)
2163 
  SRL16E #(
2164 
    .INIT(16'h0001))
2165 
    \INFERRED_GEN.data_reg[14][0]_srl15
2166 
       (.A0(1'b0),
2167 
        .A1(1'b1),
2168 
        .A2(1'b1),
2169 
        .A3(1'b1),
2170 
        .CE(en_16x_Baud),
2171 
        .CLK(s_axi_aclk),
2172 
        .D(\INFERRED_GEN.data_reg_n_0_[15][0] ),
2173 
        .Q(\INFERRED_GEN.data_reg[14][0]_srl15_n_0 ));
2174 
  FDRE #(
2175 
    .INIT(1'b0))
2176 
    \INFERRED_GEN.data_reg[15][0]
2177 
       (.C(s_axi_aclk),
2178 
        .CE(en_16x_Baud),
2179 
        .D(\INFERRED_GEN.data_reg[14][0]_srl15_n_0 ),
2180 
        .Q(\INFERRED_GEN.data_reg_n_0_[15][0] ),
2181 
        .R(1'b0));
2182 
  LUT3 #(
2183 
    .INIT(8'h20))
2184 
    tx_Data_Enable_i_1
2185 
       (.I0(\INFERRED_GEN.data_reg_n_0_[15][0] ),
2186 
        .I1(tx_Data_Enable_reg_0),
2187 
        .I2(en_16x_Baud),
2188 
        .O(tx_Data_Enable_reg));
2189 
endmodule
2190 
 
2191 
module axi_uartlite_module_sim_pselect_f
2192 
   (ce_expnd_i_3,
2193 
    \bus2ip_addr_i_reg[2] ,
2194 
    \bus2ip_addr_i_reg[3] );
2195 
  output ce_expnd_i_3;
2196 
  input \bus2ip_addr_i_reg[2] ;
2197 
  input \bus2ip_addr_i_reg[3] ;
2198 
 
2199 
  wire \bus2ip_addr_i_reg[2] ;
2200 
  wire \bus2ip_addr_i_reg[3] ;
2201 
  wire ce_expnd_i_3;
2202 
 
2203 
  LUT2 #(
2204 
    .INIT(4'h1))
2205 
    CS
2206 
       (.I0(\bus2ip_addr_i_reg[2] ),
2207 
        .I1(\bus2ip_addr_i_reg[3] ),
2208 
        .O(ce_expnd_i_3));
2209 
endmodule
2210 
 
2211 
(* ORIG_REF_NAME = "pselect_f" *)
2212 
module axi_uartlite_module_sim_pselect_f__parameterized1
2213 
   (ce_expnd_i_1,
2214 
    \bus2ip_addr_i_reg[3] ,
2215 
    \bus2ip_addr_i_reg[2] );
2216 
  output ce_expnd_i_1;
2217 
  input \bus2ip_addr_i_reg[3] ;
2218 
  input \bus2ip_addr_i_reg[2] ;
2219 
 
2220 
  wire \bus2ip_addr_i_reg[2] ;
2221 
  wire \bus2ip_addr_i_reg[3] ;
2222 
  wire ce_expnd_i_1;
2223 
 
2224 
  LUT2 #(
2225 
    .INIT(4'h2))
2226 
    CS
2227 
       (.I0(\bus2ip_addr_i_reg[3] ),
2228 
        .I1(\bus2ip_addr_i_reg[2] ),
2229 
        .O(ce_expnd_i_1));
2230 
endmodule
2231 
 
2232 
module axi_uartlite_module_sim_slave_attachment
2233 
   (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
2234 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
2235 
    s_axi_rresp,
2236 
    enable_interrupts_reg,
2237 
    s_axi_rvalid,
2238 
    s_axi_bvalid,
2239 
    s_axi_bresp,
2240 
    reset_TX_FIFO,
2241 
    reset_RX_FIFO,
2242 
    s_axi_awready,
2243 
    s_axi_arready,
2244 
    \INFERRED_GEN.cnt_i_reg[2] ,
2245 
    rx_Data_Present_Pre_reg,
2246 
    FIFO_Full_reg,
2247 
    bus2ip_rdce,
2248 
    fifo_wr,
2249 
    \INFERRED_GEN.cnt_i_reg[2]_0 ,
2250 
    tx_Buffer_Empty_Pre_reg,
2251 
    enable_interrupts_reg_0,
2252 
    s_axi_rdata,
2253 
    bus2ip_reset,
2254 
    s_axi_aclk,
2255 
    s_axi_wdata,
2256 
    s_axi_arvalid,
2257 
    s_axi_aresetn,
2258 
    Q,
2259 
    out,
2260 
    rx_Buffer_Full,
2261 
    \INFERRED_GEN.cnt_i_reg[4] ,
2262 
    tx_Buffer_Full,
2263 
    enable_interrupts,
2264 
    status_reg,
2265 
    s_axi_awvalid,
2266 
    s_axi_wvalid,
2267 
    s_axi_rready,
2268 
    s_axi_bready,
2269 
    s_axi_awaddr,
2270 
    s_axi_araddr);
2271 
  output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
2272 
  output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
2273 
  output [0:0]s_axi_rresp;
2274 
  output enable_interrupts_reg;
2275 
  output s_axi_rvalid;
2276 
  output s_axi_bvalid;
2277 
  output [0:0]s_axi_bresp;
2278 
  output reset_TX_FIFO;
2279 
  output reset_RX_FIFO;
2280 
  output s_axi_awready;
2281 
  output s_axi_arready;
2282 
  output \INFERRED_GEN.cnt_i_reg[2] ;
2283 
  output rx_Data_Present_Pre_reg;
2284 
  output FIFO_Full_reg;
2285 
  output [0:0]bus2ip_rdce;
2286 
  output fifo_wr;
2287 
  output \INFERRED_GEN.cnt_i_reg[2]_0 ;
2288 
  output tx_Buffer_Empty_Pre_reg;
2289 
  output enable_interrupts_reg_0;
2290 
  output [7:0]s_axi_rdata;
2291 
  input bus2ip_reset;
2292 
  input s_axi_aclk;
2293 
  input [2:0]s_axi_wdata;
2294 
  input s_axi_arvalid;
2295 
  input s_axi_aresetn;
2296 
  input [0:0]Q;
2297 
  input [7:0]out;
2298 
  input rx_Buffer_Full;
2299 
  input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
2300 
  input tx_Buffer_Full;
2301 
  input enable_interrupts;
2302 
  input [1:0]status_reg;
2303 
  input s_axi_awvalid;
2304 
  input s_axi_wvalid;
2305 
  input s_axi_rready;
2306 
  input s_axi_bready;
2307 
  input [1:0]s_axi_awaddr;
2308 
  input [1:0]s_axi_araddr;
2309 
 
2310 
  wire FIFO_Full_reg;
2311 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
2312 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
2313 
  wire \INFERRED_GEN.cnt_i_reg[2] ;
2314 
  wire \INFERRED_GEN.cnt_i_reg[2]_0 ;
2315 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
2316 
  wire I_DECODER_n_26;
2317 
  wire I_DECODER_n_27;
2318 
  wire I_DECODER_n_28;
2319 
  wire I_DECODER_n_5;
2320 
  wire I_DECODER_n_6;
2321 
  wire [0:0]Q;
2322 
  wire [0:7]SIn_DBus;
2323 
  wire \bus2ip_addr_i[2]_i_1_n_0 ;
2324 
  wire \bus2ip_addr_i[3]_i_1_n_0 ;
2325 
  wire \bus2ip_addr_i[3]_i_2_n_0 ;
2326 
  wire \bus2ip_addr_i_reg_n_0_[2] ;
2327 
  wire \bus2ip_addr_i_reg_n_0_[3] ;
2328 
  wire [0:0]bus2ip_rdce;
2329 
  wire bus2ip_reset;
2330 
  wire bus2ip_rnw_i;
2331 
  wire bus2ip_rnw_i_i_1_n_0;
2332 
  wire enable_interrupts;
2333 
  wire enable_interrupts_reg;
2334 
  wire enable_interrupts_reg_0;
2335 
  wire fifo_wr;
2336 
  wire ip2bus_error;
2337 
  wire [7:0]out;
2338 
  wire reset_RX_FIFO;
2339 
  wire reset_TX_FIFO;
2340 
  wire rst;
2341 
  wire rx_Buffer_Full;
2342 
  wire rx_Data_Present_Pre_reg;
2343 
  wire s_axi_aclk;
2344 
  wire [1:0]s_axi_araddr;
2345 
  wire s_axi_aresetn;
2346 
  wire s_axi_arready;
2347 
  wire s_axi_arvalid;
2348 
  wire [1:0]s_axi_awaddr;
2349 
  wire s_axi_awready;
2350 
  wire s_axi_awvalid;
2351 
  wire s_axi_bready;
2352 
  wire [0:0]s_axi_bresp;
2353 
  wire s_axi_bvalid;
2354 
  wire [7:0]s_axi_rdata;
2355 
  wire s_axi_rdata_i;
2356 
  wire s_axi_rready;
2357 
  wire [0:0]s_axi_rresp;
2358 
  wire s_axi_rvalid;
2359 
  wire [2:0]s_axi_wdata;
2360 
  wire s_axi_wvalid;
2361 
  wire start2;
2362 
  wire start2_i_1_n_0;
2363 
  wire [1:0]state;
2364 
  wire \state[0]_i_2_n_0 ;
2365 
  wire \state[1]_i_2_n_0 ;
2366 
  wire \state[1]_i_3_n_0 ;
2367 
  wire [1:0]status_reg;
2368 
  wire tx_Buffer_Empty_Pre_reg;
2369 
  wire tx_Buffer_Full;
2370 
 
2371 
  axi_uartlite_module_sim_address_decoder I_DECODER
2372 
       (.D({I_DECODER_n_5,I_DECODER_n_6}),
2373 
        .FIFO_Full_reg(FIFO_Full_reg),
2374 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
2375 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
2376 
        .\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
2377 
        .\INFERRED_GEN.cnt_i_reg[2]_0 (\INFERRED_GEN.cnt_i_reg[2]_0 ),
2378 
        .\INFERRED_GEN.cnt_i_reg[4] (Q),
2379 
        .\INFERRED_GEN.cnt_i_reg[4]_0 (\INFERRED_GEN.cnt_i_reg[4] ),
2380 
        .Q(state),
2381 
        .\bus2ip_addr_i_reg[2] (\bus2ip_addr_i_reg_n_0_[2] ),
2382 
        .\bus2ip_addr_i_reg[3] (\bus2ip_addr_i_reg_n_0_[3] ),
2383 
        .bus2ip_rdce(bus2ip_rdce),
2384 
        .bus2ip_rnw_i(bus2ip_rnw_i),
2385 
        .enable_interrupts(enable_interrupts),
2386 
        .enable_interrupts_reg(enable_interrupts_reg),
2387 
        .enable_interrupts_reg_0(enable_interrupts_reg_0),
2388 
        .fifo_wr(fifo_wr),
2389 
        .ip2bus_error(ip2bus_error),
2390 
        .out(out),
2391 
        .reset_RX_FIFO(reset_RX_FIFO),
2392 
        .reset_TX_FIFO(reset_TX_FIFO),
2393 
        .rx_Buffer_Full(rx_Buffer_Full),
2394 
        .rx_Data_Present_Pre_reg(rx_Data_Present_Pre_reg),
2395 
        .s_axi_aclk(s_axi_aclk),
2396 
        .s_axi_aresetn(s_axi_aresetn),
2397 
        .s_axi_arready(s_axi_arready),
2398 
        .s_axi_arvalid(s_axi_arvalid),
2399 
        .s_axi_awready(s_axi_awready),
2400 
        .s_axi_bready(s_axi_bready),
2401 
        .s_axi_bresp(s_axi_bresp),
2402 
        .\s_axi_bresp_i_reg[1] (I_DECODER_n_28),
2403 
        .s_axi_bvalid_i_reg(I_DECODER_n_27),
2404 
        .s_axi_bvalid_i_reg_0(s_axi_bvalid),
2405 
        .\s_axi_rdata_i_reg[7] ({SIn_DBus[0],SIn_DBus[1],SIn_DBus[2],SIn_DBus[3],SIn_DBus[4],SIn_DBus[5],SIn_DBus[6],SIn_DBus[7]}),
2406 
        .s_axi_rready(s_axi_rready),
2407 
        .s_axi_rvalid_i_reg(I_DECODER_n_26),
2408 
        .s_axi_rvalid_i_reg_0(s_axi_rvalid),
2409 
        .s_axi_wdata(s_axi_wdata),
2410 
        .s_axi_wvalid(\state[1]_i_3_n_0 ),
2411 
        .start2(start2),
2412 
        .\state_reg[0] (\state[0]_i_2_n_0 ),
2413 
        .\state_reg[1] (\state[1]_i_2_n_0 ),
2414 
        .status_reg(status_reg),
2415 
        .tx_Buffer_Empty_Pre_reg(tx_Buffer_Empty_Pre_reg),
2416 
        .tx_Buffer_Full(tx_Buffer_Full));
2417 
  LUT5 #(
2418 
    .INIT(32'hB8FFB800))
2419 
    \bus2ip_addr_i[2]_i_1
2420 
       (.I0(s_axi_awaddr[0]),
2421 
        .I1(\bus2ip_addr_i[3]_i_2_n_0 ),
2422 
        .I2(s_axi_araddr[0]),
2423 
        .I3(start2_i_1_n_0),
2424 
        .I4(\bus2ip_addr_i_reg_n_0_[2] ),
2425 
        .O(\bus2ip_addr_i[2]_i_1_n_0 ));
2426 
  LUT5 #(
2427 
    .INIT(32'hB8FFB800))
2428 
    \bus2ip_addr_i[3]_i_1
2429 
       (.I0(s_axi_awaddr[1]),
2430 
        .I1(\bus2ip_addr_i[3]_i_2_n_0 ),
2431 
        .I2(s_axi_araddr[1]),
2432 
        .I3(start2_i_1_n_0),
2433 
        .I4(\bus2ip_addr_i_reg_n_0_[3] ),
2434 
        .O(\bus2ip_addr_i[3]_i_1_n_0 ));
2435 
  (* SOFT_HLUTNM = "soft_lutpair9" *)
2436 
  LUT3 #(
2437 
    .INIT(8'hEF))
2438 
    \bus2ip_addr_i[3]_i_2
2439 
       (.I0(state[1]),
2440 
        .I1(state[0]),
2441 
        .I2(s_axi_arvalid),
2442 
        .O(\bus2ip_addr_i[3]_i_2_n_0 ));
2443 
  FDRE \bus2ip_addr_i_reg[2]
2444 
       (.C(s_axi_aclk),
2445 
        .CE(1'b1),
2446 
        .D(\bus2ip_addr_i[2]_i_1_n_0 ),
2447 
        .Q(\bus2ip_addr_i_reg_n_0_[2] ),
2448 
        .R(rst));
2449 
  FDRE \bus2ip_addr_i_reg[3]
2450 
       (.C(s_axi_aclk),
2451 
        .CE(1'b1),
2452 
        .D(\bus2ip_addr_i[3]_i_1_n_0 ),
2453 
        .Q(\bus2ip_addr_i_reg_n_0_[3] ),
2454 
        .R(rst));
2455 
  LUT6 #(
2456 
    .INIT(64'hFFFFFFF7000000F0))
2457 
    bus2ip_rnw_i_i_1
2458 
       (.I0(s_axi_awvalid),
2459 
        .I1(s_axi_wvalid),
2460 
        .I2(s_axi_arvalid),
2461 
        .I3(state[0]),
2462 
        .I4(state[1]),
2463 
        .I5(bus2ip_rnw_i),
2464 
        .O(bus2ip_rnw_i_i_1_n_0));
2465 
  FDRE bus2ip_rnw_i_reg
2466 
       (.C(s_axi_aclk),
2467 
        .CE(1'b1),
2468 
        .D(bus2ip_rnw_i_i_1_n_0),
2469 
        .Q(bus2ip_rnw_i),
2470 
        .R(rst));
2471 
  FDRE rst_reg
2472 
       (.C(s_axi_aclk),
2473 
        .CE(1'b1),
2474 
        .D(bus2ip_reset),
2475 
        .Q(rst),
2476 
        .R(1'b0));
2477 
  FDRE #(
2478 
    .INIT(1'b0))
2479 
    \s_axi_bresp_i_reg[1]
2480 
       (.C(s_axi_aclk),
2481 
        .CE(1'b1),
2482 
        .D(I_DECODER_n_28),
2483 
        .Q(s_axi_bresp),
2484 
        .R(rst));
2485 
  FDRE #(
2486 
    .INIT(1'b0))
2487 
    s_axi_bvalid_i_reg
2488 
       (.C(s_axi_aclk),
2489 
        .CE(1'b1),
2490 
        .D(I_DECODER_n_27),
2491 
        .Q(s_axi_bvalid),
2492 
        .R(rst));
2493 
  LUT2 #(
2494 
    .INIT(4'h2))
2495 
    \s_axi_rdata_i[7]_i_1
2496 
       (.I0(state[0]),
2497 
        .I1(state[1]),
2498 
        .O(s_axi_rdata_i));
2499 
  FDRE #(
2500 
    .INIT(1'b0))
2501 
    \s_axi_rdata_i_reg[0]
2502 
       (.C(s_axi_aclk),
2503 
        .CE(s_axi_rdata_i),
2504 
        .D(SIn_DBus[7]),
2505 
        .Q(s_axi_rdata[0]),
2506 
        .R(rst));
2507 
  FDRE #(
2508 
    .INIT(1'b0))
2509 
    \s_axi_rdata_i_reg[1]
2510 
       (.C(s_axi_aclk),
2511 
        .CE(s_axi_rdata_i),
2512 
        .D(SIn_DBus[6]),
2513 
        .Q(s_axi_rdata[1]),
2514 
        .R(rst));
2515 
  FDRE #(
2516 
    .INIT(1'b0))
2517 
    \s_axi_rdata_i_reg[2]
2518 
       (.C(s_axi_aclk),
2519 
        .CE(s_axi_rdata_i),
2520 
        .D(SIn_DBus[5]),
2521 
        .Q(s_axi_rdata[2]),
2522 
        .R(rst));
2523 
  FDRE #(
2524 
    .INIT(1'b0))
2525 
    \s_axi_rdata_i_reg[3]
2526 
       (.C(s_axi_aclk),
2527 
        .CE(s_axi_rdata_i),
2528 
        .D(SIn_DBus[4]),
2529 
        .Q(s_axi_rdata[3]),
2530 
        .R(rst));
2531 
  FDRE #(
2532 
    .INIT(1'b0))
2533 
    \s_axi_rdata_i_reg[4]
2534 
       (.C(s_axi_aclk),
2535 
        .CE(s_axi_rdata_i),
2536 
        .D(SIn_DBus[3]),
2537 
        .Q(s_axi_rdata[4]),
2538 
        .R(rst));
2539 
  FDRE #(
2540 
    .INIT(1'b0))
2541 
    \s_axi_rdata_i_reg[5]
2542 
       (.C(s_axi_aclk),
2543 
        .CE(s_axi_rdata_i),
2544 
        .D(SIn_DBus[2]),
2545 
        .Q(s_axi_rdata[5]),
2546 
        .R(rst));
2547 
  FDRE #(
2548 
    .INIT(1'b0))
2549 
    \s_axi_rdata_i_reg[6]
2550 
       (.C(s_axi_aclk),
2551 
        .CE(s_axi_rdata_i),
2552 
        .D(SIn_DBus[1]),
2553 
        .Q(s_axi_rdata[6]),
2554 
        .R(rst));
2555 
  FDRE #(
2556 
    .INIT(1'b0))
2557 
    \s_axi_rdata_i_reg[7]
2558 
       (.C(s_axi_aclk),
2559 
        .CE(s_axi_rdata_i),
2560 
        .D(SIn_DBus[0]),
2561 
        .Q(s_axi_rdata[7]),
2562 
        .R(rst));
2563 
  FDRE #(
2564 
    .INIT(1'b0))
2565 
    \s_axi_rresp_i_reg[1]
2566 
       (.C(s_axi_aclk),
2567 
        .CE(s_axi_rdata_i),
2568 
        .D(ip2bus_error),
2569 
        .Q(s_axi_rresp),
2570 
        .R(rst));
2571 
  FDRE #(
2572 
    .INIT(1'b0))
2573 
    s_axi_rvalid_i_reg
2574 
       (.C(s_axi_aclk),
2575 
        .CE(1'b1),
2576 
        .D(I_DECODER_n_26),
2577 
        .Q(s_axi_rvalid),
2578 
        .R(rst));
2579 
  (* SOFT_HLUTNM = "soft_lutpair9" *)
2580 
  LUT5 #(
2581 
    .INIT(32'h000000F8))
2582 
    start2_i_1
2583 
       (.I0(s_axi_awvalid),
2584 
        .I1(s_axi_wvalid),
2585 
        .I2(s_axi_arvalid),
2586 
        .I3(state[0]),
2587 
        .I4(state[1]),
2588 
        .O(start2_i_1_n_0));
2589 
  FDRE start2_reg
2590 
       (.C(s_axi_aclk),
2591 
        .CE(1'b1),
2592 
        .D(start2_i_1_n_0),
2593 
        .Q(start2),
2594 
        .R(rst));
2595 
  LUT5 #(
2596 
    .INIT(32'h002A2A2A))
2597 
    \state[0]_i_2
2598 
       (.I0(state[0]),
2599 
        .I1(s_axi_rvalid),
2600 
        .I2(s_axi_rready),
2601 
        .I3(s_axi_bready),
2602 
        .I4(s_axi_bvalid),
2603 
        .O(\state[0]_i_2_n_0 ));
2604 
  LUT5 #(
2605 
    .INIT(32'h002A2A2A))
2606 
    \state[1]_i_2
2607 
       (.I0(state[1]),
2608 
        .I1(s_axi_rvalid),
2609 
        .I2(s_axi_rready),
2610 
        .I3(s_axi_bready),
2611 
        .I4(s_axi_bvalid),
2612 
        .O(\state[1]_i_2_n_0 ));
2613 
  LUT2 #(
2614 
    .INIT(4'h8))
2615 
    \state[1]_i_3
2616 
       (.I0(s_axi_awvalid),
2617 
        .I1(s_axi_wvalid),
2618 
        .O(\state[1]_i_3_n_0 ));
2619 
  FDRE \state_reg[0]
2620 
       (.C(s_axi_aclk),
2621 
        .CE(1'b1),
2622 
        .D(I_DECODER_n_6),
2623 
        .Q(state[0]),
2624 
        .R(rst));
2625 
  FDRE \state_reg[1]
2626 
       (.C(s_axi_aclk),
2627 
        .CE(1'b1),
2628 
        .D(I_DECODER_n_5),
2629 
        .Q(state[1]),
2630 
        .R(rst));
2631 
endmodule
2632 
 
2633 
module axi_uartlite_module_sim_srl_fifo_f
2634 
   (tx_Buffer_Full,
2635 
    mux_Out,
2636 
    Q,
2637 
    tx_Start0,
2638 
    s_axi_aclk,
2639 
    p_4_in,
2640 
    \mux_sel_reg[2] ,
2641 
    \mux_sel_reg[0] ,
2642 
    reset_TX_FIFO_reg,
2643 
    s_axi_aresetn,
2644 
    fifo_Read,
2645 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
2646 
    Bus_RNW_reg,
2647 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
2648 
    tx_Data_Enable_reg,
2649 
    tx_DataBits,
2650 
    tx_Start,
2651 
    fifo_wr,
2652 
    s_axi_wdata);
2653 
  output tx_Buffer_Full;
2654 
  output mux_Out;
2655 
  output [0:0]Q;
2656 
  output tx_Start0;
2657 
  input s_axi_aclk;
2658 
  input p_4_in;
2659 
  input \mux_sel_reg[2] ;
2660 
  input \mux_sel_reg[0] ;
2661 
  input reset_TX_FIFO_reg;
2662 
  input s_axi_aresetn;
2663 
  input fifo_Read;
2664 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
2665 
  input Bus_RNW_reg;
2666 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
2667 
  input tx_Data_Enable_reg;
2668 
  input tx_DataBits;
2669 
  input tx_Start;
2670 
  input fifo_wr;
2671 
  input [7:0]s_axi_wdata;
2672 
 
2673 
  wire Bus_RNW_reg;
2674 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
2675 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
2676 
  wire [0:0]Q;
2677 
  wire fifo_Read;
2678 
  wire fifo_wr;
2679 
  wire mux_Out;
2680 
  wire \mux_sel_reg[0] ;
2681 
  wire \mux_sel_reg[2] ;
2682 
  wire p_4_in;
2683 
  wire reset_TX_FIFO_reg;
2684 
  wire s_axi_aclk;
2685 
  wire s_axi_aresetn;
2686 
  wire [7:0]s_axi_wdata;
2687 
  wire tx_Buffer_Full;
2688 
  wire tx_DataBits;
2689 
  wire tx_Data_Enable_reg;
2690 
  wire tx_Start;
2691 
  wire tx_Start0;
2692 
 
2693 
  axi_uartlite_module_sim_srl_fifo_rbu_f I_SRL_FIFO_RBU_F
2694 
       (.Bus_RNW_reg(Bus_RNW_reg),
2695 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
2696 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
2697 
        .Q(Q),
2698 
        .fifo_Read(fifo_Read),
2699 
        .fifo_wr(fifo_wr),
2700 
        .mux_Out(mux_Out),
2701 
        .\mux_sel_reg[0] (\mux_sel_reg[0] ),
2702 
        .\mux_sel_reg[2] (\mux_sel_reg[2] ),
2703 
        .p_4_in(p_4_in),
2704 
        .reset_TX_FIFO_reg(reset_TX_FIFO_reg),
2705 
        .s_axi_aclk(s_axi_aclk),
2706 
        .s_axi_aresetn(s_axi_aresetn),
2707 
        .s_axi_wdata(s_axi_wdata),
2708 
        .tx_Buffer_Full(tx_Buffer_Full),
2709 
        .tx_DataBits(tx_DataBits),
2710 
        .tx_Data_Enable_reg(tx_Data_Enable_reg),
2711 
        .tx_Start(tx_Start),
2712 
        .tx_Start0(tx_Start0));
2713 
endmodule
2714 
 
2715 
(* ORIG_REF_NAME = "srl_fifo_f" *)
2716 
module axi_uartlite_module_sim_srl_fifo_f_0
2717 
   (\status_reg_reg[2] ,
2718 
    Q,
2719 
    \status_reg_reg[2]_0 ,
2720 
    Interrupt0,
2721 
    out,
2722 
    s_axi_aclk,
2723 
    reset_RX_FIFO_reg,
2724 
    s_axi_aresetn,
2725 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
2726 
    Bus_RNW_reg,
2727 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
2728 
    Bus_RNW_reg_reg,
2729 
    status_reg,
2730 
    fifo_Write,
2731 
    clr_Status,
2732 
    valid_rx,
2733 
    rx_Data_Present_Pre,
2734 
    enable_interrupts,
2735 
    \INFERRED_GEN.cnt_i_reg[4] ,
2736 
    tx_Buffer_Empty_Pre,
2737 
    in);
2738 
  output \status_reg_reg[2] ;
2739 
  output [0:0]Q;
2740 
  output \status_reg_reg[2]_0 ;
2741 
  output Interrupt0;
2742 
  output [7:0]out;
2743 
  input s_axi_aclk;
2744 
  input reset_RX_FIFO_reg;
2745 
  input s_axi_aresetn;
2746 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
2747 
  input Bus_RNW_reg;
2748 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
2749 
  input Bus_RNW_reg_reg;
2750 
  input [0:0]status_reg;
2751 
  input fifo_Write;
2752 
  input clr_Status;
2753 
  input valid_rx;
2754 
  input rx_Data_Present_Pre;
2755 
  input enable_interrupts;
2756 
  input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
2757 
  input tx_Buffer_Empty_Pre;
2758 
  input [0:7]in;
2759 
 
2760 
  wire Bus_RNW_reg;
2761 
  wire Bus_RNW_reg_reg;
2762 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
2763 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
2764 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
2765 
  wire Interrupt0;
2766 
  wire [0:0]Q;
2767 
  wire clr_Status;
2768 
  wire enable_interrupts;
2769 
  wire fifo_Write;
2770 
  wire [0:7]in;
2771 
  wire [7:0]out;
2772 
  wire reset_RX_FIFO_reg;
2773 
  wire rx_Data_Present_Pre;
2774 
  wire s_axi_aclk;
2775 
  wire s_axi_aresetn;
2776 
  wire [0:0]status_reg;
2777 
  wire \status_reg_reg[2] ;
2778 
  wire \status_reg_reg[2]_0 ;
2779 
  wire tx_Buffer_Empty_Pre;
2780 
  wire valid_rx;
2781 
 
2782 
  axi_uartlite_module_sim_srl_fifo_rbu_f_1 I_SRL_FIFO_RBU_F
2783 
       (.Bus_RNW_reg(Bus_RNW_reg),
2784 
        .Bus_RNW_reg_reg(Bus_RNW_reg_reg),
2785 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
2786 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
2787 
        .\INFERRED_GEN.cnt_i_reg[4] (\INFERRED_GEN.cnt_i_reg[4] ),
2788 
        .Interrupt0(Interrupt0),
2789 
        .Q(Q),
2790 
        .clr_Status(clr_Status),
2791 
        .enable_interrupts(enable_interrupts),
2792 
        .fifo_Write(fifo_Write),
2793 
        .in(in),
2794 
        .out(out),
2795 
        .reset_RX_FIFO_reg(reset_RX_FIFO_reg),
2796 
        .rx_Data_Present_Pre(rx_Data_Present_Pre),
2797 
        .s_axi_aclk(s_axi_aclk),
2798 
        .s_axi_aresetn(s_axi_aresetn),
2799 
        .status_reg(status_reg),
2800 
        .\status_reg_reg[2] (\status_reg_reg[2] ),
2801 
        .\status_reg_reg[2]_0 (\status_reg_reg[2]_0 ),
2802 
        .tx_Buffer_Empty_Pre(tx_Buffer_Empty_Pre),
2803 
        .valid_rx(valid_rx));
2804 
endmodule
2805 
 
2806 
module axi_uartlite_module_sim_srl_fifo_rbu_f
2807 
   (tx_Buffer_Full,
2808 
    mux_Out,
2809 
    Q,
2810 
    tx_Start0,
2811 
    s_axi_aclk,
2812 
    p_4_in,
2813 
    \mux_sel_reg[2] ,
2814 
    \mux_sel_reg[0] ,
2815 
    reset_TX_FIFO_reg,
2816 
    s_axi_aresetn,
2817 
    fifo_Read,
2818 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
2819 
    Bus_RNW_reg,
2820 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
2821 
    tx_Data_Enable_reg,
2822 
    tx_DataBits,
2823 
    tx_Start,
2824 
    fifo_wr,
2825 
    s_axi_wdata);
2826 
  output tx_Buffer_Full;
2827 
  output mux_Out;
2828 
  output [0:0]Q;
2829 
  output tx_Start0;
2830 
  input s_axi_aclk;
2831 
  input p_4_in;
2832 
  input \mux_sel_reg[2] ;
2833 
  input \mux_sel_reg[0] ;
2834 
  input reset_TX_FIFO_reg;
2835 
  input s_axi_aresetn;
2836 
  input fifo_Read;
2837 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
2838 
  input Bus_RNW_reg;
2839 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
2840 
  input tx_Data_Enable_reg;
2841 
  input tx_DataBits;
2842 
  input tx_Start;
2843 
  input fifo_wr;
2844 
  input [7:0]s_axi_wdata;
2845 
 
2846 
  wire Bus_RNW_reg;
2847 
  wire CNTR_INCR_DECR_ADDN_F_I_n_2;
2848 
  wire CNTR_INCR_DECR_ADDN_F_I_n_3;
2849 
  wire CNTR_INCR_DECR_ADDN_F_I_n_4;
2850 
  wire CNTR_INCR_DECR_ADDN_F_I_n_5;
2851 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
2852 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
2853 
  wire [0:0]Q;
2854 
  wire TX_FIFO_Reset;
2855 
  wire fifo_Read;
2856 
  wire fifo_full_p1;
2857 
  wire fifo_wr;
2858 
  wire mux_Out;
2859 
  wire \mux_sel_reg[0] ;
2860 
  wire \mux_sel_reg[2] ;
2861 
  wire p_4_in;
2862 
  wire reset_TX_FIFO_reg;
2863 
  wire s_axi_aclk;
2864 
  wire s_axi_aresetn;
2865 
  wire [7:0]s_axi_wdata;
2866 
  wire tx_Buffer_Full;
2867 
  wire tx_DataBits;
2868 
  wire tx_Data_Enable_reg;
2869 
  wire tx_Start;
2870 
  wire tx_Start0;
2871 
 
2872 
  axi_uartlite_module_sim_cntr_incr_decr_addn_f CNTR_INCR_DECR_ADDN_F_I
2873 
       (.Bus_RNW_reg(Bus_RNW_reg),
2874 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
2875 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
2876 
        .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4,CNTR_INCR_DECR_ADDN_F_I_n_5}),
2877 
        .SS(TX_FIFO_Reset),
2878 
        .fifo_Read(fifo_Read),
2879 
        .fifo_full_p1(fifo_full_p1),
2880 
        .reset_TX_FIFO_reg(reset_TX_FIFO_reg),
2881 
        .s_axi_aclk(s_axi_aclk),
2882 
        .s_axi_aresetn(s_axi_aresetn),
2883 
        .tx_Buffer_Full(tx_Buffer_Full),
2884 
        .tx_DataBits(tx_DataBits),
2885 
        .tx_Data_Enable_reg(tx_Data_Enable_reg),
2886 
        .tx_Start(tx_Start),
2887 
        .tx_Start0(tx_Start0));
2888 
  axi_uartlite_module_sim_dynshreg_f DYNSHREG_F_I
2889 
       (.Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4,CNTR_INCR_DECR_ADDN_F_I_n_5}),
2890 
        .fifo_wr(fifo_wr),
2891 
        .mux_Out(mux_Out),
2892 
        .\mux_sel_reg[0] (\mux_sel_reg[0] ),
2893 
        .\mux_sel_reg[2] (\mux_sel_reg[2] ),
2894 
        .p_4_in(p_4_in),
2895 
        .s_axi_aclk(s_axi_aclk),
2896 
        .s_axi_wdata(s_axi_wdata));
2897 
  FDRE FIFO_Full_reg
2898 
       (.C(s_axi_aclk),
2899 
        .CE(1'b1),
2900 
        .D(fifo_full_p1),
2901 
        .Q(tx_Buffer_Full),
2902 
        .R(TX_FIFO_Reset));
2903 
endmodule
2904 
 
2905 
(* ORIG_REF_NAME = "srl_fifo_rbu_f" *)
2906 
module axi_uartlite_module_sim_srl_fifo_rbu_f_1
2907 
   (\status_reg_reg[2] ,
2908 
    Q,
2909 
    \status_reg_reg[2]_0 ,
2910 
    Interrupt0,
2911 
    out,
2912 
    s_axi_aclk,
2913 
    reset_RX_FIFO_reg,
2914 
    s_axi_aresetn,
2915 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
2916 
    Bus_RNW_reg,
2917 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
2918 
    Bus_RNW_reg_reg,
2919 
    status_reg,
2920 
    fifo_Write,
2921 
    clr_Status,
2922 
    valid_rx,
2923 
    rx_Data_Present_Pre,
2924 
    enable_interrupts,
2925 
    \INFERRED_GEN.cnt_i_reg[4] ,
2926 
    tx_Buffer_Empty_Pre,
2927 
    in);
2928 
  output \status_reg_reg[2] ;
2929 
  output [0:0]Q;
2930 
  output \status_reg_reg[2]_0 ;
2931 
  output Interrupt0;
2932 
  output [7:0]out;
2933 
  input s_axi_aclk;
2934 
  input reset_RX_FIFO_reg;
2935 
  input s_axi_aresetn;
2936 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
2937 
  input Bus_RNW_reg;
2938 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
2939 
  input Bus_RNW_reg_reg;
2940 
  input [0:0]status_reg;
2941 
  input fifo_Write;
2942 
  input clr_Status;
2943 
  input valid_rx;
2944 
  input rx_Data_Present_Pre;
2945 
  input enable_interrupts;
2946 
  input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
2947 
  input tx_Buffer_Empty_Pre;
2948 
  input [0:7]in;
2949 
 
2950 
  wire Bus_RNW_reg;
2951 
  wire Bus_RNW_reg_reg;
2952 
  wire CNTR_INCR_DECR_ADDN_F_I_n_3;
2953 
  wire CNTR_INCR_DECR_ADDN_F_I_n_4;
2954 
  wire CNTR_INCR_DECR_ADDN_F_I_n_5;
2955 
  wire CNTR_INCR_DECR_ADDN_F_I_n_6;
2956 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
2957 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
2958 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
2959 
  wire Interrupt0;
2960 
  wire [0:0]Q;
2961 
  wire RX_FIFO_Reset;
2962 
  wire clr_Status;
2963 
  wire enable_interrupts;
2964 
  wire fifo_Write;
2965 
  wire fifo_full_p1;
2966 
  wire [0:7]in;
2967 
  wire [7:0]out;
2968 
  wire reset_RX_FIFO_reg;
2969 
  wire rx_Data_Present_Pre;
2970 
  wire s_axi_aclk;
2971 
  wire s_axi_aresetn;
2972 
  wire [0:0]status_reg;
2973 
  wire \status_reg_reg[2] ;
2974 
  wire \status_reg_reg[2]_0 ;
2975 
  wire tx_Buffer_Empty_Pre;
2976 
  wire valid_rx;
2977 
 
2978 
  axi_uartlite_module_sim_cntr_incr_decr_addn_f_2 CNTR_INCR_DECR_ADDN_F_I
2979 
       (.Bus_RNW_reg(Bus_RNW_reg),
2980 
        .Bus_RNW_reg_reg(Bus_RNW_reg_reg),
2981 
        .FIFO_Full_reg(\status_reg_reg[2] ),
2982 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
2983 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
2984 
        .\INFERRED_GEN.cnt_i_reg[4]_0 (\INFERRED_GEN.cnt_i_reg[4] ),
2985 
        .Interrupt0(Interrupt0),
2986 
        .Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4,CNTR_INCR_DECR_ADDN_F_I_n_5,CNTR_INCR_DECR_ADDN_F_I_n_6}),
2987 
        .SS(RX_FIFO_Reset),
2988 
        .enable_interrupts(enable_interrupts),
2989 
        .fifo_Write(fifo_Write),
2990 
        .fifo_full_p1(fifo_full_p1),
2991 
        .reset_RX_FIFO_reg(reset_RX_FIFO_reg),
2992 
        .rx_Data_Present_Pre(rx_Data_Present_Pre),
2993 
        .s_axi_aclk(s_axi_aclk),
2994 
        .s_axi_aresetn(s_axi_aresetn),
2995 
        .tx_Buffer_Empty_Pre(tx_Buffer_Empty_Pre),
2996 
        .valid_rx(valid_rx));
2997 
  axi_uartlite_module_sim_dynshreg_f_3 DYNSHREG_F_I
2998 
       (.FIFO_Full_reg(\status_reg_reg[2] ),
2999 
        .Q({CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4,CNTR_INCR_DECR_ADDN_F_I_n_5,CNTR_INCR_DECR_ADDN_F_I_n_6}),
3000 
        .fifo_Write(fifo_Write),
3001 
        .in(in),
3002 
        .out(out),
3003 
        .s_axi_aclk(s_axi_aclk),
3004 
        .valid_rx(valid_rx));
3005 
  FDRE FIFO_Full_reg
3006 
       (.C(s_axi_aclk),
3007 
        .CE(1'b1),
3008 
        .D(fifo_full_p1),
3009 
        .Q(\status_reg_reg[2] ),
3010 
        .R(RX_FIFO_Reset));
3011 
  LUT5 #(
3012 
    .INIT(32'h00EA0000))
3013 
    \status_reg[2]_i_1
3014 
       (.I0(status_reg),
3015 
        .I1(fifo_Write),
3016 
        .I2(\status_reg_reg[2] ),
3017 
        .I3(clr_Status),
3018 
        .I4(s_axi_aresetn),
3019 
        .O(\status_reg_reg[2]_0 ));
3020 
endmodule
3021 
 
3022 
module axi_uartlite_module_sim_uartlite_core
3023 
   (status_reg,
3024 
    bus2ip_reset,
3025 
    rx_Buffer_Full,
3026 
    tx_Buffer_Full,
3027 
    tx,
3028 
    interrupt,
3029 
    enable_interrupts,
3030 
    Q,
3031 
    \INFERRED_GEN.cnt_i_reg[2] ,
3032 
    out,
3033 
    s_axi_aclk,
3034 
    reset_TX_FIFO,
3035 
    reset_RX_FIFO,
3036 
    bus2ip_rdce,
3037 
    \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ,
3038 
    \INFERRED_GEN.cnt_i_reg[4] ,
3039 
    \INFERRED_GEN.cnt_i_reg[4]_0 ,
3040 
    s_axi_aresetn,
3041 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
3042 
    Bus_RNW_reg,
3043 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
3044 
    Bus_RNW_reg_reg,
3045 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
3046 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
3047 
    rx,
3048 
    fifo_wr,
3049 
    s_axi_wdata);
3050 
  output [1:0]status_reg;
3051 
  output bus2ip_reset;
3052 
  output rx_Buffer_Full;
3053 
  output tx_Buffer_Full;
3054 
  output tx;
3055 
  output interrupt;
3056 
  output enable_interrupts;
3057 
  output [0:0]Q;
3058 
  output [0:0]\INFERRED_GEN.cnt_i_reg[2] ;
3059 
  output [7:0]out;
3060 
  input s_axi_aclk;
3061 
  input reset_TX_FIFO;
3062 
  input reset_RX_FIFO;
3063 
  input [0:0]bus2ip_rdce;
3064 
  input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ;
3065 
  input \INFERRED_GEN.cnt_i_reg[4] ;
3066 
  input \INFERRED_GEN.cnt_i_reg[4]_0 ;
3067 
  input s_axi_aresetn;
3068 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
3069 
  input Bus_RNW_reg;
3070 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
3071 
  input Bus_RNW_reg_reg;
3072 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
3073 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
3074 
  input rx;
3075 
  input fifo_wr;
3076 
  input [7:0]s_axi_wdata;
3077 
 
3078 
  wire Bus_RNW_reg;
3079 
  wire Bus_RNW_reg_reg;
3080 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
3081 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
3082 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
3083 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
3084 
  wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ;
3085 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[2] ;
3086 
  wire \INFERRED_GEN.cnt_i_reg[4] ;
3087 
  wire \INFERRED_GEN.cnt_i_reg[4]_0 ;
3088 
  wire Interrupt0;
3089 
  wire [0:0]Q;
3090 
  wire UARTLITE_RX_I_n_4;
3091 
  wire [0:0]bus2ip_rdce;
3092 
  wire bus2ip_reset;
3093 
  wire clr_Status;
3094 
  wire en_16x_Baud;
3095 
  wire enable_interrupts;
3096 
  wire fifo_wr;
3097 
  wire interrupt;
3098 
  wire [7:0]out;
3099 
  wire reset_RX_FIFO;
3100 
  wire reset_RX_FIFO_reg_n_0;
3101 
  wire reset_TX_FIFO;
3102 
  wire reset_TX_FIFO_reg_n_0;
3103 
  wire rx;
3104 
  wire rx_Buffer_Full;
3105 
  wire rx_Data_Present_Pre;
3106 
  wire s_axi_aclk;
3107 
  wire s_axi_aresetn;
3108 
  wire [7:0]s_axi_wdata;
3109 
  wire [1:0]status_reg;
3110 
  wire status_reg_reg0;
3111 
  wire tx;
3112 
  wire tx_Buffer_Empty_Pre;
3113 
  wire tx_Buffer_Full;
3114 
 
3115 
  axi_uartlite_module_sim_baudrate BAUD_RATE_I
3116 
       (.SR(bus2ip_reset),
3117 
        .en_16x_Baud(en_16x_Baud),
3118 
        .s_axi_aclk(s_axi_aclk));
3119 
  FDRE Interrupt_reg
3120 
       (.C(s_axi_aclk),
3121 
        .CE(1'b1),
3122 
        .D(Interrupt0),
3123 
        .Q(interrupt),
3124 
        .R(bus2ip_reset));
3125 
  axi_uartlite_module_sim_uartlite_rx UARTLITE_RX_I
3126 
       (.Bus_RNW_reg(Bus_RNW_reg),
3127 
        .Bus_RNW_reg_reg(Bus_RNW_reg_reg),
3128 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
3129 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
3130 
        .\INFERRED_GEN.cnt_i_reg[4] (\INFERRED_GEN.cnt_i_reg[2] ),
3131 
        .Interrupt0(Interrupt0),
3132 
        .Q(Q),
3133 
        .SR(bus2ip_reset),
3134 
        .clr_Status(clr_Status),
3135 
        .en_16x_Baud(en_16x_Baud),
3136 
        .enable_interrupts(enable_interrupts),
3137 
        .out(out),
3138 
        .reset_RX_FIFO_reg(reset_RX_FIFO_reg_n_0),
3139 
        .rx(rx),
3140 
        .rx_Data_Present_Pre(rx_Data_Present_Pre),
3141 
        .s_axi_aclk(s_axi_aclk),
3142 
        .s_axi_aresetn(s_axi_aresetn),
3143 
        .status_reg(status_reg),
3144 
        .status_reg_reg0(status_reg_reg0),
3145 
        .\status_reg_reg[2] (rx_Buffer_Full),
3146 
        .\status_reg_reg[2]_0 (UARTLITE_RX_I_n_4),
3147 
        .tx_Buffer_Empty_Pre(tx_Buffer_Empty_Pre));
3148 
  axi_uartlite_module_sim_uartlite_tx UARTLITE_TX_I
3149 
       (.Bus_RNW_reg(Bus_RNW_reg),
3150 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
3151 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
3152 
        .Q(\INFERRED_GEN.cnt_i_reg[2] ),
3153 
        .SR(bus2ip_reset),
3154 
        .en_16x_Baud(en_16x_Baud),
3155 
        .fifo_wr(fifo_wr),
3156 
        .reset_TX_FIFO_reg(reset_TX_FIFO_reg_n_0),
3157 
        .s_axi_aclk(s_axi_aclk),
3158 
        .s_axi_aresetn(s_axi_aresetn),
3159 
        .s_axi_wdata(s_axi_wdata),
3160 
        .tx(tx),
3161 
        .tx_Buffer_Full(tx_Buffer_Full));
3162 
  FDRE clr_Status_reg
3163 
       (.C(s_axi_aclk),
3164 
        .CE(1'b1),
3165 
        .D(bus2ip_rdce),
3166 
        .Q(clr_Status),
3167 
        .R(bus2ip_reset));
3168 
  FDRE enable_interrupts_reg
3169 
       (.C(s_axi_aclk),
3170 
        .CE(1'b1),
3171 
        .D(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ),
3172 
        .Q(enable_interrupts),
3173 
        .R(bus2ip_reset));
3174 
  FDSE reset_RX_FIFO_reg
3175 
       (.C(s_axi_aclk),
3176 
        .CE(1'b1),
3177 
        .D(reset_RX_FIFO),
3178 
        .Q(reset_RX_FIFO_reg_n_0),
3179 
        .S(bus2ip_reset));
3180 
  FDSE reset_TX_FIFO_reg
3181 
       (.C(s_axi_aclk),
3182 
        .CE(1'b1),
3183 
        .D(reset_TX_FIFO),
3184 
        .Q(reset_TX_FIFO_reg_n_0),
3185 
        .S(bus2ip_reset));
3186 
  FDRE rx_Data_Present_Pre_reg
3187 
       (.C(s_axi_aclk),
3188 
        .CE(1'b1),
3189 
        .D(\INFERRED_GEN.cnt_i_reg[4]_0 ),
3190 
        .Q(rx_Data_Present_Pre),
3191 
        .R(1'b0));
3192 
  FDRE #(
3193 
    .INIT(1'b0))
3194 
    \status_reg_reg[1]
3195 
       (.C(s_axi_aclk),
3196 
        .CE(1'b1),
3197 
        .D(status_reg_reg0),
3198 
        .Q(status_reg[1]),
3199 
        .R(1'b0));
3200 
  FDRE #(
3201 
    .INIT(1'b0))
3202 
    \status_reg_reg[2]
3203 
       (.C(s_axi_aclk),
3204 
        .CE(1'b1),
3205 
        .D(UARTLITE_RX_I_n_4),
3206 
        .Q(status_reg[0]),
3207 
        .R(1'b0));
3208 
  FDRE tx_Buffer_Empty_Pre_reg
3209 
       (.C(s_axi_aclk),
3210 
        .CE(1'b1),
3211 
        .D(\INFERRED_GEN.cnt_i_reg[4] ),
3212 
        .Q(tx_Buffer_Empty_Pre),
3213 
        .R(1'b0));
3214 
endmodule
3215 
 
3216 
module axi_uartlite_module_sim_uartlite_rx
3217 
   (\status_reg_reg[2] ,
3218 
    SR,
3219 
    status_reg_reg0,
3220 
    Q,
3221 
    \status_reg_reg[2]_0 ,
3222 
    Interrupt0,
3223 
    out,
3224 
    s_axi_aclk,
3225 
    en_16x_Baud,
3226 
    s_axi_aresetn,
3227 
    status_reg,
3228 
    clr_Status,
3229 
    reset_RX_FIFO_reg,
3230 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
3231 
    Bus_RNW_reg,
3232 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
3233 
    Bus_RNW_reg_reg,
3234 
    rx_Data_Present_Pre,
3235 
    enable_interrupts,
3236 
    \INFERRED_GEN.cnt_i_reg[4] ,
3237 
    tx_Buffer_Empty_Pre,
3238 
    rx);
3239 
  output \status_reg_reg[2] ;
3240 
  output [0:0]SR;
3241 
  output status_reg_reg0;
3242 
  output [0:0]Q;
3243 
  output \status_reg_reg[2]_0 ;
3244 
  output Interrupt0;
3245 
  output [7:0]out;
3246 
  input s_axi_aclk;
3247 
  input en_16x_Baud;
3248 
  input s_axi_aresetn;
3249 
  input [1:0]status_reg;
3250 
  input clr_Status;
3251 
  input reset_RX_FIFO_reg;
3252 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
3253 
  input Bus_RNW_reg;
3254 
  input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
3255 
  input Bus_RNW_reg_reg;
3256 
  input rx_Data_Present_Pre;
3257 
  input enable_interrupts;
3258 
  input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
3259 
  input tx_Buffer_Empty_Pre;
3260 
  input rx;
3261 
 
3262 
  wire Bus_RNW_reg;
3263 
  wire Bus_RNW_reg_reg;
3264 
  wire DELAY_16_I_n_1;
3265 
  wire DELAY_16_I_n_10;
3266 
  wire DELAY_16_I_n_11;
3267 
  wire DELAY_16_I_n_12;
3268 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
3269 
  wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
3270 
  wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
3271 
  wire Interrupt0;
3272 
  wire [0:0]Q;
3273 
  wire RX_D2;
3274 
  wire [0:0]SR;
3275 
  wire clr_Status;
3276 
  wire en_16x_Baud;
3277 
  wire enable_interrupts;
3278 
  wire fifo_Write;
3279 
  wire fifo_Write0;
3280 
  wire [1:8]fifo_din;
3281 
  wire frame_err_ocrd;
3282 
  wire [7:0]out;
3283 
  wire p_11_out;
3284 
  wire p_14_out;
3285 
  wire p_17_out;
3286 
  wire p_20_out;
3287 
  wire p_26_out;
3288 
  wire p_2_out;
3289 
  wire p_5_out;
3290 
  wire p_8_out;
3291 
  wire reset_RX_FIFO_reg;
3292 
  wire running_reg_n_0;
3293 
  wire rx;
3294 
  wire rx_1;
3295 
  wire rx_2;
3296 
  wire rx_3;
3297 
  wire rx_4;
3298 
  wire rx_5;
3299 
  wire rx_6;
3300 
  wire rx_7;
3301 
  wire rx_8;
3302 
  wire rx_9;
3303 
  wire rx_Data_Present_Pre;
3304 
  wire s_axi_aclk;
3305 
  wire s_axi_aresetn;
3306 
  wire start_Edge_Detected;
3307 
  wire start_Edge_Detected0;
3308 
  wire start_Edge_Detected_i_2_n_0;
3309 
  wire [1:0]status_reg;
3310 
  wire status_reg_reg0;
3311 
  wire \status_reg_reg[2] ;
3312 
  wire \status_reg_reg[2]_0 ;
3313 
  wire stop_Bit_Position_reg_n_0;
3314 
  wire tx_Buffer_Empty_Pre;
3315 
  wire valid_rx;
3316 
  wire valid_rx_i_1_n_0;
3317 
 
3318 
  axi_uartlite_module_sim_dynshreg_i_f DELAY_16_I
3319 
       (.\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] (DELAY_16_I_n_1),
3320 
        .clr_Status(clr_Status),
3321 
        .en_16x_Baud(en_16x_Baud),
3322 
        .fifo_Write0(fifo_Write0),
3323 
        .frame_err_ocrd(frame_err_ocrd),
3324 
        .frame_err_ocrd_reg(DELAY_16_I_n_11),
3325 
        .in(fifo_din),
3326 
        .p_11_out(p_11_out),
3327 
        .p_14_out(p_14_out),
3328 
        .p_17_out(p_17_out),
3329 
        .p_20_out(p_20_out),
3330 
        .p_2_out(p_2_out),
3331 
        .p_5_out(p_5_out),
3332 
        .p_8_out(p_8_out),
3333 
        .running_reg(DELAY_16_I_n_12),
3334 
        .running_reg_0(running_reg_n_0),
3335 
        .s_axi_aclk(s_axi_aclk),
3336 
        .s_axi_aresetn(s_axi_aresetn),
3337 
        .scndry_out(RX_D2),
3338 
        .start_Edge_Detected(start_Edge_Detected),
3339 
        .status_reg(status_reg[1]),
3340 
        .status_reg_reg0(status_reg_reg0),
3341 
        .stop_Bit_Position_reg(DELAY_16_I_n_10),
3342 
        .stop_Bit_Position_reg_0(stop_Bit_Position_reg_n_0),
3343 
        .valid_rx(valid_rx));
3344 
  axi_uartlite_module_sim_cdc_sync INPUT_DOUBLE_REGS3
3345 
       (.EN_16x_Baud_reg(DELAY_16_I_n_1),
3346 
        .in(fifo_din[1]),
3347 
        .p_26_out(p_26_out),
3348 
        .rx(rx),
3349 
        .s_axi_aclk(s_axi_aclk),
3350 
        .s_axi_aresetn(s_axi_aresetn),
3351 
        .scndry_out(RX_D2),
3352 
        .start_Edge_Detected(start_Edge_Detected));
3353 
  LUT1 #(
3354 
    .INIT(2'h1))
3355 
    Interrupt_i_1
3356 
       (.I0(s_axi_aresetn),
3357 
        .O(SR));
3358 
  FDRE \SERIAL_TO_PARALLEL[1].fifo_din_reg[1]
3359 
       (.C(s_axi_aclk),
3360 
        .CE(1'b1),
3361 
        .D(p_26_out),
3362 
        .Q(fifo_din[1]),
3363 
        .R(1'b0));
3364 
  FDRE \SERIAL_TO_PARALLEL[2].fifo_din_reg[2]
3365 
       (.C(s_axi_aclk),
3366 
        .CE(1'b1),
3367 
        .D(p_20_out),
3368 
        .Q(fifo_din[2]),
3369 
        .R(1'b0));
3370 
  FDRE \SERIAL_TO_PARALLEL[3].fifo_din_reg[3]
3371 
       (.C(s_axi_aclk),
3372 
        .CE(1'b1),
3373 
        .D(p_17_out),
3374 
        .Q(fifo_din[3]),
3375 
        .R(1'b0));
3376 
  FDRE \SERIAL_TO_PARALLEL[4].fifo_din_reg[4]
3377 
       (.C(s_axi_aclk),
3378 
        .CE(1'b1),
3379 
        .D(p_14_out),
3380 
        .Q(fifo_din[4]),
3381 
        .R(1'b0));
3382 
  FDRE \SERIAL_TO_PARALLEL[5].fifo_din_reg[5]
3383 
       (.C(s_axi_aclk),
3384 
        .CE(1'b1),
3385 
        .D(p_11_out),
3386 
        .Q(fifo_din[5]),
3387 
        .R(1'b0));
3388 
  FDRE \SERIAL_TO_PARALLEL[6].fifo_din_reg[6]
3389 
       (.C(s_axi_aclk),
3390 
        .CE(1'b1),
3391 
        .D(p_8_out),
3392 
        .Q(fifo_din[6]),
3393 
        .R(1'b0));
3394 
  FDRE \SERIAL_TO_PARALLEL[7].fifo_din_reg[7]
3395 
       (.C(s_axi_aclk),
3396 
        .CE(1'b1),
3397 
        .D(p_5_out),
3398 
        .Q(fifo_din[7]),
3399 
        .R(1'b0));
3400 
  FDRE \SERIAL_TO_PARALLEL[8].fifo_din_reg[8]
3401 
       (.C(s_axi_aclk),
3402 
        .CE(1'b1),
3403 
        .D(p_2_out),
3404 
        .Q(fifo_din[8]),
3405 
        .R(1'b0));
3406 
  axi_uartlite_module_sim_srl_fifo_f_0 SRL_FIFO_I
3407 
       (.Bus_RNW_reg(Bus_RNW_reg),
3408 
        .Bus_RNW_reg_reg(Bus_RNW_reg_reg),
3409 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
3410 
        .\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
3411 
        .\INFERRED_GEN.cnt_i_reg[4] (\INFERRED_GEN.cnt_i_reg[4] ),
3412 
        .Interrupt0(Interrupt0),
3413 
        .Q(Q),
3414 
        .clr_Status(clr_Status),
3415 
        .enable_interrupts(enable_interrupts),
3416 
        .fifo_Write(fifo_Write),
3417 
        .in(fifo_din),
3418 
        .out(out),
3419 
        .reset_RX_FIFO_reg(reset_RX_FIFO_reg),
3420 
        .rx_Data_Present_Pre(rx_Data_Present_Pre),
3421 
        .s_axi_aclk(s_axi_aclk),
3422 
        .s_axi_aresetn(s_axi_aresetn),
3423 
        .status_reg(status_reg[0]),
3424 
        .\status_reg_reg[2] (\status_reg_reg[2] ),
3425 
        .\status_reg_reg[2]_0 (\status_reg_reg[2]_0 ),
3426 
        .tx_Buffer_Empty_Pre(tx_Buffer_Empty_Pre),
3427 
        .valid_rx(valid_rx));
3428 
  FDRE fifo_Write_reg
3429 
       (.C(s_axi_aclk),
3430 
        .CE(1'b1),
3431 
        .D(fifo_Write0),
3432 
        .Q(fifo_Write),
3433 
        .R(SR));
3434 
  FDRE frame_err_ocrd_reg
3435 
       (.C(s_axi_aclk),
3436 
        .CE(1'b1),
3437 
        .D(DELAY_16_I_n_11),
3438 
        .Q(frame_err_ocrd),
3439 
        .R(SR));
3440 
  FDRE running_reg
3441 
       (.C(s_axi_aclk),
3442 
        .CE(1'b1),
3443 
        .D(DELAY_16_I_n_12),
3444 
        .Q(running_reg_n_0),
3445 
        .R(SR));
3446 
  FDRE rx_1_reg
3447 
       (.C(s_axi_aclk),
3448 
        .CE(en_16x_Baud),
3449 
        .D(RX_D2),
3450 
        .Q(rx_1),
3451 
        .R(SR));
3452 
  FDRE rx_2_reg
3453 
       (.C(s_axi_aclk),
3454 
        .CE(en_16x_Baud),
3455 
        .D(rx_1),
3456 
        .Q(rx_2),
3457 
        .R(SR));
3458 
  FDRE rx_3_reg
3459 
       (.C(s_axi_aclk),
3460 
        .CE(en_16x_Baud),
3461 
        .D(rx_2),
3462 
        .Q(rx_3),
3463 
        .R(SR));
3464 
  FDRE rx_4_reg
3465 
       (.C(s_axi_aclk),
3466 
        .CE(en_16x_Baud),
3467 
        .D(rx_3),
3468 
        .Q(rx_4),
3469 
        .R(SR));
3470 
  FDRE rx_5_reg
3471 
       (.C(s_axi_aclk),
3472 
        .CE(en_16x_Baud),
3473 
        .D(rx_4),
3474 
        .Q(rx_5),
3475 
        .R(SR));
3476 
  FDRE rx_6_reg
3477 
       (.C(s_axi_aclk),
3478 
        .CE(en_16x_Baud),
3479 
        .D(rx_5),
3480 
        .Q(rx_6),
3481 
        .R(SR));
3482 
  FDRE rx_7_reg
3483 
       (.C(s_axi_aclk),
3484 
        .CE(en_16x_Baud),
3485 
        .D(rx_6),
3486 
        .Q(rx_7),
3487 
        .R(SR));
3488 
  FDRE rx_8_reg
3489 
       (.C(s_axi_aclk),
3490 
        .CE(en_16x_Baud),
3491 
        .D(rx_7),
3492 
        .Q(rx_8),
3493 
        .R(SR));
3494 
  FDRE rx_9_reg
3495 
       (.C(s_axi_aclk),
3496 
        .CE(en_16x_Baud),
3497 
        .D(rx_8),
3498 
        .Q(rx_9),
3499 
        .R(SR));
3500 
  LUT6 #(
3501 
    .INIT(64'h0000000000000010))
3502 
    start_Edge_Detected_i_1
3503 
       (.I0(rx_8),
3504 
        .I1(rx_2),
3505 
        .I2(start_Edge_Detected_i_2_n_0),
3506 
        .I3(rx_3),
3507 
        .I4(rx_1),
3508 
        .I5(frame_err_ocrd),
3509 
        .O(start_Edge_Detected0));
3510 
  LUT6 #(
3511 
    .INIT(64'h0000000000000010))
3512 
    start_Edge_Detected_i_2
3513 
       (.I0(rx_5),
3514 
        .I1(rx_7),
3515 
        .I2(rx_9),
3516 
        .I3(running_reg_n_0),
3517 
        .I4(rx_6),
3518 
        .I5(rx_4),
3519 
        .O(start_Edge_Detected_i_2_n_0));
3520 
  FDRE start_Edge_Detected_reg
3521 
       (.C(s_axi_aclk),
3522 
        .CE(en_16x_Baud),
3523 
        .D(start_Edge_Detected0),
3524 
        .Q(start_Edge_Detected),
3525 
        .R(SR));
3526 
  FDRE stop_Bit_Position_reg
3527 
       (.C(s_axi_aclk),
3528 
        .CE(1'b1),
3529 
        .D(DELAY_16_I_n_10),
3530 
        .Q(stop_Bit_Position_reg_n_0),
3531 
        .R(SR));
3532 
  LUT3 #(
3533 
    .INIT(8'hBA))
3534 
    valid_rx_i_1
3535 
       (.I0(start_Edge_Detected),
3536 
        .I1(fifo_Write),
3537 
        .I2(valid_rx),
3538 
        .O(valid_rx_i_1_n_0));
3539 
  FDRE valid_rx_reg
3540 
       (.C(s_axi_aclk),
3541 
        .CE(1'b1),
3542 
        .D(valid_rx_i_1_n_0),
3543 
        .Q(valid_rx),
3544 
        .R(SR));
3545 
endmodule
3546 
 
3547 
module axi_uartlite_module_sim_uartlite_tx
3548 
   (tx_Buffer_Full,
3549 
    tx,
3550 
    Q,
3551 
    s_axi_aclk,
3552 
    SR,
3553 
    en_16x_Baud,
3554 
    reset_TX_FIFO_reg,
3555 
    s_axi_aresetn,
3556 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
3557 
    Bus_RNW_reg,
3558 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
3559 
    fifo_wr,
3560 
    s_axi_wdata);
3561 
  output tx_Buffer_Full;
3562 
  output tx;
3563 
  output [0:0]Q;
3564 
  input s_axi_aclk;
3565 
  input [0:0]SR;
3566 
  input en_16x_Baud;
3567 
  input reset_TX_FIFO_reg;
3568 
  input s_axi_aresetn;
3569 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
3570 
  input Bus_RNW_reg;
3571 
  input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
3572 
  input fifo_wr;
3573 
  input [7:0]s_axi_wdata;
3574 
 
3575 
  wire Bus_RNW_reg;
3576 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
3577 
  wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
3578 
  wire MID_START_BIT_SRL16_I_n_0;
3579 
  wire [0:0]Q;
3580 
  wire [0:0]SR;
3581 
  wire TX0;
3582 
  wire en_16x_Baud;
3583 
  wire fifo_Read;
3584 
  wire fifo_Read0;
3585 
  wire fifo_wr;
3586 
  wire mux_Out;
3587 
  wire \mux_sel[0]_i_1_n_0 ;
3588 
  wire \mux_sel[1]_i_1_n_0 ;
3589 
  wire \mux_sel[2]_i_1_n_0 ;
3590 
  wire \mux_sel_reg_n_0_[0] ;
3591 
  wire \mux_sel_reg_n_0_[2] ;
3592 
  wire p_4_in;
3593 
  wire reset_TX_FIFO_reg;
3594 
  wire s_axi_aclk;
3595 
  wire s_axi_aresetn;
3596 
  wire [7:0]s_axi_wdata;
3597 
  wire serial_Data;
3598 
  wire tx;
3599 
  wire tx_Buffer_Full;
3600 
  wire tx_DataBits;
3601 
  wire tx_DataBits0;
3602 
  wire tx_Data_Enable_reg_n_0;
3603 
  wire tx_Start;
3604 
  wire tx_Start0;
3605 
 
3606 
  axi_uartlite_module_sim_dynshreg_i_f__parameterized0 MID_START_BIT_SRL16_I
3607 
       (.en_16x_Baud(en_16x_Baud),
3608 
        .s_axi_aclk(s_axi_aclk),
3609 
        .tx_Data_Enable_reg(MID_START_BIT_SRL16_I_n_0),
3610 
        .tx_Data_Enable_reg_0(tx_Data_Enable_reg_n_0));
3611 
  axi_uartlite_module_sim_srl_fifo_f SRL_FIFO_I
3612 
       (.Bus_RNW_reg(Bus_RNW_reg),
3613 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
3614 
        .\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
3615 
        .Q(Q),
3616 
        .fifo_Read(fifo_Read),
3617 
        .fifo_wr(fifo_wr),
3618 
        .mux_Out(mux_Out),
3619 
        .\mux_sel_reg[0] (\mux_sel_reg_n_0_[0] ),
3620 
        .\mux_sel_reg[2] (\mux_sel_reg_n_0_[2] ),
3621 
        .p_4_in(p_4_in),
3622 
        .reset_TX_FIFO_reg(reset_TX_FIFO_reg),
3623 
        .s_axi_aclk(s_axi_aclk),
3624 
        .s_axi_aresetn(s_axi_aresetn),
3625 
        .s_axi_wdata(s_axi_wdata),
3626 
        .tx_Buffer_Full(tx_Buffer_Full),
3627 
        .tx_DataBits(tx_DataBits),
3628 
        .tx_Data_Enable_reg(tx_Data_Enable_reg_n_0),
3629 
        .tx_Start(tx_Start),
3630 
        .tx_Start0(tx_Start0));
3631 
  LUT3 #(
3632 
    .INIT(8'h31))
3633 
    TX_i_1
3634 
       (.I0(tx_DataBits),
3635 
        .I1(tx_Start),
3636 
        .I2(serial_Data),
3637 
        .O(TX0));
3638 
  FDSE TX_reg
3639 
       (.C(s_axi_aclk),
3640 
        .CE(1'b1),
3641 
        .D(TX0),
3642 
        .Q(tx),
3643 
        .S(SR));
3644 
  LUT4 #(
3645 
    .INIT(16'h0100))
3646 
    fifo_Read_i_1
3647 
       (.I0(\mux_sel_reg_n_0_[0] ),
3648 
        .I1(\mux_sel_reg_n_0_[2] ),
3649 
        .I2(p_4_in),
3650 
        .I3(tx_Data_Enable_reg_n_0),
3651 
        .O(fifo_Read0));
3652 
  FDRE fifo_Read_reg
3653 
       (.C(s_axi_aclk),
3654 
        .CE(1'b1),
3655 
        .D(fifo_Read0),
3656 
        .Q(fifo_Read),
3657 
        .R(SR));
3658 
  (* SOFT_HLUTNM = "soft_lutpair21" *)
3659 
  LUT5 #(
3660 
    .INIT(32'hE1F0F1F0))
3661 
    \mux_sel[0]_i_1
3662 
       (.I0(p_4_in),
3663 
        .I1(\mux_sel_reg_n_0_[2] ),
3664 
        .I2(\mux_sel_reg_n_0_[0] ),
3665 
        .I3(tx_Data_Enable_reg_n_0),
3666 
        .I4(tx_DataBits),
3667 
        .O(\mux_sel[0]_i_1_n_0 ));
3668 
  (* SOFT_HLUTNM = "soft_lutpair21" *)
3669 
  LUT5 #(
3670 
    .INIT(32'h99AAABAA))
3671 
    \mux_sel[1]_i_1
3672 
       (.I0(p_4_in),
3673 
        .I1(\mux_sel_reg_n_0_[2] ),
3674 
        .I2(\mux_sel_reg_n_0_[0] ),
3675 
        .I3(tx_Data_Enable_reg_n_0),
3676 
        .I4(tx_DataBits),
3677 
        .O(\mux_sel[1]_i_1_n_0 ));
3678 
  LUT5 #(
3679 
    .INIT(32'h7777888C))
3680 
    \mux_sel[2]_i_1
3681 
       (.I0(tx_DataBits),
3682 
        .I1(tx_Data_Enable_reg_n_0),
3683 
        .I2(\mux_sel_reg_n_0_[0] ),
3684 
        .I3(p_4_in),
3685 
        .I4(\mux_sel_reg_n_0_[2] ),
3686 
        .O(\mux_sel[2]_i_1_n_0 ));
3687 
  FDSE \mux_sel_reg[0]
3688 
       (.C(s_axi_aclk),
3689 
        .CE(1'b1),
3690 
        .D(\mux_sel[0]_i_1_n_0 ),
3691 
        .Q(\mux_sel_reg_n_0_[0] ),
3692 
        .S(SR));
3693 
  FDSE \mux_sel_reg[1]
3694 
       (.C(s_axi_aclk),
3695 
        .CE(1'b1),
3696 
        .D(\mux_sel[1]_i_1_n_0 ),
3697 
        .Q(p_4_in),
3698 
        .S(SR));
3699 
  FDSE \mux_sel_reg[2]
3700 
       (.C(s_axi_aclk),
3701 
        .CE(1'b1),
3702 
        .D(\mux_sel[2]_i_1_n_0 ),
3703 
        .Q(\mux_sel_reg_n_0_[2] ),
3704 
        .S(SR));
3705 
  FDRE serial_Data_reg
3706 
       (.C(s_axi_aclk),
3707 
        .CE(1'b1),
3708 
        .D(mux_Out),
3709 
        .Q(serial_Data),
3710 
        .R(SR));
3711 
  LUT4 #(
3712 
    .INIT(16'h0F08))
3713 
    tx_DataBits_i_1
3714 
       (.I0(tx_Start),
3715 
        .I1(tx_Data_Enable_reg_n_0),
3716 
        .I2(fifo_Read),
3717 
        .I3(tx_DataBits),
3718 
        .O(tx_DataBits0));
3719 
  FDRE tx_DataBits_reg
3720 
       (.C(s_axi_aclk),
3721 
        .CE(1'b1),
3722 
        .D(tx_DataBits0),
3723 
        .Q(tx_DataBits),
3724 
        .R(SR));
3725 
  FDRE tx_Data_Enable_reg
3726 
       (.C(s_axi_aclk),
3727 
        .CE(1'b1),
3728 
        .D(MID_START_BIT_SRL16_I_n_0),
3729 
        .Q(tx_Data_Enable_reg_n_0),
3730 
        .R(SR));
3731 
  FDRE tx_Start_reg
3732 
       (.C(s_axi_aclk),
3733 
        .CE(1'b1),
3734 
        .D(tx_Start0),
3735 
        .Q(tx_Start),
3736 
        .R(SR));
3737 
endmodule
3738 
`ifndef GLBL
3739 
`define GLBL
3740 
`timescale  1 ps / 1 ps
3741 
 
3742 
module glbl ();
3743 
 
3744 
    parameter ROC_WIDTH = 100000;
3745 
    parameter TOC_WIDTH = 0;
3746 
 
3747 
//--------   STARTUP Globals --------------
3748 
    wire GSR;
3749 
    wire GTS;
3750 
    wire GWE;
3751 
    wire PRLD;
3752 
    tri1 p_up_tmp;
3753 
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
3754 
 
3755 
    wire PROGB_GLBL;
3756 
    wire CCLKO_GLBL;
3757 
    wire FCSBO_GLBL;
3758 
    wire [3:0] DO_GLBL;
3759 
    wire [3:0] DI_GLBL;
3760 
 
3761 
    reg GSR_int;
3762 
    reg GTS_int;
3763 
    reg PRLD_int;
3764 
 
3765 
//--------   JTAG Globals --------------
3766 
    wire JTAG_TDO_GLBL;
3767 
    wire JTAG_TCK_GLBL;
3768 
    wire JTAG_TDI_GLBL;
3769 
    wire JTAG_TMS_GLBL;
3770 
    wire JTAG_TRST_GLBL;
3771 
 
3772 
    reg JTAG_CAPTURE_GLBL;
3773 
    reg JTAG_RESET_GLBL;
3774 
    reg JTAG_SHIFT_GLBL;
3775 
    reg JTAG_UPDATE_GLBL;
3776 
    reg JTAG_RUNTEST_GLBL;
3777 
 
3778 
    reg JTAG_SEL1_GLBL = 0;
3779 
    reg JTAG_SEL2_GLBL = 0 ;
3780 
    reg JTAG_SEL3_GLBL = 0;
3781 
    reg JTAG_SEL4_GLBL = 0;
3782 
 
3783 
    reg JTAG_USER_TDO1_GLBL = 1'bz;
3784 
    reg JTAG_USER_TDO2_GLBL = 1'bz;
3785 
    reg JTAG_USER_TDO3_GLBL = 1'bz;
3786 
    reg JTAG_USER_TDO4_GLBL = 1'bz;
3787 
 
3788 
    assign (strong1, weak0) GSR = GSR_int;
3789 
    assign (strong1, weak0) GTS = GTS_int;
3790 
    assign (weak1, weak0) PRLD = PRLD_int;
3791 
 
3792 
    initial begin
3793 
        GSR_int = 1'b1;
3794 
        PRLD_int = 1'b1;
3795 
        #(ROC_WIDTH)
3796 
        GSR_int = 1'b0;
3797 
        PRLD_int = 1'b0;
3798 
    end
3799 
 
3800 
    initial begin
3801 
        GTS_int = 1'b1;
3802 
        #(TOC_WIDTH)
3803 
        GTS_int = 1'b0;
3804 
    end
3805 
 
3806 
endmodule
3807 
`endif

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