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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [axi_uartlite_module_sim/] [axi_uartlite_module_sim_sim_netlist.vhdl] - Blame information for rev 2

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1 2 vv_gulyaev 
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
2 
-- --------------------------------------------------------------------------------
3 
-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
4 
-- Date        : Thu Jul 23 09:49:59 2020
5 
-- Host        : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)
6 
-- Command     : write_vhdl -force -mode funcsim -rename_top axi_uartlite_module_sim -prefix
7 
--               axi_uartlite_module_sim_ axi_uartlite_module_sim_netlist.vhdl
8 
-- Design      : axi_uartlite_module
9 
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
10 
--               synthesized. This netlist cannot be used for SDF annotated simulation.
11 
-- Device      : xc7k325tffg900-2
12 
-- --------------------------------------------------------------------------------
13 
library IEEE;
14 
use IEEE.STD_LOGIC_1164.ALL;
15 
library UNISIM;
16 
use UNISIM.VCOMPONENTS.ALL;
17 
entity axi_uartlite_module_sim_baudrate is
18 
  port (
19 
    en_16x_Baud : out STD_LOGIC;
20 
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
21 
    s_axi_aclk : in STD_LOGIC
22 
  );
23 
end axi_uartlite_module_sim_baudrate;
24 
 
25 
architecture STRUCTURE of axi_uartlite_module_sim_baudrate is
26 
  signal \^en_16x_baud\ : STD_LOGIC;
27 
  signal count : STD_LOGIC_VECTOR ( 7 downto 0 );
28 
  signal \count[2]_i_2_n_0\ : STD_LOGIC;
29 
  signal \count[3]_i_2_n_0\ : STD_LOGIC;
30 
  signal \count[4]_i_2_n_0\ : STD_LOGIC;
31 
  signal \count[7]_i_2_n_0\ : STD_LOGIC;
32 
  signal count_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
33 
  attribute SOFT_HLUTNM : string;
34 
  attribute SOFT_HLUTNM of EN_16x_Baud_i_1 : label is "soft_lutpair12";
35 
  attribute SOFT_HLUTNM of \count[1]_i_1\ : label is "soft_lutpair13";
36 
  attribute SOFT_HLUTNM of \count[2]_i_2\ : label is "soft_lutpair10";
37 
  attribute SOFT_HLUTNM of \count[3]_i_2\ : label is "soft_lutpair13";
38 
  attribute SOFT_HLUTNM of \count[4]_i_1\ : label is "soft_lutpair10";
39 
  attribute SOFT_HLUTNM of \count[4]_i_2\ : label is "soft_lutpair11";
40 
  attribute SOFT_HLUTNM of \count[6]_i_1\ : label is "soft_lutpair12";
41 
  attribute SOFT_HLUTNM of \count[7]_i_2\ : label is "soft_lutpair11";
42 
begin
43 
EN_16x_Baud_i_1: unisim.vcomponents.LUT4
44 
    generic map(
45 
      INIT => X"0001"
46 
    )
47 
        port map (
48 
      I0 => count(7),
49 
      I1 => count(5),
50 
      I2 => count(6),
51 
      I3 => \count[7]_i_2_n_0\,
52 
      O => \^en_16x_baud\
53 
    );
54 
EN_16x_Baud_reg: unisim.vcomponents.FDRE
55 
     port map (
56 
      C => s_axi_aclk,
57 
      CE => '1',
58 
      D => \^en_16x_baud\,
59 
      Q => en_16x_Baud,
60 
      R => SR(0)
61 
    );
62 
\count[0]_i_1\: unisim.vcomponents.LUT6
63 
    generic map(
64 
      INIT => X"0000FFFF0000FFFE"
65 
    )
66 
        port map (
67 
      I0 => count(3),
68 
      I1 => \count[2]_i_2_n_0\,
69 
      I2 => count(4),
70 
      I3 => count(2),
71 
      I4 => count(0),
72 
      I5 => count(1),
73 
      O => count_0(0)
74 
    );
75 
\count[1]_i_1\: unisim.vcomponents.LUT2
76 
    generic map(
77 
      INIT => X"9"
78 
    )
79 
        port map (
80 
      I0 => count(1),
81 
      I1 => count(0),
82 
      O => count_0(1)
83 
    );
84 
\count[2]_i_1\: unisim.vcomponents.LUT6
85 
    generic map(
86 
      INIT => X"E1E1E1E1E1E1E1E0"
87 
    )
88 
        port map (
89 
      I0 => count(1),
90 
      I1 => count(0),
91 
      I2 => count(2),
92 
      I3 => count(4),
93 
      I4 => \count[2]_i_2_n_0\,
94 
      I5 => count(3),
95 
      O => count_0(2)
96 
    );
97 
\count[2]_i_2\: unisim.vcomponents.LUT3
98 
    generic map(
99 
      INIT => X"FE"
100 
    )
101 
        port map (
102 
      I0 => count(6),
103 
      I1 => count(5),
104 
      I2 => count(7),
105 
      O => \count[2]_i_2_n_0\
106 
    );
107 
\count[3]_i_1\: unisim.vcomponents.LUT6
108 
    generic map(
109 
      INIT => X"9999999999999998"
110 
    )
111 
        port map (
112 
      I0 => \count[3]_i_2_n_0\,
113 
      I1 => count(3),
114 
      I2 => count(7),
115 
      I3 => count(5),
116 
      I4 => count(6),
117 
      I5 => count(4),
118 
      O => count_0(3)
119 
    );
120 
\count[3]_i_2\: unisim.vcomponents.LUT3
121 
    generic map(
122 
      INIT => X"FE"
123 
    )
124 
        port map (
125 
      I0 => count(1),
126 
      I1 => count(0),
127 
      I2 => count(2),
128 
      O => \count[3]_i_2_n_0\
129 
    );
130 
\count[4]_i_1\: unisim.vcomponents.LUT5
131 
    generic map(
132 
      INIT => X"99999998"
133 
    )
134 
        port map (
135 
      I0 => \count[4]_i_2_n_0\,
136 
      I1 => count(4),
137 
      I2 => count(6),
138 
      I3 => count(5),
139 
      I4 => count(7),
140 
      O => count_0(4)
141 
    );
142 
\count[4]_i_2\: unisim.vcomponents.LUT4
143 
    generic map(
144 
      INIT => X"FFFE"
145 
    )
146 
        port map (
147 
      I0 => count(2),
148 
      I1 => count(0),
149 
      I2 => count(1),
150 
      I3 => count(3),
151 
      O => \count[4]_i_2_n_0\
152 
    );
153 
\count[5]_i_1\: unisim.vcomponents.LUT6
154 
    generic map(
155 
      INIT => X"AAAAAAAAAAAAAAA9"
156 
    )
157 
        port map (
158 
      I0 => count(5),
159 
      I1 => count(3),
160 
      I2 => count(1),
161 
      I3 => count(0),
162 
      I4 => count(2),
163 
      I5 => count(4),
164 
      O => count_0(5)
165 
    );
166 
\count[6]_i_1\: unisim.vcomponents.LUT4
167 
    generic map(
168 
      INIT => X"C9C8"
169 
    )
170 
        port map (
171 
      I0 => \count[7]_i_2_n_0\,
172 
      I1 => count(6),
173 
      I2 => count(5),
174 
      I3 => count(7),
175 
      O => count_0(6)
176 
    );
177 
\count[7]_i_1\: unisim.vcomponents.LUT4
178 
    generic map(
179 
      INIT => X"FE01"
180 
    )
181 
        port map (
182 
      I0 => \count[7]_i_2_n_0\,
183 
      I1 => count(6),
184 
      I2 => count(5),
185 
      I3 => count(7),
186 
      O => count_0(7)
187 
    );
188 
\count[7]_i_2\: unisim.vcomponents.LUT5
189 
    generic map(
190 
      INIT => X"FFFFFFFE"
191 
    )
192 
        port map (
193 
      I0 => count(3),
194 
      I1 => count(1),
195 
      I2 => count(0),
196 
      I3 => count(2),
197 
      I4 => count(4),
198 
      O => \count[7]_i_2_n_0\
199 
    );
200 
\count_reg[0]\: unisim.vcomponents.FDRE
201 
     port map (
202 
      C => s_axi_aclk,
203 
      CE => '1',
204 
      D => count_0(0),
205 
      Q => count(0),
206 
      R => SR(0)
207 
    );
208 
\count_reg[1]\: unisim.vcomponents.FDRE
209 
     port map (
210 
      C => s_axi_aclk,
211 
      CE => '1',
212 
      D => count_0(1),
213 
      Q => count(1),
214 
      R => SR(0)
215 
    );
216 
\count_reg[2]\: unisim.vcomponents.FDRE
217 
     port map (
218 
      C => s_axi_aclk,
219 
      CE => '1',
220 
      D => count_0(2),
221 
      Q => count(2),
222 
      R => SR(0)
223 
    );
224 
\count_reg[3]\: unisim.vcomponents.FDRE
225 
     port map (
226 
      C => s_axi_aclk,
227 
      CE => '1',
228 
      D => count_0(3),
229 
      Q => count(3),
230 
      R => SR(0)
231 
    );
232 
\count_reg[4]\: unisim.vcomponents.FDRE
233 
     port map (
234 
      C => s_axi_aclk,
235 
      CE => '1',
236 
      D => count_0(4),
237 
      Q => count(4),
238 
      R => SR(0)
239 
    );
240 
\count_reg[5]\: unisim.vcomponents.FDRE
241 
     port map (
242 
      C => s_axi_aclk,
243 
      CE => '1',
244 
      D => count_0(5),
245 
      Q => count(5),
246 
      R => SR(0)
247 
    );
248 
\count_reg[6]\: unisim.vcomponents.FDRE
249 
     port map (
250 
      C => s_axi_aclk,
251 
      CE => '1',
252 
      D => count_0(6),
253 
      Q => count(6),
254 
      R => SR(0)
255 
    );
256 
\count_reg[7]\: unisim.vcomponents.FDRE
257 
     port map (
258 
      C => s_axi_aclk,
259 
      CE => '1',
260 
      D => count_0(7),
261 
      Q => count(7),
262 
      R => SR(0)
263 
    );
264 
end STRUCTURE;
265 
library IEEE;
266 
use IEEE.STD_LOGIC_1164.ALL;
267 
library UNISIM;
268 
use UNISIM.VCOMPONENTS.ALL;
269 
entity axi_uartlite_module_sim_cdc_sync is
270 
  port (
271 
    p_26_out : out STD_LOGIC;
272 
    scndry_out : out STD_LOGIC;
273 
    start_Edge_Detected : in STD_LOGIC;
274 
    EN_16x_Baud_reg : in STD_LOGIC;
275 
    s_axi_aresetn : in STD_LOGIC;
276 
    \in\ : in STD_LOGIC_VECTOR ( 0 to 0 );
277 
    rx : in STD_LOGIC;
278 
    s_axi_aclk : in STD_LOGIC
279 
  );
280 
end axi_uartlite_module_sim_cdc_sync;
281 
 
282 
architecture STRUCTURE of axi_uartlite_module_sim_cdc_sync is
283 
  signal s_level_out_d1_cdc_to : STD_LOGIC;
284 
  signal s_level_out_d2 : STD_LOGIC;
285 
  signal s_level_out_d3 : STD_LOGIC;
286 
  signal \^scndry_out\ : STD_LOGIC;
287 
  attribute ASYNC_REG : boolean;
288 
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
289 
  attribute XILINX_LEGACY_PRIM : string;
290 
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
291 
  attribute box_type : string;
292 
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
293 
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
294 
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
295 
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
296 
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
297 
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
298 
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
299 
  attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
300 
  attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
301 
  attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
302 
begin
303 
  scndry_out <= \^scndry_out\;
304 
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
305 
    generic map(
306 
      INIT => '0'
307 
    )
308 
        port map (
309 
      C => s_axi_aclk,
310 
      CE => '1',
311 
      D => rx,
312 
      Q => s_level_out_d1_cdc_to,
313 
      R => '0'
314 
    );
315 
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
316 
    generic map(
317 
      INIT => '0'
318 
    )
319 
        port map (
320 
      C => s_axi_aclk,
321 
      CE => '1',
322 
      D => s_level_out_d1_cdc_to,
323 
      Q => s_level_out_d2,
324 
      R => '0'
325 
    );
326 
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
327 
    generic map(
328 
      INIT => '0'
329 
    )
330 
        port map (
331 
      C => s_axi_aclk,
332 
      CE => '1',
333 
      D => s_level_out_d2,
334 
      Q => s_level_out_d3,
335 
      R => '0'
336 
    );
337 
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
338 
    generic map(
339 
      INIT => '0'
340 
    )
341 
        port map (
342 
      C => s_axi_aclk,
343 
      CE => '1',
344 
      D => s_level_out_d3,
345 
      Q => \^scndry_out\,
346 
      R => '0'
347 
    );
348 
\SERIAL_TO_PARALLEL[1].fifo_din[1]_i_1\: unisim.vcomponents.LUT5
349 
    generic map(
350 
      INIT => X"FE00CE00"
351 
    )
352 
        port map (
353 
      I0 => \^scndry_out\,
354 
      I1 => start_Edge_Detected,
355 
      I2 => EN_16x_Baud_reg,
356 
      I3 => s_axi_aresetn,
357 
      I4 => \in\(0),
358 
      O => p_26_out
359 
    );
360 
end STRUCTURE;
361 
library IEEE;
362 
use IEEE.STD_LOGIC_1164.ALL;
363 
library UNISIM;
364 
use UNISIM.VCOMPONENTS.ALL;
365 
entity axi_uartlite_module_sim_cntr_incr_decr_addn_f is
366 
  port (
367 
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
368 
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
369 
    fifo_full_p1 : out STD_LOGIC;
370 
    tx_Start0 : out STD_LOGIC;
371 
    reset_TX_FIFO_reg : in STD_LOGIC;
372 
    s_axi_aresetn : in STD_LOGIC;
373 
    fifo_Read : in STD_LOGIC;
374 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
375 
    tx_Buffer_Full : in STD_LOGIC;
376 
    Bus_RNW_reg : in STD_LOGIC;
377 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
378 
    tx_Data_Enable_reg : in STD_LOGIC;
379 
    tx_DataBits : in STD_LOGIC;
380 
    tx_Start : in STD_LOGIC;
381 
    s_axi_aclk : in STD_LOGIC
382 
  );
383 
end axi_uartlite_module_sim_cntr_incr_decr_addn_f;
384 
 
385 
architecture STRUCTURE of axi_uartlite_module_sim_cntr_incr_decr_addn_f is
386 
  signal \FIFO_Full_i_2__0_n_0\ : STD_LOGIC;
387 
  signal \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\ : STD_LOGIC;
388 
  signal \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\ : STD_LOGIC;
389 
  signal \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\ : STD_LOGIC;
390 
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
391 
  signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
392 
  signal addr_i_p1 : STD_LOGIC_VECTOR ( 4 downto 0 );
393 
  attribute SOFT_HLUTNM : string;
394 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[1]_i_1__0\ : label is "soft_lutpair19";
395 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[3]_i_2__0\ : label is "soft_lutpair19";
396 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_3__0\ : label is "soft_lutpair20";
397 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_4__0\ : label is "soft_lutpair20";
398 
begin
399 
  Q(4 downto 0) <= \^q\(4 downto 0);
400 
  SS(0) <= \^ss\(0);
401 
\FIFO_Full_i_1__0\: unisim.vcomponents.LUT6
402 
    generic map(
403 
      INIT => X"0000000004090000"
404 
    )
405 
        port map (
406 
      I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
407 
      I1 => \^q\(0),
408 
      I2 => \^q\(4),
409 
      I3 => fifo_Read,
410 
      I4 => \^q\(3),
411 
      I5 => \FIFO_Full_i_2__0_n_0\,
412 
      O => fifo_full_p1
413 
    );
414 
\FIFO_Full_i_2__0\: unisim.vcomponents.LUT2
415 
    generic map(
416 
      INIT => X"7"
417 
    )
418 
        port map (
419 
      I0 => \^q\(1),
420 
      I1 => \^q\(2),
421 
      O => \FIFO_Full_i_2__0_n_0\
422 
    );
423 
\INFERRED_GEN.cnt_i[0]_i_1__0\: unisim.vcomponents.LUT6
424 
    generic map(
425 
      INIT => X"BBB4BBBB444B4444"
426 
    )
427 
        port map (
428 
      I0 => \^q\(4),
429 
      I1 => fifo_Read,
430 
      I2 => tx_Buffer_Full,
431 
      I3 => Bus_RNW_reg,
432 
      I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
433 
      I5 => \^q\(0),
434 
      O => addr_i_p1(0)
435 
    );
436 
\INFERRED_GEN.cnt_i[1]_i_1__0\: unisim.vcomponents.LUT5
437 
    generic map(
438 
      INIT => X"AA9A65AA"
439 
    )
440 
        port map (
441 
      I0 => \^q\(1),
442 
      I1 => \^q\(4),
443 
      I2 => fifo_Read,
444 
      I3 => \^q\(0),
445 
      I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
446 
      O => addr_i_p1(1)
447 
    );
448 
\INFERRED_GEN.cnt_i[2]_i_1__0\: unisim.vcomponents.LUT6
449 
    generic map(
450 
      INIT => X"F4FF0B00FFBF0040"
451 
    )
452 
        port map (
453 
      I0 => \^q\(4),
454 
      I1 => fifo_Read,
455 
      I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
456 
      I3 => \^q\(0),
457 
      I4 => \^q\(2),
458 
      I5 => \^q\(1),
459 
      O => addr_i_p1(2)
460 
    );
461 
\INFERRED_GEN.cnt_i[3]_i_1__0\: unisim.vcomponents.LUT6
462 
    generic map(
463 
      INIT => X"AAAA6AAAAAA9AAAA"
464 
    )
465 
        port map (
466 
      I0 => \^q\(3),
467 
      I1 => \^q\(1),
468 
      I2 => \^q\(2),
469 
      I3 => \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\,
470 
      I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
471 
      I5 => \^q\(0),
472 
      O => addr_i_p1(3)
473 
    );
474 
\INFERRED_GEN.cnt_i[3]_i_2__0\: unisim.vcomponents.LUT2
475 
    generic map(
476 
      INIT => X"B"
477 
    )
478 
        port map (
479 
      I0 => \^q\(4),
480 
      I1 => fifo_Read,
481 
      O => \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\
482 
    );
483 
\INFERRED_GEN.cnt_i[4]_i_1__0\: unisim.vcomponents.LUT2
484 
    generic map(
485 
      INIT => X"B"
486 
    )
487 
        port map (
488 
      I0 => reset_TX_FIFO_reg,
489 
      I1 => s_axi_aresetn,
490 
      O => \^ss\(0)
491 
    );
492 
\INFERRED_GEN.cnt_i[4]_i_2__0\: unisim.vcomponents.LUT6
493 
    generic map(
494 
      INIT => X"F0F0FAFAF003F0F0"
495 
    )
496 
        port map (
497 
      I0 => \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\,
498 
      I1 => fifo_Read,
499 
      I2 => \^q\(4),
500 
      I3 => \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\,
501 
      I4 => \^q\(0),
502 
      I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
503 
      O => addr_i_p1(4)
504 
    );
505 
\INFERRED_GEN.cnt_i[4]_i_3__0\: unisim.vcomponents.LUT4
506 
    generic map(
507 
      INIT => X"0004"
508 
    )
509 
        port map (
510 
      I0 => \^q\(3),
511 
      I1 => fifo_Read,
512 
      I2 => \^q\(2),
513 
      I3 => \^q\(1),
514 
      O => \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\
515 
    );
516 
\INFERRED_GEN.cnt_i[4]_i_4__0\: unisim.vcomponents.LUT3
517 
    generic map(
518 
      INIT => X"7F"
519 
    )
520 
        port map (
521 
      I0 => \^q\(2),
522 
      I1 => \^q\(1),
523 
      I2 => \^q\(3),
524 
      O => \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\
525 
    );
526 
\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE
527 
     port map (
528 
      C => s_axi_aclk,
529 
      CE => '1',
530 
      D => addr_i_p1(0),
531 
      Q => \^q\(0),
532 
      S => \^ss\(0)
533 
    );
534 
\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE
535 
     port map (
536 
      C => s_axi_aclk,
537 
      CE => '1',
538 
      D => addr_i_p1(1),
539 
      Q => \^q\(1),
540 
      S => \^ss\(0)
541 
    );
542 
\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE
543 
     port map (
544 
      C => s_axi_aclk,
545 
      CE => '1',
546 
      D => addr_i_p1(2),
547 
      Q => \^q\(2),
548 
      S => \^ss\(0)
549 
    );
550 
\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE
551 
     port map (
552 
      C => s_axi_aclk,
553 
      CE => '1',
554 
      D => addr_i_p1(3),
555 
      Q => \^q\(3),
556 
      S => \^ss\(0)
557 
    );
558 
\INFERRED_GEN.cnt_i_reg[4]\: unisim.vcomponents.FDSE
559 
     port map (
560 
      C => s_axi_aclk,
561 
      CE => '1',
562 
      D => addr_i_p1(4),
563 
      Q => \^q\(4),
564 
      S => \^ss\(0)
565 
    );
566 
tx_Start_i_1: unisim.vcomponents.LUT4
567 
    generic map(
568 
      INIT => X"0F02"
569 
    )
570 
        port map (
571 
      I0 => tx_Data_Enable_reg,
572 
      I1 => \^q\(4),
573 
      I2 => tx_DataBits,
574 
      I3 => tx_Start,
575 
      O => tx_Start0
576 
    );
577 
end STRUCTURE;
578 
library IEEE;
579 
use IEEE.STD_LOGIC_1164.ALL;
580 
library UNISIM;
581 
use UNISIM.VCOMPONENTS.ALL;
582 
entity axi_uartlite_module_sim_cntr_incr_decr_addn_f_2 is
583 
  port (
584 
    SS : out STD_LOGIC_VECTOR ( 0 to 0 );
585 
    fifo_full_p1 : out STD_LOGIC;
586 
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
587 
    Interrupt0 : out STD_LOGIC;
588 
    reset_RX_FIFO_reg : in STD_LOGIC;
589 
    s_axi_aresetn : in STD_LOGIC;
590 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
591 
    Bus_RNW_reg : in STD_LOGIC;
592 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
593 
    Bus_RNW_reg_reg : in STD_LOGIC;
594 
    fifo_Write : in STD_LOGIC;
595 
    FIFO_Full_reg : in STD_LOGIC;
596 
    valid_rx : in STD_LOGIC;
597 
    rx_Data_Present_Pre : in STD_LOGIC;
598 
    enable_interrupts : in STD_LOGIC;
599 
    \INFERRED_GEN.cnt_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
600 
    tx_Buffer_Empty_Pre : in STD_LOGIC;
601 
    s_axi_aclk : in STD_LOGIC
602 
  );
603 
  attribute ORIG_REF_NAME : string;
604 
  attribute ORIG_REF_NAME of axi_uartlite_module_sim_cntr_incr_decr_addn_f_2 : entity is "cntr_incr_decr_addn_f";
605 
end axi_uartlite_module_sim_cntr_incr_decr_addn_f_2;
606 
 
607 
architecture STRUCTURE of axi_uartlite_module_sim_cntr_incr_decr_addn_f_2 is
608 
  signal FIFO_Full_i_2_n_0 : STD_LOGIC;
609 
  signal \INFERRED_GEN.cnt_i[4]_i_4_n_0\ : STD_LOGIC;
610 
  signal \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\ : STD_LOGIC;
611 
  signal \INFERRED_GEN.cnt_i[4]_i_6_n_0\ : STD_LOGIC;
612 
  signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
613 
  signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
614 
  signal addr_i_p1 : STD_LOGIC_VECTOR ( 4 downto 0 );
615 
  attribute SOFT_HLUTNM : string;
616 
  attribute SOFT_HLUTNM of FIFO_Full_i_2 : label is "soft_lutpair17";
617 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1\ : label is "soft_lutpair17";
618 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_4\ : label is "soft_lutpair18";
619 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_5__0\ : label is "soft_lutpair18";
620 
begin
621 
  Q(4 downto 0) <= \^q\(4 downto 0);
622 
  SS(0) <= \^ss\(0);
623 
FIFO_Full_i_1: unisim.vcomponents.LUT6
624 
    generic map(
625 
      INIT => X"0000000009040000"
626 
    )
627 
        port map (
628 
      I0 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
629 
      I1 => \^q\(0),
630 
      I2 => \^q\(4),
631 
      I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
632 
      I4 => \^q\(3),
633 
      I5 => FIFO_Full_i_2_n_0,
634 
      O => fifo_full_p1
635 
    );
636 
FIFO_Full_i_2: unisim.vcomponents.LUT2
637 
    generic map(
638 
      INIT => X"7"
639 
    )
640 
        port map (
641 
      I0 => \^q\(1),
642 
      I1 => \^q\(2),
643 
      O => FIFO_Full_i_2_n_0
644 
    );
645 
\INFERRED_GEN.cnt_i[0]_i_1\: unisim.vcomponents.LUT5
646 
    generic map(
647 
      INIT => X"F70808F7"
648 
    )
649 
        port map (
650 
      I0 => Bus_RNW_reg,
651 
      I1 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
652 
      I2 => \^q\(4),
653 
      I3 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
654 
      I4 => \^q\(0),
655 
      O => addr_i_p1(0)
656 
    );
657 
\INFERRED_GEN.cnt_i[1]_i_1\: unisim.vcomponents.LUT6
658 
    generic map(
659 
      INIT => X"AAAAAA6A5595AAAA"
660 
    )
661 
        port map (
662 
      I0 => \^q\(1),
663 
      I1 => Bus_RNW_reg,
664 
      I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
665 
      I3 => \^q\(4),
666 
      I4 => \^q\(0),
667 
      I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
668 
      O => addr_i_p1(1)
669 
    );
670 
\INFERRED_GEN.cnt_i[2]_i_1\: unisim.vcomponents.LUT5
671 
    generic map(
672 
      INIT => X"FE017F80"
673 
    )
674 
        port map (
675 
      I0 => \^q\(0),
676 
      I1 => Bus_RNW_reg_reg,
677 
      I2 => \^q\(1),
678 
      I3 => \^q\(2),
679 
      I4 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
680 
      O => addr_i_p1(2)
681 
    );
682 
\INFERRED_GEN.cnt_i[3]_i_1\: unisim.vcomponents.LUT6
683 
    generic map(
684 
      INIT => X"F0F0F0E178F0F0F0"
685 
    )
686 
        port map (
687 
      I0 => \^q\(0),
688 
      I1 => Bus_RNW_reg_reg,
689 
      I2 => \^q\(3),
690 
      I3 => \^q\(1),
691 
      I4 => \^q\(2),
692 
      I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
693 
      O => addr_i_p1(3)
694 
    );
695 
\INFERRED_GEN.cnt_i[4]_i_1\: unisim.vcomponents.LUT2
696 
    generic map(
697 
      INIT => X"B"
698 
    )
699 
        port map (
700 
      I0 => reset_RX_FIFO_reg,
701 
      I1 => s_axi_aresetn,
702 
      O => \^ss\(0)
703 
    );
704 
\INFERRED_GEN.cnt_i[4]_i_2\: unisim.vcomponents.LUT6
705 
    generic map(
706 
      INIT => X"F0F0F4F4F00AF0F0"
707 
    )
708 
        port map (
709 
      I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
710 
      I1 => \INFERRED_GEN.cnt_i[4]_i_4_n_0\,
711 
      I2 => \^q\(4),
712 
      I3 => \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\,
713 
      I4 => \^q\(0),
714 
      I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
715 
      O => addr_i_p1(4)
716 
    );
717 
\INFERRED_GEN.cnt_i[4]_i_4\: unisim.vcomponents.LUT3
718 
    generic map(
719 
      INIT => X"01"
720 
    )
721 
        port map (
722 
      I0 => \^q\(2),
723 
      I1 => \^q\(1),
724 
      I2 => \^q\(3),
725 
      O => \INFERRED_GEN.cnt_i[4]_i_4_n_0\
726 
    );
727 
\INFERRED_GEN.cnt_i[4]_i_5__0\: unisim.vcomponents.LUT3
728 
    generic map(
729 
      INIT => X"7F"
730 
    )
731 
        port map (
732 
      I0 => \^q\(2),
733 
      I1 => \^q\(1),
734 
      I2 => \^q\(3),
735 
      O => \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\
736 
    );
737 
\INFERRED_GEN.cnt_i[4]_i_6\: unisim.vcomponents.LUT3
738 
    generic map(
739 
      INIT => X"DF"
740 
    )
741 
        port map (
742 
      I0 => fifo_Write,
743 
      I1 => FIFO_Full_reg,
744 
      I2 => valid_rx,
745 
      O => \INFERRED_GEN.cnt_i[4]_i_6_n_0\
746 
    );
747 
\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE
748 
     port map (
749 
      C => s_axi_aclk,
750 
      CE => '1',
751 
      D => addr_i_p1(0),
752 
      Q => \^q\(0),
753 
      S => \^ss\(0)
754 
    );
755 
\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE
756 
     port map (
757 
      C => s_axi_aclk,
758 
      CE => '1',
759 
      D => addr_i_p1(1),
760 
      Q => \^q\(1),
761 
      S => \^ss\(0)
762 
    );
763 
\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE
764 
     port map (
765 
      C => s_axi_aclk,
766 
      CE => '1',
767 
      D => addr_i_p1(2),
768 
      Q => \^q\(2),
769 
      S => \^ss\(0)
770 
    );
771 
\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE
772 
     port map (
773 
      C => s_axi_aclk,
774 
      CE => '1',
775 
      D => addr_i_p1(3),
776 
      Q => \^q\(3),
777 
      S => \^ss\(0)
778 
    );
779 
\INFERRED_GEN.cnt_i_reg[4]\: unisim.vcomponents.FDSE
780 
     port map (
781 
      C => s_axi_aclk,
782 
      CE => '1',
783 
      D => addr_i_p1(4),
784 
      Q => \^q\(4),
785 
      S => \^ss\(0)
786 
    );
787 
Interrupt_i_2: unisim.vcomponents.LUT5
788 
    generic map(
789 
      INIT => X"1010F010"
790 
    )
791 
        port map (
792 
      I0 => rx_Data_Present_Pre,
793 
      I1 => \^q\(4),
794 
      I2 => enable_interrupts,
795 
      I3 => \INFERRED_GEN.cnt_i_reg[4]_0\(0),
796 
      I4 => tx_Buffer_Empty_Pre,
797 
      O => Interrupt0
798 
    );
799 
end STRUCTURE;
800 
library IEEE;
801 
use IEEE.STD_LOGIC_1164.ALL;
802 
library UNISIM;
803 
use UNISIM.VCOMPONENTS.ALL;
804 
entity axi_uartlite_module_sim_dynshreg_f is
805 
  port (
806 
    mux_Out : out STD_LOGIC;
807 
    p_4_in : in STD_LOGIC;
808 
    \mux_sel_reg[2]\ : in STD_LOGIC;
809 
    \mux_sel_reg[0]\ : in STD_LOGIC;
810 
    fifo_wr : in STD_LOGIC;
811 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
812 
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
813 
    s_axi_aclk : in STD_LOGIC
814 
  );
815 
end axi_uartlite_module_sim_dynshreg_f;
816 
 
817 
architecture STRUCTURE of axi_uartlite_module_sim_dynshreg_f is
818 
  signal fifo_DOut : STD_LOGIC_VECTOR ( 0 to 7 );
819 
  signal serial_Data_i_2_n_0 : STD_LOGIC;
820 
  signal serial_Data_i_3_n_0 : STD_LOGIC;
821 
  signal serial_Data_i_4_n_0 : STD_LOGIC;
822 
  signal serial_Data_i_5_n_0 : STD_LOGIC;
823 
  attribute srl_bus_name : string;
824 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
825 
  attribute srl_name : string;
826 
  attribute srl_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ";
827 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
828 
  attribute srl_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ";
829 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
830 
  attribute srl_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ";
831 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
832 
  attribute srl_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ";
833 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
834 
  attribute srl_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ";
835 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
836 
  attribute srl_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ";
837 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
838 
  attribute srl_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ";
839 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
840 
  attribute srl_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ";
841 
begin
842 
\INFERRED_GEN.data_reg[15][0]_srl16\: unisim.vcomponents.SRL16E
843 
    generic map(
844 
      INIT => X"0000"
845 
    )
846 
        port map (
847 
      A0 => Q(0),
848 
      A1 => Q(1),
849 
      A2 => Q(2),
850 
      A3 => Q(3),
851 
      CE => fifo_wr,
852 
      CLK => s_axi_aclk,
853 
      D => s_axi_wdata(7),
854 
      Q => fifo_DOut(0)
855 
    );
856 
\INFERRED_GEN.data_reg[15][1]_srl16\: unisim.vcomponents.SRL16E
857 
    generic map(
858 
      INIT => X"0000"
859 
    )
860 
        port map (
861 
      A0 => Q(0),
862 
      A1 => Q(1),
863 
      A2 => Q(2),
864 
      A3 => Q(3),
865 
      CE => fifo_wr,
866 
      CLK => s_axi_aclk,
867 
      D => s_axi_wdata(6),
868 
      Q => fifo_DOut(1)
869 
    );
870 
\INFERRED_GEN.data_reg[15][2]_srl16\: unisim.vcomponents.SRL16E
871 
    generic map(
872 
      INIT => X"0000"
873 
    )
874 
        port map (
875 
      A0 => Q(0),
876 
      A1 => Q(1),
877 
      A2 => Q(2),
878 
      A3 => Q(3),
879 
      CE => fifo_wr,
880 
      CLK => s_axi_aclk,
881 
      D => s_axi_wdata(5),
882 
      Q => fifo_DOut(2)
883 
    );
884 
\INFERRED_GEN.data_reg[15][3]_srl16\: unisim.vcomponents.SRL16E
885 
    generic map(
886 
      INIT => X"0000"
887 
    )
888 
        port map (
889 
      A0 => Q(0),
890 
      A1 => Q(1),
891 
      A2 => Q(2),
892 
      A3 => Q(3),
893 
      CE => fifo_wr,
894 
      CLK => s_axi_aclk,
895 
      D => s_axi_wdata(4),
896 
      Q => fifo_DOut(3)
897 
    );
898 
\INFERRED_GEN.data_reg[15][4]_srl16\: unisim.vcomponents.SRL16E
899 
    generic map(
900 
      INIT => X"0000"
901 
    )
902 
        port map (
903 
      A0 => Q(0),
904 
      A1 => Q(1),
905 
      A2 => Q(2),
906 
      A3 => Q(3),
907 
      CE => fifo_wr,
908 
      CLK => s_axi_aclk,
909 
      D => s_axi_wdata(3),
910 
      Q => fifo_DOut(4)
911 
    );
912 
\INFERRED_GEN.data_reg[15][5]_srl16\: unisim.vcomponents.SRL16E
913 
    generic map(
914 
      INIT => X"0000"
915 
    )
916 
        port map (
917 
      A0 => Q(0),
918 
      A1 => Q(1),
919 
      A2 => Q(2),
920 
      A3 => Q(3),
921 
      CE => fifo_wr,
922 
      CLK => s_axi_aclk,
923 
      D => s_axi_wdata(2),
924 
      Q => fifo_DOut(5)
925 
    );
926 
\INFERRED_GEN.data_reg[15][6]_srl16\: unisim.vcomponents.SRL16E
927 
    generic map(
928 
      INIT => X"0000"
929 
    )
930 
        port map (
931 
      A0 => Q(0),
932 
      A1 => Q(1),
933 
      A2 => Q(2),
934 
      A3 => Q(3),
935 
      CE => fifo_wr,
936 
      CLK => s_axi_aclk,
937 
      D => s_axi_wdata(1),
938 
      Q => fifo_DOut(6)
939 
    );
940 
\INFERRED_GEN.data_reg[15][7]_srl16\: unisim.vcomponents.SRL16E
941 
    generic map(
942 
      INIT => X"0000"
943 
    )
944 
        port map (
945 
      A0 => Q(0),
946 
      A1 => Q(1),
947 
      A2 => Q(2),
948 
      A3 => Q(3),
949 
      CE => fifo_wr,
950 
      CLK => s_axi_aclk,
951 
      D => s_axi_wdata(0),
952 
      Q => fifo_DOut(7)
953 
    );
954 
serial_Data_i_1: unisim.vcomponents.LUT4
955 
    generic map(
956 
      INIT => X"FFFE"
957 
    )
958 
        port map (
959 
      I0 => serial_Data_i_2_n_0,
960 
      I1 => serial_Data_i_3_n_0,
961 
      I2 => serial_Data_i_4_n_0,
962 
      I3 => serial_Data_i_5_n_0,
963 
      O => mux_Out
964 
    );
965 
serial_Data_i_2: unisim.vcomponents.LUT5
966 
    generic map(
967 
      INIT => X"44400040"
968 
    )
969 
        port map (
970 
      I0 => \mux_sel_reg[2]\,
971 
      I1 => p_4_in,
972 
      I2 => fifo_DOut(2),
973 
      I3 => \mux_sel_reg[0]\,
974 
      I4 => fifo_DOut(6),
975 
      O => serial_Data_i_2_n_0
976 
    );
977 
serial_Data_i_3: unisim.vcomponents.LUT5
978 
    generic map(
979 
      INIT => X"88800080"
980 
    )
981 
        port map (
982 
      I0 => \mux_sel_reg[0]\,
983 
      I1 => \mux_sel_reg[2]\,
984 
      I2 => fifo_DOut(5),
985 
      I3 => p_4_in,
986 
      I4 => fifo_DOut(7),
987 
      O => serial_Data_i_3_n_0
988 
    );
989 
serial_Data_i_4: unisim.vcomponents.LUT5
990 
    generic map(
991 
      INIT => X"44400040"
992 
    )
993 
        port map (
994 
      I0 => \mux_sel_reg[0]\,
995 
      I1 => \mux_sel_reg[2]\,
996 
      I2 => fifo_DOut(1),
997 
      I3 => p_4_in,
998 
      I4 => fifo_DOut(3),
999 
      O => serial_Data_i_4_n_0
1000 
    );
1001 
serial_Data_i_5: unisim.vcomponents.LUT5
1002 
    generic map(
1003 
      INIT => X"000A000C"
1004 
    )
1005 
        port map (
1006 
      I0 => fifo_DOut(4),
1007 
      I1 => fifo_DOut(0),
1008 
      I2 => p_4_in,
1009 
      I3 => \mux_sel_reg[2]\,
1010 
      I4 => \mux_sel_reg[0]\,
1011 
      O => serial_Data_i_5_n_0
1012 
    );
1013 
end STRUCTURE;
1014 
library IEEE;
1015 
use IEEE.STD_LOGIC_1164.ALL;
1016 
library UNISIM;
1017 
use UNISIM.VCOMPONENTS.ALL;
1018 
entity axi_uartlite_module_sim_dynshreg_f_3 is
1019 
  port (
1020 
    \out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
1021 
    valid_rx : in STD_LOGIC;
1022 
    FIFO_Full_reg : in STD_LOGIC;
1023 
    fifo_Write : in STD_LOGIC;
1024 
    \in\ : in STD_LOGIC_VECTOR ( 0 to 7 );
1025 
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
1026 
    s_axi_aclk : in STD_LOGIC
1027 
  );
1028 
  attribute ORIG_REF_NAME : string;
1029 
  attribute ORIG_REF_NAME of axi_uartlite_module_sim_dynshreg_f_3 : entity is "dynshreg_f";
1030 
end axi_uartlite_module_sim_dynshreg_f_3;
1031 
 
1032 
architecture STRUCTURE of axi_uartlite_module_sim_dynshreg_f_3 is
1033 
  signal fifo_wr : STD_LOGIC;
1034 
  attribute srl_bus_name : string;
1035 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
1036 
  attribute srl_name : string;
1037 
  attribute srl_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ";
1038 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
1039 
  attribute srl_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ";
1040 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
1041 
  attribute srl_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ";
1042 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
1043 
  attribute srl_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ";
1044 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
1045 
  attribute srl_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ";
1046 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
1047 
  attribute srl_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ";
1048 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
1049 
  attribute srl_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ";
1050 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
1051 
  attribute srl_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ";
1052 
begin
1053 
\INFERRED_GEN.data_reg[15][0]_srl16\: unisim.vcomponents.SRL16E
1054 
    generic map(
1055 
      INIT => X"0000"
1056 
    )
1057 
        port map (
1058 
      A0 => Q(0),
1059 
      A1 => Q(1),
1060 
      A2 => Q(2),
1061 
      A3 => Q(3),
1062 
      CE => fifo_wr,
1063 
      CLK => s_axi_aclk,
1064 
      D => \in\(0),
1065 
      Q => \out\(7)
1066 
    );
1067 
\INFERRED_GEN.data_reg[15][1]_srl16\: unisim.vcomponents.SRL16E
1068 
    generic map(
1069 
      INIT => X"0000"
1070 
    )
1071 
        port map (
1072 
      A0 => Q(0),
1073 
      A1 => Q(1),
1074 
      A2 => Q(2),
1075 
      A3 => Q(3),
1076 
      CE => fifo_wr,
1077 
      CLK => s_axi_aclk,
1078 
      D => \in\(1),
1079 
      Q => \out\(6)
1080 
    );
1081 
\INFERRED_GEN.data_reg[15][2]_srl16\: unisim.vcomponents.SRL16E
1082 
    generic map(
1083 
      INIT => X"0000"
1084 
    )
1085 
        port map (
1086 
      A0 => Q(0),
1087 
      A1 => Q(1),
1088 
      A2 => Q(2),
1089 
      A3 => Q(3),
1090 
      CE => fifo_wr,
1091 
      CLK => s_axi_aclk,
1092 
      D => \in\(2),
1093 
      Q => \out\(5)
1094 
    );
1095 
\INFERRED_GEN.data_reg[15][3]_srl16\: unisim.vcomponents.SRL16E
1096 
    generic map(
1097 
      INIT => X"0000"
1098 
    )
1099 
        port map (
1100 
      A0 => Q(0),
1101 
      A1 => Q(1),
1102 
      A2 => Q(2),
1103 
      A3 => Q(3),
1104 
      CE => fifo_wr,
1105 
      CLK => s_axi_aclk,
1106 
      D => \in\(3),
1107 
      Q => \out\(4)
1108 
    );
1109 
\INFERRED_GEN.data_reg[15][4]_srl16\: unisim.vcomponents.SRL16E
1110 
    generic map(
1111 
      INIT => X"0000"
1112 
    )
1113 
        port map (
1114 
      A0 => Q(0),
1115 
      A1 => Q(1),
1116 
      A2 => Q(2),
1117 
      A3 => Q(3),
1118 
      CE => fifo_wr,
1119 
      CLK => s_axi_aclk,
1120 
      D => \in\(4),
1121 
      Q => \out\(3)
1122 
    );
1123 
\INFERRED_GEN.data_reg[15][5]_srl16\: unisim.vcomponents.SRL16E
1124 
    generic map(
1125 
      INIT => X"0000"
1126 
    )
1127 
        port map (
1128 
      A0 => Q(0),
1129 
      A1 => Q(1),
1130 
      A2 => Q(2),
1131 
      A3 => Q(3),
1132 
      CE => fifo_wr,
1133 
      CLK => s_axi_aclk,
1134 
      D => \in\(5),
1135 
      Q => \out\(2)
1136 
    );
1137 
\INFERRED_GEN.data_reg[15][6]_srl16\: unisim.vcomponents.SRL16E
1138 
    generic map(
1139 
      INIT => X"0000"
1140 
    )
1141 
        port map (
1142 
      A0 => Q(0),
1143 
      A1 => Q(1),
1144 
      A2 => Q(2),
1145 
      A3 => Q(3),
1146 
      CE => fifo_wr,
1147 
      CLK => s_axi_aclk,
1148 
      D => \in\(6),
1149 
      Q => \out\(1)
1150 
    );
1151 
\INFERRED_GEN.data_reg[15][7]_srl16\: unisim.vcomponents.SRL16E
1152 
    generic map(
1153 
      INIT => X"0000"
1154 
    )
1155 
        port map (
1156 
      A0 => Q(0),
1157 
      A1 => Q(1),
1158 
      A2 => Q(2),
1159 
      A3 => Q(3),
1160 
      CE => fifo_wr,
1161 
      CLK => s_axi_aclk,
1162 
      D => \in\(7),
1163 
      Q => \out\(0)
1164 
    );
1165 
\INFERRED_GEN.data_reg[15][7]_srl16_i_1__0\: unisim.vcomponents.LUT3
1166 
    generic map(
1167 
      INIT => X"20"
1168 
    )
1169 
        port map (
1170 
      I0 => valid_rx,
1171 
      I1 => FIFO_Full_reg,
1172 
      I2 => fifo_Write,
1173 
      O => fifo_wr
1174 
    );
1175 
end STRUCTURE;
1176 
library IEEE;
1177 
use IEEE.STD_LOGIC_1164.ALL;
1178 
library UNISIM;
1179 
use UNISIM.VCOMPONENTS.ALL;
1180 
entity axi_uartlite_module_sim_dynshreg_i_f is
1181 
  port (
1182 
    p_20_out : out STD_LOGIC;
1183 
    \SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ : out STD_LOGIC;
1184 
    p_17_out : out STD_LOGIC;
1185 
    p_14_out : out STD_LOGIC;
1186 
    p_11_out : out STD_LOGIC;
1187 
    p_8_out : out STD_LOGIC;
1188 
    p_5_out : out STD_LOGIC;
1189 
    p_2_out : out STD_LOGIC;
1190 
    status_reg_reg0 : out STD_LOGIC;
1191 
    fifo_Write0 : out STD_LOGIC;
1192 
    stop_Bit_Position_reg : out STD_LOGIC;
1193 
    frame_err_ocrd_reg : out STD_LOGIC;
1194 
    running_reg : out STD_LOGIC;
1195 
    en_16x_Baud : in STD_LOGIC;
1196 
    s_axi_aclk : in STD_LOGIC;
1197 
    \in\ : in STD_LOGIC_VECTOR ( 0 to 7 );
1198 
    start_Edge_Detected : in STD_LOGIC;
1199 
    s_axi_aresetn : in STD_LOGIC;
1200 
    stop_Bit_Position_reg_0 : in STD_LOGIC;
1201 
    scndry_out : in STD_LOGIC;
1202 
    status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
1203 
    clr_Status : in STD_LOGIC;
1204 
    valid_rx : in STD_LOGIC;
1205 
    frame_err_ocrd : in STD_LOGIC;
1206 
    running_reg_0 : in STD_LOGIC
1207 
  );
1208 
end axi_uartlite_module_sim_dynshreg_i_f;
1209 
 
1210 
architecture STRUCTURE of axi_uartlite_module_sim_dynshreg_i_f is
1211 
  signal \INFERRED_GEN.data_reg[14][0]_srl15_n_0\ : STD_LOGIC;
1212 
  signal \INFERRED_GEN.data_reg[15]\ : STD_LOGIC;
1213 
  signal \^serial_to_parallel[2].fifo_din_reg[2]\ : STD_LOGIC;
1214 
  signal recycle : STD_LOGIC;
1215 
  signal \status_reg[1]_i_2_n_0\ : STD_LOGIC;
1216 
  attribute srl_bus_name : string;
1217 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14] ";
1218 
  attribute srl_name : string;
1219 
  attribute srl_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15 ";
1220 
  attribute SOFT_HLUTNM : string;
1221 
  attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[14][0]_srl15_i_1\ : label is "soft_lutpair16";
1222 
  attribute SOFT_HLUTNM of \SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2\ : label is "soft_lutpair14";
1223 
  attribute SOFT_HLUTNM of fifo_Write_i_1 : label is "soft_lutpair15";
1224 
  attribute SOFT_HLUTNM of frame_err_ocrd_i_1 : label is "soft_lutpair15";
1225 
  attribute SOFT_HLUTNM of running_i_1 : label is "soft_lutpair14";
1226 
  attribute SOFT_HLUTNM of \status_reg[1]_i_2\ : label is "soft_lutpair16";
1227 
begin
1228 
  \SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ <= \^serial_to_parallel[2].fifo_din_reg[2]\;
1229 
\INFERRED_GEN.data_reg[14][0]_srl15\: unisim.vcomponents.SRL16E
1230 
    generic map(
1231 
      INIT => X"0000"
1232 
    )
1233 
        port map (
1234 
      A0 => '0',
1235 
      A1 => '1',
1236 
      A2 => '1',
1237 
      A3 => '1',
1238 
      CE => en_16x_Baud,
1239 
      CLK => s_axi_aclk,
1240 
      D => recycle,
1241 
      Q => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\
1242 
    );
1243 
\INFERRED_GEN.data_reg[14][0]_srl15_i_1\: unisim.vcomponents.LUT4
1244 
    generic map(
1245 
      INIT => X"4440"
1246 
    )
1247 
        port map (
1248 
      I0 => stop_Bit_Position_reg_0,
1249 
      I1 => valid_rx,
1250 
      I2 => \INFERRED_GEN.data_reg[15]\,
1251 
      I3 => start_Edge_Detected,
1252 
      O => recycle
1253 
    );
1254 
\INFERRED_GEN.data_reg[15][0]\: unisim.vcomponents.FDRE
1255 
    generic map(
1256 
      INIT => '0'
1257 
    )
1258 
        port map (
1259 
      C => s_axi_aclk,
1260 
      CE => en_16x_Baud,
1261 
      D => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\,
1262 
      Q => \INFERRED_GEN.data_reg[15]\,
1263 
      R => '0'
1264 
    );
1265 
\SERIAL_TO_PARALLEL[2].fifo_din[2]_i_1\: unisim.vcomponents.LUT5
1266 
    generic map(
1267 
      INIT => X"0A000C00"
1268 
    )
1269 
        port map (
1270 
      I0 => \in\(1),
1271 
      I1 => \in\(0),
1272 
      I2 => start_Edge_Detected,
1273 
      I3 => s_axi_aresetn,
1274 
      I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
1275 
      O => p_20_out
1276 
    );
1277 
\SERIAL_TO_PARALLEL[3].fifo_din[3]_i_1\: unisim.vcomponents.LUT5
1278 
    generic map(
1279 
      INIT => X"0A000C00"
1280 
    )
1281 
        port map (
1282 
      I0 => \in\(2),
1283 
      I1 => \in\(1),
1284 
      I2 => start_Edge_Detected,
1285 
      I3 => s_axi_aresetn,
1286 
      I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
1287 
      O => p_17_out
1288 
    );
1289 
\SERIAL_TO_PARALLEL[4].fifo_din[4]_i_1\: unisim.vcomponents.LUT5
1290 
    generic map(
1291 
      INIT => X"0A000C00"
1292 
    )
1293 
        port map (
1294 
      I0 => \in\(3),
1295 
      I1 => \in\(2),
1296 
      I2 => start_Edge_Detected,
1297 
      I3 => s_axi_aresetn,
1298 
      I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
1299 
      O => p_14_out
1300 
    );
1301 
\SERIAL_TO_PARALLEL[5].fifo_din[5]_i_1\: unisim.vcomponents.LUT5
1302 
    generic map(
1303 
      INIT => X"0A000C00"
1304 
    )
1305 
        port map (
1306 
      I0 => \in\(4),
1307 
      I1 => \in\(3),
1308 
      I2 => start_Edge_Detected,
1309 
      I3 => s_axi_aresetn,
1310 
      I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
1311 
      O => p_11_out
1312 
    );
1313 
\SERIAL_TO_PARALLEL[6].fifo_din[6]_i_1\: unisim.vcomponents.LUT5
1314 
    generic map(
1315 
      INIT => X"0A000C00"
1316 
    )
1317 
        port map (
1318 
      I0 => \in\(5),
1319 
      I1 => \in\(4),
1320 
      I2 => start_Edge_Detected,
1321 
      I3 => s_axi_aresetn,
1322 
      I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
1323 
      O => p_8_out
1324 
    );
1325 
\SERIAL_TO_PARALLEL[7].fifo_din[7]_i_1\: unisim.vcomponents.LUT5
1326 
    generic map(
1327 
      INIT => X"0A000C00"
1328 
    )
1329 
        port map (
1330 
      I0 => \in\(6),
1331 
      I1 => \in\(5),
1332 
      I2 => start_Edge_Detected,
1333 
      I3 => s_axi_aresetn,
1334 
      I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
1335 
      O => p_5_out
1336 
    );
1337 
\SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1\: unisim.vcomponents.LUT5
1338 
    generic map(
1339 
      INIT => X"0A000C00"
1340 
    )
1341 
        port map (
1342 
      I0 => \in\(7),
1343 
      I1 => \in\(6),
1344 
      I2 => start_Edge_Detected,
1345 
      I3 => s_axi_aresetn,
1346 
      I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
1347 
      O => p_2_out
1348 
    );
1349 
\SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2\: unisim.vcomponents.LUT3
1350 
    generic map(
1351 
      INIT => X"F7"
1352 
    )
1353 
        port map (
1354 
      I0 => en_16x_Baud,
1355 
      I1 => \INFERRED_GEN.data_reg[15]\,
1356 
      I2 => stop_Bit_Position_reg_0,
1357 
      O => \^serial_to_parallel[2].fifo_din_reg[2]\
1358 
    );
1359 
fifo_Write_i_1: unisim.vcomponents.LUT4
1360 
    generic map(
1361 
      INIT => X"8000"
1362 
    )
1363 
        port map (
1364 
      I0 => \INFERRED_GEN.data_reg[15]\,
1365 
      I1 => en_16x_Baud,
1366 
      I2 => stop_Bit_Position_reg_0,
1367 
      I3 => scndry_out,
1368 
      O => fifo_Write0
1369 
    );
1370 
frame_err_ocrd_i_1: unisim.vcomponents.LUT5
1371 
    generic map(
1372 
      INIT => X"00FF0080"
1373 
    )
1374 
        port map (
1375 
      I0 => \INFERRED_GEN.data_reg[15]\,
1376 
      I1 => en_16x_Baud,
1377 
      I2 => stop_Bit_Position_reg_0,
1378 
      I3 => scndry_out,
1379 
      I4 => frame_err_ocrd,
1380 
      O => frame_err_ocrd_reg
1381 
    );
1382 
running_i_1: unisim.vcomponents.LUT5
1383 
    generic map(
1384 
      INIT => X"BFFFA0A0"
1385 
    )
1386 
        port map (
1387 
      I0 => start_Edge_Detected,
1388 
      I1 => \INFERRED_GEN.data_reg[15]\,
1389 
      I2 => en_16x_Baud,
1390 
      I3 => stop_Bit_Position_reg_0,
1391 
      I4 => running_reg_0,
1392 
      O => running_reg
1393 
    );
1394 
\status_reg[1]_i_1\: unisim.vcomponents.LUT5
1395 
    generic map(
1396 
      INIT => X"0000F200"
1397 
    )
1398 
        port map (
1399 
      I0 => \status_reg[1]_i_2_n_0\,
1400 
      I1 => scndry_out,
1401 
      I2 => status_reg(0),
1402 
      I3 => s_axi_aresetn,
1403 
      I4 => clr_Status,
1404 
      O => status_reg_reg0
1405 
    );
1406 
\status_reg[1]_i_2\: unisim.vcomponents.LUT3
1407 
    generic map(
1408 
      INIT => X"80"
1409 
    )
1410 
        port map (
1411 
      I0 => stop_Bit_Position_reg_0,
1412 
      I1 => en_16x_Baud,
1413 
      I2 => \INFERRED_GEN.data_reg[15]\,
1414 
      O => \status_reg[1]_i_2_n_0\
1415 
    );
1416 
stop_Bit_Position_i_1: unisim.vcomponents.LUT4
1417 
    generic map(
1418 
      INIT => X"2CCC"
1419 
    )
1420 
        port map (
1421 
      I0 => \in\(7),
1422 
      I1 => stop_Bit_Position_reg_0,
1423 
      I2 => en_16x_Baud,
1424 
      I3 => \INFERRED_GEN.data_reg[15]\,
1425 
      O => stop_Bit_Position_reg
1426 
    );
1427 
end STRUCTURE;
1428 
library IEEE;
1429 
use IEEE.STD_LOGIC_1164.ALL;
1430 
library UNISIM;
1431 
use UNISIM.VCOMPONENTS.ALL;
1432 
entity \axi_uartlite_module_sim_dynshreg_i_f__parameterized0\ is
1433 
  port (
1434 
    tx_Data_Enable_reg : out STD_LOGIC;
1435 
    en_16x_Baud : in STD_LOGIC;
1436 
    s_axi_aclk : in STD_LOGIC;
1437 
    tx_Data_Enable_reg_0 : in STD_LOGIC
1438 
  );
1439 
  attribute ORIG_REF_NAME : string;
1440 
  attribute ORIG_REF_NAME of \axi_uartlite_module_sim_dynshreg_i_f__parameterized0\ : entity is "dynshreg_i_f";
1441 
end \axi_uartlite_module_sim_dynshreg_i_f__parameterized0\;
1442 
 
1443 
architecture STRUCTURE of \axi_uartlite_module_sim_dynshreg_i_f__parameterized0\ is
1444 
  signal \INFERRED_GEN.data_reg[14][0]_srl15_n_0\ : STD_LOGIC;
1445 
  signal \INFERRED_GEN.data_reg_n_0_[15][0]\ : STD_LOGIC;
1446 
  attribute srl_bus_name : string;
1447 
  attribute srl_bus_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14] ";
1448 
  attribute srl_name : string;
1449 
  attribute srl_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15 ";
1450 
begin
1451 
\INFERRED_GEN.data_reg[14][0]_srl15\: unisim.vcomponents.SRL16E
1452 
    generic map(
1453 
      INIT => X"0001"
1454 
    )
1455 
        port map (
1456 
      A0 => '0',
1457 
      A1 => '1',
1458 
      A2 => '1',
1459 
      A3 => '1',
1460 
      CE => en_16x_Baud,
1461 
      CLK => s_axi_aclk,
1462 
      D => \INFERRED_GEN.data_reg_n_0_[15][0]\,
1463 
      Q => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\
1464 
    );
1465 
\INFERRED_GEN.data_reg[15][0]\: unisim.vcomponents.FDRE
1466 
    generic map(
1467 
      INIT => '0'
1468 
    )
1469 
        port map (
1470 
      C => s_axi_aclk,
1471 
      CE => en_16x_Baud,
1472 
      D => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\,
1473 
      Q => \INFERRED_GEN.data_reg_n_0_[15][0]\,
1474 
      R => '0'
1475 
    );
1476 
tx_Data_Enable_i_1: unisim.vcomponents.LUT3
1477 
    generic map(
1478 
      INIT => X"20"
1479 
    )
1480 
        port map (
1481 
      I0 => \INFERRED_GEN.data_reg_n_0_[15][0]\,
1482 
      I1 => tx_Data_Enable_reg_0,
1483 
      I2 => en_16x_Baud,
1484 
      O => tx_Data_Enable_reg
1485 
    );
1486 
end STRUCTURE;
1487 
library IEEE;
1488 
use IEEE.STD_LOGIC_1164.ALL;
1489 
library UNISIM;
1490 
use UNISIM.VCOMPONENTS.ALL;
1491 
entity axi_uartlite_module_sim_pselect_f is
1492 
  port (
1493 
    ce_expnd_i_3 : out STD_LOGIC;
1494 
    \bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
1495 
    \bus2ip_addr_i_reg[3]\ : in STD_LOGIC
1496 
  );
1497 
end axi_uartlite_module_sim_pselect_f;
1498 
 
1499 
architecture STRUCTURE of axi_uartlite_module_sim_pselect_f is
1500 
begin
1501 
CS: unisim.vcomponents.LUT2
1502 
    generic map(
1503 
      INIT => X"1"
1504 
    )
1505 
        port map (
1506 
      I0 => \bus2ip_addr_i_reg[2]\,
1507 
      I1 => \bus2ip_addr_i_reg[3]\,
1508 
      O => ce_expnd_i_3
1509 
    );
1510 
end STRUCTURE;
1511 
library IEEE;
1512 
use IEEE.STD_LOGIC_1164.ALL;
1513 
library UNISIM;
1514 
use UNISIM.VCOMPONENTS.ALL;
1515 
entity \axi_uartlite_module_sim_pselect_f__parameterized1\ is
1516 
  port (
1517 
    ce_expnd_i_1 : out STD_LOGIC;
1518 
    \bus2ip_addr_i_reg[3]\ : in STD_LOGIC;
1519 
    \bus2ip_addr_i_reg[2]\ : in STD_LOGIC
1520 
  );
1521 
  attribute ORIG_REF_NAME : string;
1522 
  attribute ORIG_REF_NAME of \axi_uartlite_module_sim_pselect_f__parameterized1\ : entity is "pselect_f";
1523 
end \axi_uartlite_module_sim_pselect_f__parameterized1\;
1524 
 
1525 
architecture STRUCTURE of \axi_uartlite_module_sim_pselect_f__parameterized1\ is
1526 
begin
1527 
CS: unisim.vcomponents.LUT2
1528 
    generic map(
1529 
      INIT => X"2"
1530 
    )
1531 
        port map (
1532 
      I0 => \bus2ip_addr_i_reg[3]\,
1533 
      I1 => \bus2ip_addr_i_reg[2]\,
1534 
      O => ce_expnd_i_1
1535 
    );
1536 
end STRUCTURE;
1537 
library IEEE;
1538 
use IEEE.STD_LOGIC_1164.ALL;
1539 
library UNISIM;
1540 
use UNISIM.VCOMPONENTS.ALL;
1541 
entity axi_uartlite_module_sim_address_decoder is
1542 
  port (
1543 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : out STD_LOGIC;
1544 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1\ : out STD_LOGIC;
1545 
    enable_interrupts_reg : out STD_LOGIC;
1546 
    reset_TX_FIFO : out STD_LOGIC;
1547 
    reset_RX_FIFO : out STD_LOGIC;
1548 
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
1549 
    s_axi_awready : out STD_LOGIC;
1550 
    s_axi_arready : out STD_LOGIC;
1551 
    \s_axi_rdata_i_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
1552 
    ip2bus_error : out STD_LOGIC;
1553 
    \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
1554 
    rx_Data_Present_Pre_reg : out STD_LOGIC;
1555 
    FIFO_Full_reg : out STD_LOGIC;
1556 
    bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
1557 
    fifo_wr : out STD_LOGIC;
1558 
    \INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
1559 
    tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
1560 
    enable_interrupts_reg_0 : out STD_LOGIC;
1561 
    s_axi_rvalid_i_reg : out STD_LOGIC;
1562 
    s_axi_bvalid_i_reg : out STD_LOGIC;
1563 
    \s_axi_bresp_i_reg[1]\ : out STD_LOGIC;
1564 
    start2 : in STD_LOGIC;
1565 
    s_axi_aclk : in STD_LOGIC;
1566 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
1567 
    \state_reg[0]\ : in STD_LOGIC;
1568 
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
1569 
    s_axi_arvalid : in STD_LOGIC;
1570 
    \state_reg[1]\ : in STD_LOGIC;
1571 
    s_axi_wvalid : in STD_LOGIC;
1572 
    s_axi_aresetn : in STD_LOGIC;
1573 
    \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
1574 
    \out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
1575 
    rx_Buffer_Full : in STD_LOGIC;
1576 
    \INFERRED_GEN.cnt_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
1577 
    tx_Buffer_Full : in STD_LOGIC;
1578 
    enable_interrupts : in STD_LOGIC;
1579 
    status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
1580 
    s_axi_rready : in STD_LOGIC;
1581 
    s_axi_rvalid_i_reg_0 : in STD_LOGIC;
1582 
    s_axi_bready : in STD_LOGIC;
1583 
    s_axi_bvalid_i_reg_0 : in STD_LOGIC;
1584 
    s_axi_bresp : in STD_LOGIC_VECTOR ( 0 to 0 );
1585 
    bus2ip_rnw_i : in STD_LOGIC;
1586 
    \bus2ip_addr_i_reg[3]\ : in STD_LOGIC;
1587 
    \bus2ip_addr_i_reg[2]\ : in STD_LOGIC
1588 
  );
1589 
end axi_uartlite_module_sim_address_decoder;
1590 
 
1591 
architecture STRUCTURE of axi_uartlite_module_sim_address_decoder is
1592 
  signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
1593 
  signal \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\ : STD_LOGIC;
1594 
  signal \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\ : STD_LOGIC;
1595 
  signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
1596 
  signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
1597 
  signal ce_expnd_i_0 : STD_LOGIC;
1598 
  signal ce_expnd_i_1 : STD_LOGIC;
1599 
  signal ce_expnd_i_2 : STD_LOGIC;
1600 
  signal ce_expnd_i_3 : STD_LOGIC;
1601 
  signal cs_ce_clr : STD_LOGIC;
1602 
  signal \^enable_interrupts_reg\ : STD_LOGIC;
1603 
  signal \^ip2bus_error\ : STD_LOGIC;
1604 
  signal \^s_axi_arready\ : STD_LOGIC;
1605 
  signal \^s_axi_awready\ : STD_LOGIC;
1606 
  attribute SOFT_HLUTNM : string;
1607 
  attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair7";
1608 
  attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair8";
1609 
  attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair8";
1610 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[3]_i_2\ : label is "soft_lutpair0";
1611 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_3\ : label is "soft_lutpair1";
1612 
  attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_5\ : label is "soft_lutpair6";
1613 
  attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[15][7]_srl16_i_1\ : label is "soft_lutpair4";
1614 
  attribute SOFT_HLUTNM of clr_Status_i_1 : label is "soft_lutpair2";
1615 
  attribute SOFT_HLUTNM of enable_interrupts_i_1 : label is "soft_lutpair5";
1616 
  attribute SOFT_HLUTNM of reset_RX_FIFO_i_1 : label is "soft_lutpair7";
1617 
  attribute SOFT_HLUTNM of reset_TX_FIFO_i_1 : label is "soft_lutpair5";
1618 
  attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair3";
1619 
  attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_1\ : label is "soft_lutpair0";
1620 
  attribute SOFT_HLUTNM of \s_axi_rdata_i[1]_i_1\ : label is "soft_lutpair1";
1621 
  attribute SOFT_HLUTNM of \s_axi_rdata_i[2]_i_1\ : label is "soft_lutpair2";
1622 
  attribute SOFT_HLUTNM of \s_axi_rresp_i[1]_i_1\ : label is "soft_lutpair4";
1623 
  attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair3";
1624 
  attribute SOFT_HLUTNM of tx_Buffer_Empty_Pre_i_1 : label is "soft_lutpair6";
1625 
begin
1626 
  \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ <= \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\;
1627 
  \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1\ <= \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\;
1628 
  enable_interrupts_reg <= \^enable_interrupts_reg\;
1629 
  ip2bus_error <= \^ip2bus_error\;
1630 
  s_axi_arready <= \^s_axi_arready\;
1631 
  s_axi_awready <= \^s_axi_awready\;
1632 
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
1633 
    generic map(
1634 
      INIT => X"B8"
1635 
    )
1636 
        port map (
1637 
      I0 => bus2ip_rnw_i,
1638 
      I1 => start2,
1639 
      I2 => \^enable_interrupts_reg\,
1640 
      O => Bus_RNW_reg_i_1_n_0
1641 
    );
1642 
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
1643 
     port map (
1644 
      C => s_axi_aclk,
1645 
      CE => '1',
1646 
      D => Bus_RNW_reg_i_1_n_0,
1647 
      Q => \^enable_interrupts_reg\,
1648 
      R => '0'
1649 
    );
1650 
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
1651 
     port map (
1652 
      C => s_axi_aclk,
1653 
      CE => start2,
1654 
      D => ce_expnd_i_3,
1655 
      Q => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1656 
      R => cs_ce_clr
1657 
    );
1658 
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2
1659 
    generic map(
1660 
      INIT => X"2"
1661 
    )
1662 
        port map (
1663 
      I0 => \bus2ip_addr_i_reg[2]\,
1664 
      I1 => \bus2ip_addr_i_reg[3]\,
1665 
      O => ce_expnd_i_2
1666 
    );
1667 
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
1668 
     port map (
1669 
      C => s_axi_aclk,
1670 
      CE => start2,
1671 
      D => ce_expnd_i_2,
1672 
      Q => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
1673 
      R => cs_ce_clr
1674 
    );
1675 
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
1676 
     port map (
1677 
      C => s_axi_aclk,
1678 
      CE => start2,
1679 
      D => ce_expnd_i_1,
1680 
      Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1681 
      R => cs_ce_clr
1682 
    );
1683 
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT5
1684 
    generic map(
1685 
      INIT => X"FFFEFFFF"
1686 
    )
1687 
        port map (
1688 
      I0 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
1689 
      I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
1690 
      I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1691 
      I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1692 
      I4 => s_axi_aresetn,
1693 
      O => cs_ce_clr
1694 
    );
1695 
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2
1696 
    generic map(
1697 
      INIT => X"8"
1698 
    )
1699 
        port map (
1700 
      I0 => \bus2ip_addr_i_reg[3]\,
1701 
      I1 => \bus2ip_addr_i_reg[2]\,
1702 
      O => ce_expnd_i_0
1703 
    );
1704 
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
1705 
     port map (
1706 
      C => s_axi_aclk,
1707 
      CE => start2,
1708 
      D => ce_expnd_i_0,
1709 
      Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
1710 
      R => cs_ce_clr
1711 
    );
1712 
\INFERRED_GEN.cnt_i[3]_i_2\: unisim.vcomponents.LUT3
1713 
    generic map(
1714 
      INIT => X"F7"
1715 
    )
1716 
        port map (
1717 
      I0 => \^enable_interrupts_reg\,
1718 
      I1 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1719 
      I2 => \INFERRED_GEN.cnt_i_reg[4]\(0),
1720 
      O => \INFERRED_GEN.cnt_i_reg[2]\
1721 
    );
1722 
\INFERRED_GEN.cnt_i[4]_i_3\: unisim.vcomponents.LUT2
1723 
    generic map(
1724 
      INIT => X"7"
1725 
    )
1726 
        port map (
1727 
      I0 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1728 
      I1 => \^enable_interrupts_reg\,
1729 
      O => FIFO_Full_reg
1730 
    );
1731 
\INFERRED_GEN.cnt_i[4]_i_5\: unisim.vcomponents.LUT3
1732 
    generic map(
1733 
      INIT => X"FD"
1734 
    )
1735 
        port map (
1736 
      I0 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
1737 
      I1 => \^enable_interrupts_reg\,
1738 
      I2 => tx_Buffer_Full,
1739 
      O => \INFERRED_GEN.cnt_i_reg[2]_0\
1740 
    );
1741 
\INFERRED_GEN.data_reg[15][7]_srl16_i_1\: unisim.vcomponents.LUT3
1742 
    generic map(
1743 
      INIT => X"10"
1744 
    )
1745 
        port map (
1746 
      I0 => tx_Buffer_Full,
1747 
      I1 => \^enable_interrupts_reg\,
1748 
      I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
1749 
      O => fifo_wr
1750 
    );
1751 
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.axi_uartlite_module_sim_pselect_f
1752 
     port map (
1753 
      \bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg[2]\,
1754 
      \bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg[3]\,
1755 
      ce_expnd_i_3 => ce_expnd_i_3
1756 
    );
1757 
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\axi_uartlite_module_sim_pselect_f__parameterized1\
1758 
     port map (
1759 
      \bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg[2]\,
1760 
      \bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg[3]\,
1761 
      ce_expnd_i_1 => ce_expnd_i_1
1762 
    );
1763 
clr_Status_i_1: unisim.vcomponents.LUT2
1764 
    generic map(
1765 
      INIT => X"8"
1766 
    )
1767 
        port map (
1768 
      I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1769 
      I1 => \^enable_interrupts_reg\,
1770 
      O => bus2ip_rdce(0)
1771 
    );
1772 
enable_interrupts_i_1: unisim.vcomponents.LUT4
1773 
    generic map(
1774 
      INIT => X"FB08"
1775 
    )
1776 
        port map (
1777 
      I0 => s_axi_wdata(2),
1778 
      I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
1779 
      I2 => \^enable_interrupts_reg\,
1780 
      I3 => enable_interrupts,
1781 
      O => enable_interrupts_reg_0
1782 
    );
1783 
reset_RX_FIFO_i_1: unisim.vcomponents.LUT3
1784 
    generic map(
1785 
      INIT => X"40"
1786 
    )
1787 
        port map (
1788 
      I0 => \^enable_interrupts_reg\,
1789 
      I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
1790 
      I2 => s_axi_wdata(1),
1791 
      O => reset_RX_FIFO
1792 
    );
1793 
reset_TX_FIFO_i_1: unisim.vcomponents.LUT3
1794 
    generic map(
1795 
      INIT => X"40"
1796 
    )
1797 
        port map (
1798 
      I0 => \^enable_interrupts_reg\,
1799 
      I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
1800 
      I2 => s_axi_wdata(0),
1801 
      O => reset_TX_FIFO
1802 
    );
1803 
rx_Data_Present_Pre_i_1: unisim.vcomponents.LUT4
1804 
    generic map(
1805 
      INIT => X"0444"
1806 
    )
1807 
        port map (
1808 
      I0 => \INFERRED_GEN.cnt_i_reg[4]\(0),
1809 
      I1 => s_axi_aresetn,
1810 
      I2 => \^enable_interrupts_reg\,
1811 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1812 
      O => rx_Data_Present_Pre_reg
1813 
    );
1814 
s_axi_arready_INST_0: unisim.vcomponents.LUT5
1815 
    generic map(
1816 
      INIT => X"F0F0F0E0"
1817 
    )
1818 
        port map (
1819 
      I0 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1820 
      I1 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1821 
      I2 => \^enable_interrupts_reg\,
1822 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
1823 
      I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
1824 
      O => \^s_axi_arready\
1825 
    );
1826 
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
1827 
    generic map(
1828 
      INIT => X"FB08"
1829 
    )
1830 
        port map (
1831 
      I0 => \^ip2bus_error\,
1832 
      I1 => Q(1),
1833 
      I2 => Q(0),
1834 
      I3 => s_axi_bresp(0),
1835 
      O => \s_axi_bresp_i_reg[1]\
1836 
    );
1837 
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
1838 
    generic map(
1839 
      INIT => X"40FF4040"
1840 
    )
1841 
        port map (
1842 
      I0 => Q(0),
1843 
      I1 => Q(1),
1844 
      I2 => \^s_axi_awready\,
1845 
      I3 => s_axi_bready,
1846 
      I4 => s_axi_bvalid_i_reg_0,
1847 
      O => s_axi_bvalid_i_reg
1848 
    );
1849 
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT5
1850 
    generic map(
1851 
      INIT => X"5050C000"
1852 
    )
1853 
        port map (
1854 
      I0 => \INFERRED_GEN.cnt_i_reg[4]\(0),
1855 
      I1 => \out\(0),
1856 
      I2 => \^enable_interrupts_reg\,
1857 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1858 
      I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1859 
      O => \s_axi_rdata_i_reg[7]\(0)
1860 
    );
1861 
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
1862 
    generic map(
1863 
      INIT => X"A0A0C000"
1864 
    )
1865 
        port map (
1866 
      I0 => rx_Buffer_Full,
1867 
      I1 => \out\(1),
1868 
      I2 => \^enable_interrupts_reg\,
1869 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1870 
      I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1871 
      O => \s_axi_rdata_i_reg[7]\(1)
1872 
    );
1873 
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT5
1874 
    generic map(
1875 
      INIT => X"A0A0C000"
1876 
    )
1877 
        port map (
1878 
      I0 => \INFERRED_GEN.cnt_i_reg[4]_0\(0),
1879 
      I1 => \out\(2),
1880 
      I2 => \^enable_interrupts_reg\,
1881 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1882 
      I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1883 
      O => \s_axi_rdata_i_reg[7]\(2)
1884 
    );
1885 
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT5
1886 
    generic map(
1887 
      INIT => X"A0A0C000"
1888 
    )
1889 
        port map (
1890 
      I0 => tx_Buffer_Full,
1891 
      I1 => \out\(3),
1892 
      I2 => \^enable_interrupts_reg\,
1893 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1894 
      I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1895 
      O => \s_axi_rdata_i_reg[7]\(3)
1896 
    );
1897 
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT5
1898 
    generic map(
1899 
      INIT => X"A0A0C000"
1900 
    )
1901 
        port map (
1902 
      I0 => enable_interrupts,
1903 
      I1 => \out\(4),
1904 
      I2 => \^enable_interrupts_reg\,
1905 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1906 
      I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1907 
      O => \s_axi_rdata_i_reg[7]\(4)
1908 
    );
1909 
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT5
1910 
    generic map(
1911 
      INIT => X"A0A0C000"
1912 
    )
1913 
        port map (
1914 
      I0 => status_reg(0),
1915 
      I1 => \out\(5),
1916 
      I2 => \^enable_interrupts_reg\,
1917 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1918 
      I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1919 
      O => \s_axi_rdata_i_reg[7]\(5)
1920 
    );
1921 
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT5
1922 
    generic map(
1923 
      INIT => X"A0A0C000"
1924 
    )
1925 
        port map (
1926 
      I0 => status_reg(1),
1927 
      I1 => \out\(6),
1928 
      I2 => \^enable_interrupts_reg\,
1929 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1930 
      I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1931 
      O => \s_axi_rdata_i_reg[7]\(6)
1932 
    );
1933 
\s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT4
1934 
    generic map(
1935 
      INIT => X"4000"
1936 
    )
1937 
        port map (
1938 
      I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1939 
      I1 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1940 
      I2 => \^enable_interrupts_reg\,
1941 
      I3 => \out\(7),
1942 
      O => \s_axi_rdata_i_reg[7]\(7)
1943 
    );
1944 
\s_axi_rresp_i[1]_i_1\: unisim.vcomponents.LUT5
1945 
    generic map(
1946 
      INIT => X"F0880088"
1947 
    )
1948 
        port map (
1949 
      I0 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
1950 
      I1 => tx_Buffer_Full,
1951 
      I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1952 
      I3 => \^enable_interrupts_reg\,
1953 
      I4 => \INFERRED_GEN.cnt_i_reg[4]\(0),
1954 
      O => \^ip2bus_error\
1955 
    );
1956 
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
1957 
    generic map(
1958 
      INIT => X"40FF4040"
1959 
    )
1960 
        port map (
1961 
      I0 => Q(1),
1962 
      I1 => Q(0),
1963 
      I2 => \^s_axi_arready\,
1964 
      I3 => s_axi_rready,
1965 
      I4 => s_axi_rvalid_i_reg_0,
1966 
      O => s_axi_rvalid_i_reg
1967 
    );
1968 
s_axi_wready_INST_0: unisim.vcomponents.LUT5
1969 
    generic map(
1970 
      INIT => X"0F0F0F0E"
1971 
    )
1972 
        port map (
1973 
      I0 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
1974 
      I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
1975 
      I2 => \^enable_interrupts_reg\,
1976 
      I3 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_1\,
1977 
      I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
1978 
      O => \^s_axi_awready\
1979 
    );
1980 
\state[0]_i_1\: unisim.vcomponents.LUT5
1981 
    generic map(
1982 
      INIT => X"CFEFCFEC"
1983 
    )
1984 
        port map (
1985 
      I0 => \^s_axi_awready\,
1986 
      I1 => \state_reg[0]\,
1987 
      I2 => Q(1),
1988 
      I3 => Q(0),
1989 
      I4 => s_axi_arvalid,
1990 
      O => D(0)
1991 
    );
1992 
\state[1]_i_1\: unisim.vcomponents.LUT6
1993 
    generic map(
1994 
      INIT => X"CFECCFECCFEFCFEC"
1995 
    )
1996 
        port map (
1997 
      I0 => \^s_axi_arready\,
1998 
      I1 => \state_reg[1]\,
1999 
      I2 => Q(0),
2000 
      I3 => Q(1),
2001 
      I4 => s_axi_wvalid,
2002 
      I5 => s_axi_arvalid,
2003 
      O => D(1)
2004 
    );
2005 
tx_Buffer_Empty_Pre_i_1: unisim.vcomponents.LUT4
2006 
    generic map(
2007 
      INIT => X"8808"
2008 
    )
2009 
        port map (
2010 
      I0 => s_axi_aresetn,
2011 
      I1 => \INFERRED_GEN.cnt_i_reg[4]_0\(0),
2012 
      I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
2013 
      I3 => \^enable_interrupts_reg\,
2014 
      O => tx_Buffer_Empty_Pre_reg
2015 
    );
2016 
end STRUCTURE;
2017 
library IEEE;
2018 
use IEEE.STD_LOGIC_1164.ALL;
2019 
library UNISIM;
2020 
use UNISIM.VCOMPONENTS.ALL;
2021 
entity axi_uartlite_module_sim_srl_fifo_rbu_f is
2022 
  port (
2023 
    tx_Buffer_Full : out STD_LOGIC;
2024 
    mux_Out : out STD_LOGIC;
2025 
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
2026 
    tx_Start0 : out STD_LOGIC;
2027 
    s_axi_aclk : in STD_LOGIC;
2028 
    p_4_in : in STD_LOGIC;
2029 
    \mux_sel_reg[2]\ : in STD_LOGIC;
2030 
    \mux_sel_reg[0]\ : in STD_LOGIC;
2031 
    reset_TX_FIFO_reg : in STD_LOGIC;
2032 
    s_axi_aresetn : in STD_LOGIC;
2033 
    fifo_Read : in STD_LOGIC;
2034 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
2035 
    Bus_RNW_reg : in STD_LOGIC;
2036 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
2037 
    tx_Data_Enable_reg : in STD_LOGIC;
2038 
    tx_DataBits : in STD_LOGIC;
2039 
    tx_Start : in STD_LOGIC;
2040 
    fifo_wr : in STD_LOGIC;
2041 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
2042 
  );
2043 
end axi_uartlite_module_sim_srl_fifo_rbu_f;
2044 
 
2045 
architecture STRUCTURE of axi_uartlite_module_sim_srl_fifo_rbu_f is
2046 
  signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC;
2047 
  signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC;
2048 
  signal CNTR_INCR_DECR_ADDN_F_I_n_4 : STD_LOGIC;
2049 
  signal CNTR_INCR_DECR_ADDN_F_I_n_5 : STD_LOGIC;
2050 
  signal TX_FIFO_Reset : STD_LOGIC;
2051 
  signal fifo_full_p1 : STD_LOGIC;
2052 
  signal \^tx_buffer_full\ : STD_LOGIC;
2053 
begin
2054 
  tx_Buffer_Full <= \^tx_buffer_full\;
2055 
CNTR_INCR_DECR_ADDN_F_I: entity work.axi_uartlite_module_sim_cntr_incr_decr_addn_f
2056 
     port map (
2057 
      Bus_RNW_reg => Bus_RNW_reg,
2058 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
2059 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
2060 
      Q(4) => Q(0),
2061 
      Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_2,
2062 
      Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_3,
2063 
      Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_4,
2064 
      Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_5,
2065 
      SS(0) => TX_FIFO_Reset,
2066 
      fifo_Read => fifo_Read,
2067 
      fifo_full_p1 => fifo_full_p1,
2068 
      reset_TX_FIFO_reg => reset_TX_FIFO_reg,
2069 
      s_axi_aclk => s_axi_aclk,
2070 
      s_axi_aresetn => s_axi_aresetn,
2071 
      tx_Buffer_Full => \^tx_buffer_full\,
2072 
      tx_DataBits => tx_DataBits,
2073 
      tx_Data_Enable_reg => tx_Data_Enable_reg,
2074 
      tx_Start => tx_Start,
2075 
      tx_Start0 => tx_Start0
2076 
    );
2077 
DYNSHREG_F_I: entity work.axi_uartlite_module_sim_dynshreg_f
2078 
     port map (
2079 
      Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_2,
2080 
      Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_3,
2081 
      Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_4,
2082 
      Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_5,
2083 
      fifo_wr => fifo_wr,
2084 
      mux_Out => mux_Out,
2085 
      \mux_sel_reg[0]\ => \mux_sel_reg[0]\,
2086 
      \mux_sel_reg[2]\ => \mux_sel_reg[2]\,
2087 
      p_4_in => p_4_in,
2088 
      s_axi_aclk => s_axi_aclk,
2089 
      s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
2090 
    );
2091 
FIFO_Full_reg: unisim.vcomponents.FDRE
2092 
     port map (
2093 
      C => s_axi_aclk,
2094 
      CE => '1',
2095 
      D => fifo_full_p1,
2096 
      Q => \^tx_buffer_full\,
2097 
      R => TX_FIFO_Reset
2098 
    );
2099 
end STRUCTURE;
2100 
library IEEE;
2101 
use IEEE.STD_LOGIC_1164.ALL;
2102 
library UNISIM;
2103 
use UNISIM.VCOMPONENTS.ALL;
2104 
entity axi_uartlite_module_sim_srl_fifo_rbu_f_1 is
2105 
  port (
2106 
    \status_reg_reg[2]\ : out STD_LOGIC;
2107 
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
2108 
    \status_reg_reg[2]_0\ : out STD_LOGIC;
2109 
    Interrupt0 : out STD_LOGIC;
2110 
    \out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
2111 
    s_axi_aclk : in STD_LOGIC;
2112 
    reset_RX_FIFO_reg : in STD_LOGIC;
2113 
    s_axi_aresetn : in STD_LOGIC;
2114 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
2115 
    Bus_RNW_reg : in STD_LOGIC;
2116 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
2117 
    Bus_RNW_reg_reg : in STD_LOGIC;
2118 
    status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
2119 
    fifo_Write : in STD_LOGIC;
2120 
    clr_Status : in STD_LOGIC;
2121 
    valid_rx : in STD_LOGIC;
2122 
    rx_Data_Present_Pre : in STD_LOGIC;
2123 
    enable_interrupts : in STD_LOGIC;
2124 
    \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
2125 
    tx_Buffer_Empty_Pre : in STD_LOGIC;
2126 
    \in\ : in STD_LOGIC_VECTOR ( 0 to 7 )
2127 
  );
2128 
  attribute ORIG_REF_NAME : string;
2129 
  attribute ORIG_REF_NAME of axi_uartlite_module_sim_srl_fifo_rbu_f_1 : entity is "srl_fifo_rbu_f";
2130 
end axi_uartlite_module_sim_srl_fifo_rbu_f_1;
2131 
 
2132 
architecture STRUCTURE of axi_uartlite_module_sim_srl_fifo_rbu_f_1 is
2133 
  signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC;
2134 
  signal CNTR_INCR_DECR_ADDN_F_I_n_4 : STD_LOGIC;
2135 
  signal CNTR_INCR_DECR_ADDN_F_I_n_5 : STD_LOGIC;
2136 
  signal CNTR_INCR_DECR_ADDN_F_I_n_6 : STD_LOGIC;
2137 
  signal RX_FIFO_Reset : STD_LOGIC;
2138 
  signal fifo_full_p1 : STD_LOGIC;
2139 
  signal \^status_reg_reg[2]\ : STD_LOGIC;
2140 
begin
2141 
  \status_reg_reg[2]\ <= \^status_reg_reg[2]\;
2142 
CNTR_INCR_DECR_ADDN_F_I: entity work.axi_uartlite_module_sim_cntr_incr_decr_addn_f_2
2143 
     port map (
2144 
      Bus_RNW_reg => Bus_RNW_reg,
2145 
      Bus_RNW_reg_reg => Bus_RNW_reg_reg,
2146 
      FIFO_Full_reg => \^status_reg_reg[2]\,
2147 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
2148 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
2149 
      \INFERRED_GEN.cnt_i_reg[4]_0\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
2150 
      Interrupt0 => Interrupt0,
2151 
      Q(4) => Q(0),
2152 
      Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_3,
2153 
      Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_4,
2154 
      Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_5,
2155 
      Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_6,
2156 
      SS(0) => RX_FIFO_Reset,
2157 
      enable_interrupts => enable_interrupts,
2158 
      fifo_Write => fifo_Write,
2159 
      fifo_full_p1 => fifo_full_p1,
2160 
      reset_RX_FIFO_reg => reset_RX_FIFO_reg,
2161 
      rx_Data_Present_Pre => rx_Data_Present_Pre,
2162 
      s_axi_aclk => s_axi_aclk,
2163 
      s_axi_aresetn => s_axi_aresetn,
2164 
      tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
2165 
      valid_rx => valid_rx
2166 
    );
2167 
DYNSHREG_F_I: entity work.axi_uartlite_module_sim_dynshreg_f_3
2168 
     port map (
2169 
      FIFO_Full_reg => \^status_reg_reg[2]\,
2170 
      Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_3,
2171 
      Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_4,
2172 
      Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_5,
2173 
      Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_6,
2174 
      fifo_Write => fifo_Write,
2175 
      \in\(0 to 7) => \in\(0 to 7),
2176 
      \out\(7 downto 0) => \out\(7 downto 0),
2177 
      s_axi_aclk => s_axi_aclk,
2178 
      valid_rx => valid_rx
2179 
    );
2180 
FIFO_Full_reg: unisim.vcomponents.FDRE
2181 
     port map (
2182 
      C => s_axi_aclk,
2183 
      CE => '1',
2184 
      D => fifo_full_p1,
2185 
      Q => \^status_reg_reg[2]\,
2186 
      R => RX_FIFO_Reset
2187 
    );
2188 
\status_reg[2]_i_1\: unisim.vcomponents.LUT5
2189 
    generic map(
2190 
      INIT => X"00EA0000"
2191 
    )
2192 
        port map (
2193 
      I0 => status_reg(0),
2194 
      I1 => fifo_Write,
2195 
      I2 => \^status_reg_reg[2]\,
2196 
      I3 => clr_Status,
2197 
      I4 => s_axi_aresetn,
2198 
      O => \status_reg_reg[2]_0\
2199 
    );
2200 
end STRUCTURE;
2201 
library IEEE;
2202 
use IEEE.STD_LOGIC_1164.ALL;
2203 
library UNISIM;
2204 
use UNISIM.VCOMPONENTS.ALL;
2205 
entity axi_uartlite_module_sim_slave_attachment is
2206 
  port (
2207 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : out STD_LOGIC;
2208 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : out STD_LOGIC;
2209 
    s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
2210 
    enable_interrupts_reg : out STD_LOGIC;
2211 
    s_axi_rvalid : out STD_LOGIC;
2212 
    s_axi_bvalid : out STD_LOGIC;
2213 
    s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
2214 
    reset_TX_FIFO : out STD_LOGIC;
2215 
    reset_RX_FIFO : out STD_LOGIC;
2216 
    s_axi_awready : out STD_LOGIC;
2217 
    s_axi_arready : out STD_LOGIC;
2218 
    \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
2219 
    rx_Data_Present_Pre_reg : out STD_LOGIC;
2220 
    FIFO_Full_reg : out STD_LOGIC;
2221 
    bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
2222 
    fifo_wr : out STD_LOGIC;
2223 
    \INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
2224 
    tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
2225 
    enable_interrupts_reg_0 : out STD_LOGIC;
2226 
    s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
2227 
    bus2ip_reset : in STD_LOGIC;
2228 
    s_axi_aclk : in STD_LOGIC;
2229 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
2230 
    s_axi_arvalid : in STD_LOGIC;
2231 
    s_axi_aresetn : in STD_LOGIC;
2232 
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
2233 
    \out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
2234 
    rx_Buffer_Full : in STD_LOGIC;
2235 
    \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
2236 
    tx_Buffer_Full : in STD_LOGIC;
2237 
    enable_interrupts : in STD_LOGIC;
2238 
    status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
2239 
    s_axi_awvalid : in STD_LOGIC;
2240 
    s_axi_wvalid : in STD_LOGIC;
2241 
    s_axi_rready : in STD_LOGIC;
2242 
    s_axi_bready : in STD_LOGIC;
2243 
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
2244 
    s_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 )
2245 
  );
2246 
end axi_uartlite_module_sim_slave_attachment;
2247 
 
2248 
architecture STRUCTURE of axi_uartlite_module_sim_slave_attachment is
2249 
  signal I_DECODER_n_26 : STD_LOGIC;
2250 
  signal I_DECODER_n_27 : STD_LOGIC;
2251 
  signal I_DECODER_n_28 : STD_LOGIC;
2252 
  signal I_DECODER_n_5 : STD_LOGIC;
2253 
  signal I_DECODER_n_6 : STD_LOGIC;
2254 
  signal SIn_DBus : STD_LOGIC_VECTOR ( 0 to 7 );
2255 
  signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
2256 
  signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
2257 
  signal \bus2ip_addr_i[3]_i_2_n_0\ : STD_LOGIC;
2258 
  signal \bus2ip_addr_i_reg_n_0_[2]\ : STD_LOGIC;
2259 
  signal \bus2ip_addr_i_reg_n_0_[3]\ : STD_LOGIC;
2260 
  signal bus2ip_rnw_i : STD_LOGIC;
2261 
  signal bus2ip_rnw_i_i_1_n_0 : STD_LOGIC;
2262 
  signal ip2bus_error : STD_LOGIC;
2263 
  signal rst : STD_LOGIC;
2264 
  signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
2265 
  signal \^s_axi_bvalid\ : STD_LOGIC;
2266 
  signal s_axi_rdata_i : STD_LOGIC;
2267 
  signal \^s_axi_rvalid\ : STD_LOGIC;
2268 
  signal start2 : STD_LOGIC;
2269 
  signal start2_i_1_n_0 : STD_LOGIC;
2270 
  signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
2271 
  signal \state[0]_i_2_n_0\ : STD_LOGIC;
2272 
  signal \state[1]_i_2_n_0\ : STD_LOGIC;
2273 
  signal \state[1]_i_3_n_0\ : STD_LOGIC;
2274 
  attribute SOFT_HLUTNM : string;
2275 
  attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_2\ : label is "soft_lutpair9";
2276 
  attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair9";
2277 
begin
2278 
  s_axi_bresp(0) <= \^s_axi_bresp\(0);
2279 
  s_axi_bvalid <= \^s_axi_bvalid\;
2280 
  s_axi_rvalid <= \^s_axi_rvalid\;
2281 
I_DECODER: entity work.axi_uartlite_module_sim_address_decoder
2282 
     port map (
2283 
      D(1) => I_DECODER_n_5,
2284 
      D(0) => I_DECODER_n_6,
2285 
      FIFO_Full_reg => FIFO_Full_reg,
2286 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
2287 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
2288 
      \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\,
2289 
      \INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\,
2290 
      \INFERRED_GEN.cnt_i_reg[4]\(0) => Q(0),
2291 
      \INFERRED_GEN.cnt_i_reg[4]_0\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
2292 
      Q(1 downto 0) => state(1 downto 0),
2293 
      \bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg_n_0_[2]\,
2294 
      \bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg_n_0_[3]\,
2295 
      bus2ip_rdce(0) => bus2ip_rdce(0),
2296 
      bus2ip_rnw_i => bus2ip_rnw_i,
2297 
      enable_interrupts => enable_interrupts,
2298 
      enable_interrupts_reg => enable_interrupts_reg,
2299 
      enable_interrupts_reg_0 => enable_interrupts_reg_0,
2300 
      fifo_wr => fifo_wr,
2301 
      ip2bus_error => ip2bus_error,
2302 
      \out\(7 downto 0) => \out\(7 downto 0),
2303 
      reset_RX_FIFO => reset_RX_FIFO,
2304 
      reset_TX_FIFO => reset_TX_FIFO,
2305 
      rx_Buffer_Full => rx_Buffer_Full,
2306 
      rx_Data_Present_Pre_reg => rx_Data_Present_Pre_reg,
2307 
      s_axi_aclk => s_axi_aclk,
2308 
      s_axi_aresetn => s_axi_aresetn,
2309 
      s_axi_arready => s_axi_arready,
2310 
      s_axi_arvalid => s_axi_arvalid,
2311 
      s_axi_awready => s_axi_awready,
2312 
      s_axi_bready => s_axi_bready,
2313 
      s_axi_bresp(0) => \^s_axi_bresp\(0),
2314 
      \s_axi_bresp_i_reg[1]\ => I_DECODER_n_28,
2315 
      s_axi_bvalid_i_reg => I_DECODER_n_27,
2316 
      s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\,
2317 
      \s_axi_rdata_i_reg[7]\(7) => SIn_DBus(0),
2318 
      \s_axi_rdata_i_reg[7]\(6) => SIn_DBus(1),
2319 
      \s_axi_rdata_i_reg[7]\(5) => SIn_DBus(2),
2320 
      \s_axi_rdata_i_reg[7]\(4) => SIn_DBus(3),
2321 
      \s_axi_rdata_i_reg[7]\(3) => SIn_DBus(4),
2322 
      \s_axi_rdata_i_reg[7]\(2) => SIn_DBus(5),
2323 
      \s_axi_rdata_i_reg[7]\(1) => SIn_DBus(6),
2324 
      \s_axi_rdata_i_reg[7]\(0) => SIn_DBus(7),
2325 
      s_axi_rready => s_axi_rready,
2326 
      s_axi_rvalid_i_reg => I_DECODER_n_26,
2327 
      s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\,
2328 
      s_axi_wdata(2 downto 0) => s_axi_wdata(2 downto 0),
2329 
      s_axi_wvalid => \state[1]_i_3_n_0\,
2330 
      start2 => start2,
2331 
      \state_reg[0]\ => \state[0]_i_2_n_0\,
2332 
      \state_reg[1]\ => \state[1]_i_2_n_0\,
2333 
      status_reg(1 downto 0) => status_reg(1 downto 0),
2334 
      tx_Buffer_Empty_Pre_reg => tx_Buffer_Empty_Pre_reg,
2335 
      tx_Buffer_Full => tx_Buffer_Full
2336 
    );
2337 
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
2338 
    generic map(
2339 
      INIT => X"B8FFB800"
2340 
    )
2341 
        port map (
2342 
      I0 => s_axi_awaddr(0),
2343 
      I1 => \bus2ip_addr_i[3]_i_2_n_0\,
2344 
      I2 => s_axi_araddr(0),
2345 
      I3 => start2_i_1_n_0,
2346 
      I4 => \bus2ip_addr_i_reg_n_0_[2]\,
2347 
      O => \bus2ip_addr_i[2]_i_1_n_0\
2348 
    );
2349 
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
2350 
    generic map(
2351 
      INIT => X"B8FFB800"
2352 
    )
2353 
        port map (
2354 
      I0 => s_axi_awaddr(1),
2355 
      I1 => \bus2ip_addr_i[3]_i_2_n_0\,
2356 
      I2 => s_axi_araddr(1),
2357 
      I3 => start2_i_1_n_0,
2358 
      I4 => \bus2ip_addr_i_reg_n_0_[3]\,
2359 
      O => \bus2ip_addr_i[3]_i_1_n_0\
2360 
    );
2361 
\bus2ip_addr_i[3]_i_2\: unisim.vcomponents.LUT3
2362 
    generic map(
2363 
      INIT => X"EF"
2364 
    )
2365 
        port map (
2366 
      I0 => state(1),
2367 
      I1 => state(0),
2368 
      I2 => s_axi_arvalid,
2369 
      O => \bus2ip_addr_i[3]_i_2_n_0\
2370 
    );
2371 
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
2372 
     port map (
2373 
      C => s_axi_aclk,
2374 
      CE => '1',
2375 
      D => \bus2ip_addr_i[2]_i_1_n_0\,
2376 
      Q => \bus2ip_addr_i_reg_n_0_[2]\,
2377 
      R => rst
2378 
    );
2379 
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
2380 
     port map (
2381 
      C => s_axi_aclk,
2382 
      CE => '1',
2383 
      D => \bus2ip_addr_i[3]_i_1_n_0\,
2384 
      Q => \bus2ip_addr_i_reg_n_0_[3]\,
2385 
      R => rst
2386 
    );
2387 
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT6
2388 
    generic map(
2389 
      INIT => X"FFFFFFF7000000F0"
2390 
    )
2391 
        port map (
2392 
      I0 => s_axi_awvalid,
2393 
      I1 => s_axi_wvalid,
2394 
      I2 => s_axi_arvalid,
2395 
      I3 => state(0),
2396 
      I4 => state(1),
2397 
      I5 => bus2ip_rnw_i,
2398 
      O => bus2ip_rnw_i_i_1_n_0
2399 
    );
2400 
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
2401 
     port map (
2402 
      C => s_axi_aclk,
2403 
      CE => '1',
2404 
      D => bus2ip_rnw_i_i_1_n_0,
2405 
      Q => bus2ip_rnw_i,
2406 
      R => rst
2407 
    );
2408 
rst_reg: unisim.vcomponents.FDRE
2409 
     port map (
2410 
      C => s_axi_aclk,
2411 
      CE => '1',
2412 
      D => bus2ip_reset,
2413 
      Q => rst,
2414 
      R => '0'
2415 
    );
2416 
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
2417 
    generic map(
2418 
      INIT => '0'
2419 
    )
2420 
        port map (
2421 
      C => s_axi_aclk,
2422 
      CE => '1',
2423 
      D => I_DECODER_n_28,
2424 
      Q => \^s_axi_bresp\(0),
2425 
      R => rst
2426 
    );
2427 
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
2428 
    generic map(
2429 
      INIT => '0'
2430 
    )
2431 
        port map (
2432 
      C => s_axi_aclk,
2433 
      CE => '1',
2434 
      D => I_DECODER_n_27,
2435 
      Q => \^s_axi_bvalid\,
2436 
      R => rst
2437 
    );
2438 
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
2439 
    generic map(
2440 
      INIT => X"2"
2441 
    )
2442 
        port map (
2443 
      I0 => state(0),
2444 
      I1 => state(1),
2445 
      O => s_axi_rdata_i
2446 
    );
2447 
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
2448 
    generic map(
2449 
      INIT => '0'
2450 
    )
2451 
        port map (
2452 
      C => s_axi_aclk,
2453 
      CE => s_axi_rdata_i,
2454 
      D => SIn_DBus(7),
2455 
      Q => s_axi_rdata(0),
2456 
      R => rst
2457 
    );
2458 
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
2459 
    generic map(
2460 
      INIT => '0'
2461 
    )
2462 
        port map (
2463 
      C => s_axi_aclk,
2464 
      CE => s_axi_rdata_i,
2465 
      D => SIn_DBus(6),
2466 
      Q => s_axi_rdata(1),
2467 
      R => rst
2468 
    );
2469 
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
2470 
    generic map(
2471 
      INIT => '0'
2472 
    )
2473 
        port map (
2474 
      C => s_axi_aclk,
2475 
      CE => s_axi_rdata_i,
2476 
      D => SIn_DBus(5),
2477 
      Q => s_axi_rdata(2),
2478 
      R => rst
2479 
    );
2480 
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
2481 
    generic map(
2482 
      INIT => '0'
2483 
    )
2484 
        port map (
2485 
      C => s_axi_aclk,
2486 
      CE => s_axi_rdata_i,
2487 
      D => SIn_DBus(4),
2488 
      Q => s_axi_rdata(3),
2489 
      R => rst
2490 
    );
2491 
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
2492 
    generic map(
2493 
      INIT => '0'
2494 
    )
2495 
        port map (
2496 
      C => s_axi_aclk,
2497 
      CE => s_axi_rdata_i,
2498 
      D => SIn_DBus(3),
2499 
      Q => s_axi_rdata(4),
2500 
      R => rst
2501 
    );
2502 
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
2503 
    generic map(
2504 
      INIT => '0'
2505 
    )
2506 
        port map (
2507 
      C => s_axi_aclk,
2508 
      CE => s_axi_rdata_i,
2509 
      D => SIn_DBus(2),
2510 
      Q => s_axi_rdata(5),
2511 
      R => rst
2512 
    );
2513 
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
2514 
    generic map(
2515 
      INIT => '0'
2516 
    )
2517 
        port map (
2518 
      C => s_axi_aclk,
2519 
      CE => s_axi_rdata_i,
2520 
      D => SIn_DBus(1),
2521 
      Q => s_axi_rdata(6),
2522 
      R => rst
2523 
    );
2524 
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
2525 
    generic map(
2526 
      INIT => '0'
2527 
    )
2528 
        port map (
2529 
      C => s_axi_aclk,
2530 
      CE => s_axi_rdata_i,
2531 
      D => SIn_DBus(0),
2532 
      Q => s_axi_rdata(7),
2533 
      R => rst
2534 
    );
2535 
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
2536 
    generic map(
2537 
      INIT => '0'
2538 
    )
2539 
        port map (
2540 
      C => s_axi_aclk,
2541 
      CE => s_axi_rdata_i,
2542 
      D => ip2bus_error,
2543 
      Q => s_axi_rresp(0),
2544 
      R => rst
2545 
    );
2546 
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
2547 
    generic map(
2548 
      INIT => '0'
2549 
    )
2550 
        port map (
2551 
      C => s_axi_aclk,
2552 
      CE => '1',
2553 
      D => I_DECODER_n_26,
2554 
      Q => \^s_axi_rvalid\,
2555 
      R => rst
2556 
    );
2557 
start2_i_1: unisim.vcomponents.LUT5
2558 
    generic map(
2559 
      INIT => X"000000F8"
2560 
    )
2561 
        port map (
2562 
      I0 => s_axi_awvalid,
2563 
      I1 => s_axi_wvalid,
2564 
      I2 => s_axi_arvalid,
2565 
      I3 => state(0),
2566 
      I4 => state(1),
2567 
      O => start2_i_1_n_0
2568 
    );
2569 
start2_reg: unisim.vcomponents.FDRE
2570 
     port map (
2571 
      C => s_axi_aclk,
2572 
      CE => '1',
2573 
      D => start2_i_1_n_0,
2574 
      Q => start2,
2575 
      R => rst
2576 
    );
2577 
\state[0]_i_2\: unisim.vcomponents.LUT5
2578 
    generic map(
2579 
      INIT => X"002A2A2A"
2580 
    )
2581 
        port map (
2582 
      I0 => state(0),
2583 
      I1 => \^s_axi_rvalid\,
2584 
      I2 => s_axi_rready,
2585 
      I3 => s_axi_bready,
2586 
      I4 => \^s_axi_bvalid\,
2587 
      O => \state[0]_i_2_n_0\
2588 
    );
2589 
\state[1]_i_2\: unisim.vcomponents.LUT5
2590 
    generic map(
2591 
      INIT => X"002A2A2A"
2592 
    )
2593 
        port map (
2594 
      I0 => state(1),
2595 
      I1 => \^s_axi_rvalid\,
2596 
      I2 => s_axi_rready,
2597 
      I3 => s_axi_bready,
2598 
      I4 => \^s_axi_bvalid\,
2599 
      O => \state[1]_i_2_n_0\
2600 
    );
2601 
\state[1]_i_3\: unisim.vcomponents.LUT2
2602 
    generic map(
2603 
      INIT => X"8"
2604 
    )
2605 
        port map (
2606 
      I0 => s_axi_awvalid,
2607 
      I1 => s_axi_wvalid,
2608 
      O => \state[1]_i_3_n_0\
2609 
    );
2610 
\state_reg[0]\: unisim.vcomponents.FDRE
2611 
     port map (
2612 
      C => s_axi_aclk,
2613 
      CE => '1',
2614 
      D => I_DECODER_n_6,
2615 
      Q => state(0),
2616 
      R => rst
2617 
    );
2618 
\state_reg[1]\: unisim.vcomponents.FDRE
2619 
     port map (
2620 
      C => s_axi_aclk,
2621 
      CE => '1',
2622 
      D => I_DECODER_n_5,
2623 
      Q => state(1),
2624 
      R => rst
2625 
    );
2626 
end STRUCTURE;
2627 
library IEEE;
2628 
use IEEE.STD_LOGIC_1164.ALL;
2629 
library UNISIM;
2630 
use UNISIM.VCOMPONENTS.ALL;
2631 
entity axi_uartlite_module_sim_srl_fifo_f is
2632 
  port (
2633 
    tx_Buffer_Full : out STD_LOGIC;
2634 
    mux_Out : out STD_LOGIC;
2635 
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
2636 
    tx_Start0 : out STD_LOGIC;
2637 
    s_axi_aclk : in STD_LOGIC;
2638 
    p_4_in : in STD_LOGIC;
2639 
    \mux_sel_reg[2]\ : in STD_LOGIC;
2640 
    \mux_sel_reg[0]\ : in STD_LOGIC;
2641 
    reset_TX_FIFO_reg : in STD_LOGIC;
2642 
    s_axi_aresetn : in STD_LOGIC;
2643 
    fifo_Read : in STD_LOGIC;
2644 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
2645 
    Bus_RNW_reg : in STD_LOGIC;
2646 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
2647 
    tx_Data_Enable_reg : in STD_LOGIC;
2648 
    tx_DataBits : in STD_LOGIC;
2649 
    tx_Start : in STD_LOGIC;
2650 
    fifo_wr : in STD_LOGIC;
2651 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
2652 
  );
2653 
end axi_uartlite_module_sim_srl_fifo_f;
2654 
 
2655 
architecture STRUCTURE of axi_uartlite_module_sim_srl_fifo_f is
2656 
begin
2657 
I_SRL_FIFO_RBU_F: entity work.axi_uartlite_module_sim_srl_fifo_rbu_f
2658 
     port map (
2659 
      Bus_RNW_reg => Bus_RNW_reg,
2660 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
2661 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
2662 
      Q(0) => Q(0),
2663 
      fifo_Read => fifo_Read,
2664 
      fifo_wr => fifo_wr,
2665 
      mux_Out => mux_Out,
2666 
      \mux_sel_reg[0]\ => \mux_sel_reg[0]\,
2667 
      \mux_sel_reg[2]\ => \mux_sel_reg[2]\,
2668 
      p_4_in => p_4_in,
2669 
      reset_TX_FIFO_reg => reset_TX_FIFO_reg,
2670 
      s_axi_aclk => s_axi_aclk,
2671 
      s_axi_aresetn => s_axi_aresetn,
2672 
      s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
2673 
      tx_Buffer_Full => tx_Buffer_Full,
2674 
      tx_DataBits => tx_DataBits,
2675 
      tx_Data_Enable_reg => tx_Data_Enable_reg,
2676 
      tx_Start => tx_Start,
2677 
      tx_Start0 => tx_Start0
2678 
    );
2679 
end STRUCTURE;
2680 
library IEEE;
2681 
use IEEE.STD_LOGIC_1164.ALL;
2682 
library UNISIM;
2683 
use UNISIM.VCOMPONENTS.ALL;
2684 
entity axi_uartlite_module_sim_srl_fifo_f_0 is
2685 
  port (
2686 
    \status_reg_reg[2]\ : out STD_LOGIC;
2687 
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
2688 
    \status_reg_reg[2]_0\ : out STD_LOGIC;
2689 
    Interrupt0 : out STD_LOGIC;
2690 
    \out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
2691 
    s_axi_aclk : in STD_LOGIC;
2692 
    reset_RX_FIFO_reg : in STD_LOGIC;
2693 
    s_axi_aresetn : in STD_LOGIC;
2694 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
2695 
    Bus_RNW_reg : in STD_LOGIC;
2696 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
2697 
    Bus_RNW_reg_reg : in STD_LOGIC;
2698 
    status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
2699 
    fifo_Write : in STD_LOGIC;
2700 
    clr_Status : in STD_LOGIC;
2701 
    valid_rx : in STD_LOGIC;
2702 
    rx_Data_Present_Pre : in STD_LOGIC;
2703 
    enable_interrupts : in STD_LOGIC;
2704 
    \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
2705 
    tx_Buffer_Empty_Pre : in STD_LOGIC;
2706 
    \in\ : in STD_LOGIC_VECTOR ( 0 to 7 )
2707 
  );
2708 
  attribute ORIG_REF_NAME : string;
2709 
  attribute ORIG_REF_NAME of axi_uartlite_module_sim_srl_fifo_f_0 : entity is "srl_fifo_f";
2710 
end axi_uartlite_module_sim_srl_fifo_f_0;
2711 
 
2712 
architecture STRUCTURE of axi_uartlite_module_sim_srl_fifo_f_0 is
2713 
begin
2714 
I_SRL_FIFO_RBU_F: entity work.axi_uartlite_module_sim_srl_fifo_rbu_f_1
2715 
     port map (
2716 
      Bus_RNW_reg => Bus_RNW_reg,
2717 
      Bus_RNW_reg_reg => Bus_RNW_reg_reg,
2718 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
2719 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
2720 
      \INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
2721 
      Interrupt0 => Interrupt0,
2722 
      Q(0) => Q(0),
2723 
      clr_Status => clr_Status,
2724 
      enable_interrupts => enable_interrupts,
2725 
      fifo_Write => fifo_Write,
2726 
      \in\(0 to 7) => \in\(0 to 7),
2727 
      \out\(7 downto 0) => \out\(7 downto 0),
2728 
      reset_RX_FIFO_reg => reset_RX_FIFO_reg,
2729 
      rx_Data_Present_Pre => rx_Data_Present_Pre,
2730 
      s_axi_aclk => s_axi_aclk,
2731 
      s_axi_aresetn => s_axi_aresetn,
2732 
      status_reg(0) => status_reg(0),
2733 
      \status_reg_reg[2]\ => \status_reg_reg[2]\,
2734 
      \status_reg_reg[2]_0\ => \status_reg_reg[2]_0\,
2735 
      tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
2736 
      valid_rx => valid_rx
2737 
    );
2738 
end STRUCTURE;
2739 
library IEEE;
2740 
use IEEE.STD_LOGIC_1164.ALL;
2741 
library UNISIM;
2742 
use UNISIM.VCOMPONENTS.ALL;
2743 
entity axi_uartlite_module_sim_axi_lite_ipif is
2744 
  port (
2745 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
2746 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
2747 
    s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
2748 
    Bus_RNW_reg : out STD_LOGIC;
2749 
    s_axi_rvalid : out STD_LOGIC;
2750 
    s_axi_bvalid : out STD_LOGIC;
2751 
    s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
2752 
    reset_TX_FIFO : out STD_LOGIC;
2753 
    reset_RX_FIFO : out STD_LOGIC;
2754 
    s_axi_awready : out STD_LOGIC;
2755 
    s_axi_arready : out STD_LOGIC;
2756 
    \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
2757 
    rx_Data_Present_Pre_reg : out STD_LOGIC;
2758 
    FIFO_Full_reg : out STD_LOGIC;
2759 
    bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
2760 
    fifo_wr : out STD_LOGIC;
2761 
    \INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
2762 
    tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
2763 
    enable_interrupts_reg : out STD_LOGIC;
2764 
    s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
2765 
    bus2ip_reset : in STD_LOGIC;
2766 
    s_axi_aclk : in STD_LOGIC;
2767 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
2768 
    s_axi_arvalid : in STD_LOGIC;
2769 
    s_axi_aresetn : in STD_LOGIC;
2770 
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
2771 
    \out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
2772 
    rx_Buffer_Full : in STD_LOGIC;
2773 
    \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
2774 
    tx_Buffer_Full : in STD_LOGIC;
2775 
    enable_interrupts : in STD_LOGIC;
2776 
    status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
2777 
    s_axi_awvalid : in STD_LOGIC;
2778 
    s_axi_wvalid : in STD_LOGIC;
2779 
    s_axi_rready : in STD_LOGIC;
2780 
    s_axi_bready : in STD_LOGIC;
2781 
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
2782 
    s_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 )
2783 
  );
2784 
end axi_uartlite_module_sim_axi_lite_ipif;
2785 
 
2786 
architecture STRUCTURE of axi_uartlite_module_sim_axi_lite_ipif is
2787 
begin
2788 
I_SLAVE_ATTACHMENT: entity work.axi_uartlite_module_sim_slave_attachment
2789 
     port map (
2790 
      FIFO_Full_reg => FIFO_Full_reg,
2791 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
2792 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
2793 
      \INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\,
2794 
      \INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\,
2795 
      \INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
2796 
      Q(0) => Q(0),
2797 
      bus2ip_rdce(0) => bus2ip_rdce(0),
2798 
      bus2ip_reset => bus2ip_reset,
2799 
      enable_interrupts => enable_interrupts,
2800 
      enable_interrupts_reg => Bus_RNW_reg,
2801 
      enable_interrupts_reg_0 => enable_interrupts_reg,
2802 
      fifo_wr => fifo_wr,
2803 
      \out\(7 downto 0) => \out\(7 downto 0),
2804 
      reset_RX_FIFO => reset_RX_FIFO,
2805 
      reset_TX_FIFO => reset_TX_FIFO,
2806 
      rx_Buffer_Full => rx_Buffer_Full,
2807 
      rx_Data_Present_Pre_reg => rx_Data_Present_Pre_reg,
2808 
      s_axi_aclk => s_axi_aclk,
2809 
      s_axi_araddr(1 downto 0) => s_axi_araddr(1 downto 0),
2810 
      s_axi_aresetn => s_axi_aresetn,
2811 
      s_axi_arready => s_axi_arready,
2812 
      s_axi_arvalid => s_axi_arvalid,
2813 
      s_axi_awaddr(1 downto 0) => s_axi_awaddr(1 downto 0),
2814 
      s_axi_awready => s_axi_awready,
2815 
      s_axi_awvalid => s_axi_awvalid,
2816 
      s_axi_bready => s_axi_bready,
2817 
      s_axi_bresp(0) => s_axi_bresp(0),
2818 
      s_axi_bvalid => s_axi_bvalid,
2819 
      s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
2820 
      s_axi_rready => s_axi_rready,
2821 
      s_axi_rresp(0) => s_axi_rresp(0),
2822 
      s_axi_rvalid => s_axi_rvalid,
2823 
      s_axi_wdata(2 downto 0) => s_axi_wdata(2 downto 0),
2824 
      s_axi_wvalid => s_axi_wvalid,
2825 
      status_reg(1 downto 0) => status_reg(1 downto 0),
2826 
      tx_Buffer_Empty_Pre_reg => tx_Buffer_Empty_Pre_reg,
2827 
      tx_Buffer_Full => tx_Buffer_Full
2828 
    );
2829 
end STRUCTURE;
2830 
library IEEE;
2831 
use IEEE.STD_LOGIC_1164.ALL;
2832 
library UNISIM;
2833 
use UNISIM.VCOMPONENTS.ALL;
2834 
entity axi_uartlite_module_sim_uartlite_rx is
2835 
  port (
2836 
    \status_reg_reg[2]\ : out STD_LOGIC;
2837 
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
2838 
    status_reg_reg0 : out STD_LOGIC;
2839 
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
2840 
    \status_reg_reg[2]_0\ : out STD_LOGIC;
2841 
    Interrupt0 : out STD_LOGIC;
2842 
    \out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
2843 
    s_axi_aclk : in STD_LOGIC;
2844 
    en_16x_Baud : in STD_LOGIC;
2845 
    s_axi_aresetn : in STD_LOGIC;
2846 
    status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
2847 
    clr_Status : in STD_LOGIC;
2848 
    reset_RX_FIFO_reg : in STD_LOGIC;
2849 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
2850 
    Bus_RNW_reg : in STD_LOGIC;
2851 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
2852 
    Bus_RNW_reg_reg : in STD_LOGIC;
2853 
    rx_Data_Present_Pre : in STD_LOGIC;
2854 
    enable_interrupts : in STD_LOGIC;
2855 
    \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
2856 
    tx_Buffer_Empty_Pre : in STD_LOGIC;
2857 
    rx : in STD_LOGIC
2858 
  );
2859 
end axi_uartlite_module_sim_uartlite_rx;
2860 
 
2861 
architecture STRUCTURE of axi_uartlite_module_sim_uartlite_rx is
2862 
  signal DELAY_16_I_n_1 : STD_LOGIC;
2863 
  signal DELAY_16_I_n_10 : STD_LOGIC;
2864 
  signal DELAY_16_I_n_11 : STD_LOGIC;
2865 
  signal DELAY_16_I_n_12 : STD_LOGIC;
2866 
  signal RX_D2 : STD_LOGIC;
2867 
  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
2868 
  signal fifo_Write : STD_LOGIC;
2869 
  signal fifo_Write0 : STD_LOGIC;
2870 
  signal fifo_din : STD_LOGIC_VECTOR ( 1 to 8 );
2871 
  signal frame_err_ocrd : STD_LOGIC;
2872 
  signal p_11_out : STD_LOGIC;
2873 
  signal p_14_out : STD_LOGIC;
2874 
  signal p_17_out : STD_LOGIC;
2875 
  signal p_20_out : STD_LOGIC;
2876 
  signal p_26_out : STD_LOGIC;
2877 
  signal p_2_out : STD_LOGIC;
2878 
  signal p_5_out : STD_LOGIC;
2879 
  signal p_8_out : STD_LOGIC;
2880 
  signal running_reg_n_0 : STD_LOGIC;
2881 
  signal rx_1 : STD_LOGIC;
2882 
  signal rx_2 : STD_LOGIC;
2883 
  signal rx_3 : STD_LOGIC;
2884 
  signal rx_4 : STD_LOGIC;
2885 
  signal rx_5 : STD_LOGIC;
2886 
  signal rx_6 : STD_LOGIC;
2887 
  signal rx_7 : STD_LOGIC;
2888 
  signal rx_8 : STD_LOGIC;
2889 
  signal rx_9 : STD_LOGIC;
2890 
  signal start_Edge_Detected : STD_LOGIC;
2891 
  signal start_Edge_Detected0 : STD_LOGIC;
2892 
  signal start_Edge_Detected_i_2_n_0 : STD_LOGIC;
2893 
  signal stop_Bit_Position_reg_n_0 : STD_LOGIC;
2894 
  signal valid_rx : STD_LOGIC;
2895 
  signal valid_rx_i_1_n_0 : STD_LOGIC;
2896 
begin
2897 
  SR(0) <= \^sr\(0);
2898 
DELAY_16_I: entity work.axi_uartlite_module_sim_dynshreg_i_f
2899 
     port map (
2900 
      \SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ => DELAY_16_I_n_1,
2901 
      clr_Status => clr_Status,
2902 
      en_16x_Baud => en_16x_Baud,
2903 
      fifo_Write0 => fifo_Write0,
2904 
      frame_err_ocrd => frame_err_ocrd,
2905 
      frame_err_ocrd_reg => DELAY_16_I_n_11,
2906 
      \in\(0 to 7) => fifo_din(1 to 8),
2907 
      p_11_out => p_11_out,
2908 
      p_14_out => p_14_out,
2909 
      p_17_out => p_17_out,
2910 
      p_20_out => p_20_out,
2911 
      p_2_out => p_2_out,
2912 
      p_5_out => p_5_out,
2913 
      p_8_out => p_8_out,
2914 
      running_reg => DELAY_16_I_n_12,
2915 
      running_reg_0 => running_reg_n_0,
2916 
      s_axi_aclk => s_axi_aclk,
2917 
      s_axi_aresetn => s_axi_aresetn,
2918 
      scndry_out => RX_D2,
2919 
      start_Edge_Detected => start_Edge_Detected,
2920 
      status_reg(0) => status_reg(1),
2921 
      status_reg_reg0 => status_reg_reg0,
2922 
      stop_Bit_Position_reg => DELAY_16_I_n_10,
2923 
      stop_Bit_Position_reg_0 => stop_Bit_Position_reg_n_0,
2924 
      valid_rx => valid_rx
2925 
    );
2926 
INPUT_DOUBLE_REGS3: entity work.axi_uartlite_module_sim_cdc_sync
2927 
     port map (
2928 
      EN_16x_Baud_reg => DELAY_16_I_n_1,
2929 
      \in\(0) => fifo_din(1),
2930 
      p_26_out => p_26_out,
2931 
      rx => rx,
2932 
      s_axi_aclk => s_axi_aclk,
2933 
      s_axi_aresetn => s_axi_aresetn,
2934 
      scndry_out => RX_D2,
2935 
      start_Edge_Detected => start_Edge_Detected
2936 
    );
2937 
Interrupt_i_1: unisim.vcomponents.LUT1
2938 
    generic map(
2939 
      INIT => X"1"
2940 
    )
2941 
        port map (
2942 
      I0 => s_axi_aresetn,
2943 
      O => \^sr\(0)
2944 
    );
2945 
\SERIAL_TO_PARALLEL[1].fifo_din_reg[1]\: unisim.vcomponents.FDRE
2946 
     port map (
2947 
      C => s_axi_aclk,
2948 
      CE => '1',
2949 
      D => p_26_out,
2950 
      Q => fifo_din(1),
2951 
      R => '0'
2952 
    );
2953 
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\: unisim.vcomponents.FDRE
2954 
     port map (
2955 
      C => s_axi_aclk,
2956 
      CE => '1',
2957 
      D => p_20_out,
2958 
      Q => fifo_din(2),
2959 
      R => '0'
2960 
    );
2961 
\SERIAL_TO_PARALLEL[3].fifo_din_reg[3]\: unisim.vcomponents.FDRE
2962 
     port map (
2963 
      C => s_axi_aclk,
2964 
      CE => '1',
2965 
      D => p_17_out,
2966 
      Q => fifo_din(3),
2967 
      R => '0'
2968 
    );
2969 
\SERIAL_TO_PARALLEL[4].fifo_din_reg[4]\: unisim.vcomponents.FDRE
2970 
     port map (
2971 
      C => s_axi_aclk,
2972 
      CE => '1',
2973 
      D => p_14_out,
2974 
      Q => fifo_din(4),
2975 
      R => '0'
2976 
    );
2977 
\SERIAL_TO_PARALLEL[5].fifo_din_reg[5]\: unisim.vcomponents.FDRE
2978 
     port map (
2979 
      C => s_axi_aclk,
2980 
      CE => '1',
2981 
      D => p_11_out,
2982 
      Q => fifo_din(5),
2983 
      R => '0'
2984 
    );
2985 
\SERIAL_TO_PARALLEL[6].fifo_din_reg[6]\: unisim.vcomponents.FDRE
2986 
     port map (
2987 
      C => s_axi_aclk,
2988 
      CE => '1',
2989 
      D => p_8_out,
2990 
      Q => fifo_din(6),
2991 
      R => '0'
2992 
    );
2993 
\SERIAL_TO_PARALLEL[7].fifo_din_reg[7]\: unisim.vcomponents.FDRE
2994 
     port map (
2995 
      C => s_axi_aclk,
2996 
      CE => '1',
2997 
      D => p_5_out,
2998 
      Q => fifo_din(7),
2999 
      R => '0'
3000 
    );
3001 
\SERIAL_TO_PARALLEL[8].fifo_din_reg[8]\: unisim.vcomponents.FDRE
3002 
     port map (
3003 
      C => s_axi_aclk,
3004 
      CE => '1',
3005 
      D => p_2_out,
3006 
      Q => fifo_din(8),
3007 
      R => '0'
3008 
    );
3009 
SRL_FIFO_I: entity work.axi_uartlite_module_sim_srl_fifo_f_0
3010 
     port map (
3011 
      Bus_RNW_reg => Bus_RNW_reg,
3012 
      Bus_RNW_reg_reg => Bus_RNW_reg_reg,
3013 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
3014 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
3015 
      \INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
3016 
      Interrupt0 => Interrupt0,
3017 
      Q(0) => Q(0),
3018 
      clr_Status => clr_Status,
3019 
      enable_interrupts => enable_interrupts,
3020 
      fifo_Write => fifo_Write,
3021 
      \in\(0 to 7) => fifo_din(1 to 8),
3022 
      \out\(7 downto 0) => \out\(7 downto 0),
3023 
      reset_RX_FIFO_reg => reset_RX_FIFO_reg,
3024 
      rx_Data_Present_Pre => rx_Data_Present_Pre,
3025 
      s_axi_aclk => s_axi_aclk,
3026 
      s_axi_aresetn => s_axi_aresetn,
3027 
      status_reg(0) => status_reg(0),
3028 
      \status_reg_reg[2]\ => \status_reg_reg[2]\,
3029 
      \status_reg_reg[2]_0\ => \status_reg_reg[2]_0\,
3030 
      tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
3031 
      valid_rx => valid_rx
3032 
    );
3033 
fifo_Write_reg: unisim.vcomponents.FDRE
3034 
     port map (
3035 
      C => s_axi_aclk,
3036 
      CE => '1',
3037 
      D => fifo_Write0,
3038 
      Q => fifo_Write,
3039 
      R => \^sr\(0)
3040 
    );
3041 
frame_err_ocrd_reg: unisim.vcomponents.FDRE
3042 
     port map (
3043 
      C => s_axi_aclk,
3044 
      CE => '1',
3045 
      D => DELAY_16_I_n_11,
3046 
      Q => frame_err_ocrd,
3047 
      R => \^sr\(0)
3048 
    );
3049 
running_reg: unisim.vcomponents.FDRE
3050 
     port map (
3051 
      C => s_axi_aclk,
3052 
      CE => '1',
3053 
      D => DELAY_16_I_n_12,
3054 
      Q => running_reg_n_0,
3055 
      R => \^sr\(0)
3056 
    );
3057 
rx_1_reg: unisim.vcomponents.FDRE
3058 
     port map (
3059 
      C => s_axi_aclk,
3060 
      CE => en_16x_Baud,
3061 
      D => RX_D2,
3062 
      Q => rx_1,
3063 
      R => \^sr\(0)
3064 
    );
3065 
rx_2_reg: unisim.vcomponents.FDRE
3066 
     port map (
3067 
      C => s_axi_aclk,
3068 
      CE => en_16x_Baud,
3069 
      D => rx_1,
3070 
      Q => rx_2,
3071 
      R => \^sr\(0)
3072 
    );
3073 
rx_3_reg: unisim.vcomponents.FDRE
3074 
     port map (
3075 
      C => s_axi_aclk,
3076 
      CE => en_16x_Baud,
3077 
      D => rx_2,
3078 
      Q => rx_3,
3079 
      R => \^sr\(0)
3080 
    );
3081 
rx_4_reg: unisim.vcomponents.FDRE
3082 
     port map (
3083 
      C => s_axi_aclk,
3084 
      CE => en_16x_Baud,
3085 
      D => rx_3,
3086 
      Q => rx_4,
3087 
      R => \^sr\(0)
3088 
    );
3089 
rx_5_reg: unisim.vcomponents.FDRE
3090 
     port map (
3091 
      C => s_axi_aclk,
3092 
      CE => en_16x_Baud,
3093 
      D => rx_4,
3094 
      Q => rx_5,
3095 
      R => \^sr\(0)
3096 
    );
3097 
rx_6_reg: unisim.vcomponents.FDRE
3098 
     port map (
3099 
      C => s_axi_aclk,
3100 
      CE => en_16x_Baud,
3101 
      D => rx_5,
3102 
      Q => rx_6,
3103 
      R => \^sr\(0)
3104 
    );
3105 
rx_7_reg: unisim.vcomponents.FDRE
3106 
     port map (
3107 
      C => s_axi_aclk,
3108 
      CE => en_16x_Baud,
3109 
      D => rx_6,
3110 
      Q => rx_7,
3111 
      R => \^sr\(0)
3112 
    );
3113 
rx_8_reg: unisim.vcomponents.FDRE
3114 
     port map (
3115 
      C => s_axi_aclk,
3116 
      CE => en_16x_Baud,
3117 
      D => rx_7,
3118 
      Q => rx_8,
3119 
      R => \^sr\(0)
3120 
    );
3121 
rx_9_reg: unisim.vcomponents.FDRE
3122 
     port map (
3123 
      C => s_axi_aclk,
3124 
      CE => en_16x_Baud,
3125 
      D => rx_8,
3126 
      Q => rx_9,
3127 
      R => \^sr\(0)
3128 
    );
3129 
start_Edge_Detected_i_1: unisim.vcomponents.LUT6
3130 
    generic map(
3131 
      INIT => X"0000000000000010"
3132 
    )
3133 
        port map (
3134 
      I0 => rx_8,
3135 
      I1 => rx_2,
3136 
      I2 => start_Edge_Detected_i_2_n_0,
3137 
      I3 => rx_3,
3138 
      I4 => rx_1,
3139 
      I5 => frame_err_ocrd,
3140 
      O => start_Edge_Detected0
3141 
    );
3142 
start_Edge_Detected_i_2: unisim.vcomponents.LUT6
3143 
    generic map(
3144 
      INIT => X"0000000000000010"
3145 
    )
3146 
        port map (
3147 
      I0 => rx_5,
3148 
      I1 => rx_7,
3149 
      I2 => rx_9,
3150 
      I3 => running_reg_n_0,
3151 
      I4 => rx_6,
3152 
      I5 => rx_4,
3153 
      O => start_Edge_Detected_i_2_n_0
3154 
    );
3155 
start_Edge_Detected_reg: unisim.vcomponents.FDRE
3156 
     port map (
3157 
      C => s_axi_aclk,
3158 
      CE => en_16x_Baud,
3159 
      D => start_Edge_Detected0,
3160 
      Q => start_Edge_Detected,
3161 
      R => \^sr\(0)
3162 
    );
3163 
stop_Bit_Position_reg: unisim.vcomponents.FDRE
3164 
     port map (
3165 
      C => s_axi_aclk,
3166 
      CE => '1',
3167 
      D => DELAY_16_I_n_10,
3168 
      Q => stop_Bit_Position_reg_n_0,
3169 
      R => \^sr\(0)
3170 
    );
3171 
valid_rx_i_1: unisim.vcomponents.LUT3
3172 
    generic map(
3173 
      INIT => X"BA"
3174 
    )
3175 
        port map (
3176 
      I0 => start_Edge_Detected,
3177 
      I1 => fifo_Write,
3178 
      I2 => valid_rx,
3179 
      O => valid_rx_i_1_n_0
3180 
    );
3181 
valid_rx_reg: unisim.vcomponents.FDRE
3182 
     port map (
3183 
      C => s_axi_aclk,
3184 
      CE => '1',
3185 
      D => valid_rx_i_1_n_0,
3186 
      Q => valid_rx,
3187 
      R => \^sr\(0)
3188 
    );
3189 
end STRUCTURE;
3190 
library IEEE;
3191 
use IEEE.STD_LOGIC_1164.ALL;
3192 
library UNISIM;
3193 
use UNISIM.VCOMPONENTS.ALL;
3194 
entity axi_uartlite_module_sim_uartlite_tx is
3195 
  port (
3196 
    tx_Buffer_Full : out STD_LOGIC;
3197 
    tx : out STD_LOGIC;
3198 
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
3199 
    s_axi_aclk : in STD_LOGIC;
3200 
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
3201 
    en_16x_Baud : in STD_LOGIC;
3202 
    reset_TX_FIFO_reg : in STD_LOGIC;
3203 
    s_axi_aresetn : in STD_LOGIC;
3204 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
3205 
    Bus_RNW_reg : in STD_LOGIC;
3206 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
3207 
    fifo_wr : in STD_LOGIC;
3208 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
3209 
  );
3210 
end axi_uartlite_module_sim_uartlite_tx;
3211 
 
3212 
architecture STRUCTURE of axi_uartlite_module_sim_uartlite_tx is
3213 
  signal MID_START_BIT_SRL16_I_n_0 : STD_LOGIC;
3214 
  signal TX0 : STD_LOGIC;
3215 
  signal fifo_Read : STD_LOGIC;
3216 
  signal fifo_Read0 : STD_LOGIC;
3217 
  signal mux_Out : STD_LOGIC;
3218 
  signal \mux_sel[0]_i_1_n_0\ : STD_LOGIC;
3219 
  signal \mux_sel[1]_i_1_n_0\ : STD_LOGIC;
3220 
  signal \mux_sel[2]_i_1_n_0\ : STD_LOGIC;
3221 
  signal \mux_sel_reg_n_0_[0]\ : STD_LOGIC;
3222 
  signal \mux_sel_reg_n_0_[2]\ : STD_LOGIC;
3223 
  signal p_4_in : STD_LOGIC;
3224 
  signal serial_Data : STD_LOGIC;
3225 
  signal tx_DataBits : STD_LOGIC;
3226 
  signal tx_DataBits0 : STD_LOGIC;
3227 
  signal tx_Data_Enable_reg_n_0 : STD_LOGIC;
3228 
  signal tx_Start : STD_LOGIC;
3229 
  signal tx_Start0 : STD_LOGIC;
3230 
  attribute SOFT_HLUTNM : string;
3231 
  attribute SOFT_HLUTNM of \mux_sel[0]_i_1\ : label is "soft_lutpair21";
3232 
  attribute SOFT_HLUTNM of \mux_sel[1]_i_1\ : label is "soft_lutpair21";
3233 
begin
3234 
MID_START_BIT_SRL16_I: entity work.\axi_uartlite_module_sim_dynshreg_i_f__parameterized0\
3235 
     port map (
3236 
      en_16x_Baud => en_16x_Baud,
3237 
      s_axi_aclk => s_axi_aclk,
3238 
      tx_Data_Enable_reg => MID_START_BIT_SRL16_I_n_0,
3239 
      tx_Data_Enable_reg_0 => tx_Data_Enable_reg_n_0
3240 
    );
3241 
SRL_FIFO_I: entity work.axi_uartlite_module_sim_srl_fifo_f
3242 
     port map (
3243 
      Bus_RNW_reg => Bus_RNW_reg,
3244 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
3245 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
3246 
      Q(0) => Q(0),
3247 
      fifo_Read => fifo_Read,
3248 
      fifo_wr => fifo_wr,
3249 
      mux_Out => mux_Out,
3250 
      \mux_sel_reg[0]\ => \mux_sel_reg_n_0_[0]\,
3251 
      \mux_sel_reg[2]\ => \mux_sel_reg_n_0_[2]\,
3252 
      p_4_in => p_4_in,
3253 
      reset_TX_FIFO_reg => reset_TX_FIFO_reg,
3254 
      s_axi_aclk => s_axi_aclk,
3255 
      s_axi_aresetn => s_axi_aresetn,
3256 
      s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
3257 
      tx_Buffer_Full => tx_Buffer_Full,
3258 
      tx_DataBits => tx_DataBits,
3259 
      tx_Data_Enable_reg => tx_Data_Enable_reg_n_0,
3260 
      tx_Start => tx_Start,
3261 
      tx_Start0 => tx_Start0
3262 
    );
3263 
TX_i_1: unisim.vcomponents.LUT3
3264 
    generic map(
3265 
      INIT => X"31"
3266 
    )
3267 
        port map (
3268 
      I0 => tx_DataBits,
3269 
      I1 => tx_Start,
3270 
      I2 => serial_Data,
3271 
      O => TX0
3272 
    );
3273 
TX_reg: unisim.vcomponents.FDSE
3274 
     port map (
3275 
      C => s_axi_aclk,
3276 
      CE => '1',
3277 
      D => TX0,
3278 
      Q => tx,
3279 
      S => SR(0)
3280 
    );
3281 
fifo_Read_i_1: unisim.vcomponents.LUT4
3282 
    generic map(
3283 
      INIT => X"0100"
3284 
    )
3285 
        port map (
3286 
      I0 => \mux_sel_reg_n_0_[0]\,
3287 
      I1 => \mux_sel_reg_n_0_[2]\,
3288 
      I2 => p_4_in,
3289 
      I3 => tx_Data_Enable_reg_n_0,
3290 
      O => fifo_Read0
3291 
    );
3292 
fifo_Read_reg: unisim.vcomponents.FDRE
3293 
     port map (
3294 
      C => s_axi_aclk,
3295 
      CE => '1',
3296 
      D => fifo_Read0,
3297 
      Q => fifo_Read,
3298 
      R => SR(0)
3299 
    );
3300 
\mux_sel[0]_i_1\: unisim.vcomponents.LUT5
3301 
    generic map(
3302 
      INIT => X"E1F0F1F0"
3303 
    )
3304 
        port map (
3305 
      I0 => p_4_in,
3306 
      I1 => \mux_sel_reg_n_0_[2]\,
3307 
      I2 => \mux_sel_reg_n_0_[0]\,
3308 
      I3 => tx_Data_Enable_reg_n_0,
3309 
      I4 => tx_DataBits,
3310 
      O => \mux_sel[0]_i_1_n_0\
3311 
    );
3312 
\mux_sel[1]_i_1\: unisim.vcomponents.LUT5
3313 
    generic map(
3314 
      INIT => X"99AAABAA"
3315 
    )
3316 
        port map (
3317 
      I0 => p_4_in,
3318 
      I1 => \mux_sel_reg_n_0_[2]\,
3319 
      I2 => \mux_sel_reg_n_0_[0]\,
3320 
      I3 => tx_Data_Enable_reg_n_0,
3321 
      I4 => tx_DataBits,
3322 
      O => \mux_sel[1]_i_1_n_0\
3323 
    );
3324 
\mux_sel[2]_i_1\: unisim.vcomponents.LUT5
3325 
    generic map(
3326 
      INIT => X"7777888C"
3327 
    )
3328 
        port map (
3329 
      I0 => tx_DataBits,
3330 
      I1 => tx_Data_Enable_reg_n_0,
3331 
      I2 => \mux_sel_reg_n_0_[0]\,
3332 
      I3 => p_4_in,
3333 
      I4 => \mux_sel_reg_n_0_[2]\,
3334 
      O => \mux_sel[2]_i_1_n_0\
3335 
    );
3336 
\mux_sel_reg[0]\: unisim.vcomponents.FDSE
3337 
     port map (
3338 
      C => s_axi_aclk,
3339 
      CE => '1',
3340 
      D => \mux_sel[0]_i_1_n_0\,
3341 
      Q => \mux_sel_reg_n_0_[0]\,
3342 
      S => SR(0)
3343 
    );
3344 
\mux_sel_reg[1]\: unisim.vcomponents.FDSE
3345 
     port map (
3346 
      C => s_axi_aclk,
3347 
      CE => '1',
3348 
      D => \mux_sel[1]_i_1_n_0\,
3349 
      Q => p_4_in,
3350 
      S => SR(0)
3351 
    );
3352 
\mux_sel_reg[2]\: unisim.vcomponents.FDSE
3353 
     port map (
3354 
      C => s_axi_aclk,
3355 
      CE => '1',
3356 
      D => \mux_sel[2]_i_1_n_0\,
3357 
      Q => \mux_sel_reg_n_0_[2]\,
3358 
      S => SR(0)
3359 
    );
3360 
serial_Data_reg: unisim.vcomponents.FDRE
3361 
     port map (
3362 
      C => s_axi_aclk,
3363 
      CE => '1',
3364 
      D => mux_Out,
3365 
      Q => serial_Data,
3366 
      R => SR(0)
3367 
    );
3368 
tx_DataBits_i_1: unisim.vcomponents.LUT4
3369 
    generic map(
3370 
      INIT => X"0F08"
3371 
    )
3372 
        port map (
3373 
      I0 => tx_Start,
3374 
      I1 => tx_Data_Enable_reg_n_0,
3375 
      I2 => fifo_Read,
3376 
      I3 => tx_DataBits,
3377 
      O => tx_DataBits0
3378 
    );
3379 
tx_DataBits_reg: unisim.vcomponents.FDRE
3380 
     port map (
3381 
      C => s_axi_aclk,
3382 
      CE => '1',
3383 
      D => tx_DataBits0,
3384 
      Q => tx_DataBits,
3385 
      R => SR(0)
3386 
    );
3387 
tx_Data_Enable_reg: unisim.vcomponents.FDRE
3388 
     port map (
3389 
      C => s_axi_aclk,
3390 
      CE => '1',
3391 
      D => MID_START_BIT_SRL16_I_n_0,
3392 
      Q => tx_Data_Enable_reg_n_0,
3393 
      R => SR(0)
3394 
    );
3395 
tx_Start_reg: unisim.vcomponents.FDRE
3396 
     port map (
3397 
      C => s_axi_aclk,
3398 
      CE => '1',
3399 
      D => tx_Start0,
3400 
      Q => tx_Start,
3401 
      R => SR(0)
3402 
    );
3403 
end STRUCTURE;
3404 
library IEEE;
3405 
use IEEE.STD_LOGIC_1164.ALL;
3406 
library UNISIM;
3407 
use UNISIM.VCOMPONENTS.ALL;
3408 
entity axi_uartlite_module_sim_uartlite_core is
3409 
  port (
3410 
    status_reg : out STD_LOGIC_VECTOR ( 1 downto 0 );
3411 
    bus2ip_reset : out STD_LOGIC;
3412 
    rx_Buffer_Full : out STD_LOGIC;
3413 
    tx_Buffer_Full : out STD_LOGIC;
3414 
    tx : out STD_LOGIC;
3415 
    interrupt : out STD_LOGIC;
3416 
    enable_interrupts : out STD_LOGIC;
3417 
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
3418 
    \INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
3419 
    \out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
3420 
    s_axi_aclk : in STD_LOGIC;
3421 
    reset_TX_FIFO : in STD_LOGIC;
3422 
    reset_RX_FIFO : in STD_LOGIC;
3423 
    bus2ip_rdce : in STD_LOGIC_VECTOR ( 0 to 0 );
3424 
    \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ : in STD_LOGIC;
3425 
    \INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC;
3426 
    \INFERRED_GEN.cnt_i_reg[4]_0\ : in STD_LOGIC;
3427 
    s_axi_aresetn : in STD_LOGIC;
3428 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
3429 
    Bus_RNW_reg : in STD_LOGIC;
3430 
    \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
3431 
    Bus_RNW_reg_reg : in STD_LOGIC;
3432 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
3433 
    \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
3434 
    rx : in STD_LOGIC;
3435 
    fifo_wr : in STD_LOGIC;
3436 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
3437 
  );
3438 
end axi_uartlite_module_sim_uartlite_core;
3439 
 
3440 
architecture STRUCTURE of axi_uartlite_module_sim_uartlite_core is
3441 
  signal \^inferred_gen.cnt_i_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 );
3442 
  signal Interrupt0 : STD_LOGIC;
3443 
  signal UARTLITE_RX_I_n_4 : STD_LOGIC;
3444 
  signal \^bus2ip_reset\ : STD_LOGIC;
3445 
  signal clr_Status : STD_LOGIC;
3446 
  signal en_16x_Baud : STD_LOGIC;
3447 
  signal \^enable_interrupts\ : STD_LOGIC;
3448 
  signal reset_RX_FIFO_reg_n_0 : STD_LOGIC;
3449 
  signal reset_TX_FIFO_reg_n_0 : STD_LOGIC;
3450 
  signal rx_Data_Present_Pre : STD_LOGIC;
3451 
  signal \^status_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 );
3452 
  signal status_reg_reg0 : STD_LOGIC;
3453 
  signal tx_Buffer_Empty_Pre : STD_LOGIC;
3454 
begin
3455 
  \INFERRED_GEN.cnt_i_reg[2]\(0) <= \^inferred_gen.cnt_i_reg[2]\(0);
3456 
  bus2ip_reset <= \^bus2ip_reset\;
3457 
  enable_interrupts <= \^enable_interrupts\;
3458 
  status_reg(1 downto 0) <= \^status_reg\(1 downto 0);
3459 
BAUD_RATE_I: entity work.axi_uartlite_module_sim_baudrate
3460 
     port map (
3461 
      SR(0) => \^bus2ip_reset\,
3462 
      en_16x_Baud => en_16x_Baud,
3463 
      s_axi_aclk => s_axi_aclk
3464 
    );
3465 
Interrupt_reg: unisim.vcomponents.FDRE
3466 
     port map (
3467 
      C => s_axi_aclk,
3468 
      CE => '1',
3469 
      D => Interrupt0,
3470 
      Q => interrupt,
3471 
      R => \^bus2ip_reset\
3472 
    );
3473 
UARTLITE_RX_I: entity work.axi_uartlite_module_sim_uartlite_rx
3474 
     port map (
3475 
      Bus_RNW_reg => Bus_RNW_reg,
3476 
      Bus_RNW_reg_reg => Bus_RNW_reg_reg,
3477 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
3478 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
3479 
      \INFERRED_GEN.cnt_i_reg[4]\(0) => \^inferred_gen.cnt_i_reg[2]\(0),
3480 
      Interrupt0 => Interrupt0,
3481 
      Q(0) => Q(0),
3482 
      SR(0) => \^bus2ip_reset\,
3483 
      clr_Status => clr_Status,
3484 
      en_16x_Baud => en_16x_Baud,
3485 
      enable_interrupts => \^enable_interrupts\,
3486 
      \out\(7 downto 0) => \out\(7 downto 0),
3487 
      reset_RX_FIFO_reg => reset_RX_FIFO_reg_n_0,
3488 
      rx => rx,
3489 
      rx_Data_Present_Pre => rx_Data_Present_Pre,
3490 
      s_axi_aclk => s_axi_aclk,
3491 
      s_axi_aresetn => s_axi_aresetn,
3492 
      status_reg(1 downto 0) => \^status_reg\(1 downto 0),
3493 
      status_reg_reg0 => status_reg_reg0,
3494 
      \status_reg_reg[2]\ => rx_Buffer_Full,
3495 
      \status_reg_reg[2]_0\ => UARTLITE_RX_I_n_4,
3496 
      tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre
3497 
    );
3498 
UARTLITE_TX_I: entity work.axi_uartlite_module_sim_uartlite_tx
3499 
     port map (
3500 
      Bus_RNW_reg => Bus_RNW_reg,
3501 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
3502 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
3503 
      Q(0) => \^inferred_gen.cnt_i_reg[2]\(0),
3504 
      SR(0) => \^bus2ip_reset\,
3505 
      en_16x_Baud => en_16x_Baud,
3506 
      fifo_wr => fifo_wr,
3507 
      reset_TX_FIFO_reg => reset_TX_FIFO_reg_n_0,
3508 
      s_axi_aclk => s_axi_aclk,
3509 
      s_axi_aresetn => s_axi_aresetn,
3510 
      s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
3511 
      tx => tx,
3512 
      tx_Buffer_Full => tx_Buffer_Full
3513 
    );
3514 
clr_Status_reg: unisim.vcomponents.FDRE
3515 
     port map (
3516 
      C => s_axi_aclk,
3517 
      CE => '1',
3518 
      D => bus2ip_rdce(0),
3519 
      Q => clr_Status,
3520 
      R => \^bus2ip_reset\
3521 
    );
3522 
enable_interrupts_reg: unisim.vcomponents.FDRE
3523 
     port map (
3524 
      C => s_axi_aclk,
3525 
      CE => '1',
3526 
      D => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\,
3527 
      Q => \^enable_interrupts\,
3528 
      R => \^bus2ip_reset\
3529 
    );
3530 
reset_RX_FIFO_reg: unisim.vcomponents.FDSE
3531 
     port map (
3532 
      C => s_axi_aclk,
3533 
      CE => '1',
3534 
      D => reset_RX_FIFO,
3535 
      Q => reset_RX_FIFO_reg_n_0,
3536 
      S => \^bus2ip_reset\
3537 
    );
3538 
reset_TX_FIFO_reg: unisim.vcomponents.FDSE
3539 
     port map (
3540 
      C => s_axi_aclk,
3541 
      CE => '1',
3542 
      D => reset_TX_FIFO,
3543 
      Q => reset_TX_FIFO_reg_n_0,
3544 
      S => \^bus2ip_reset\
3545 
    );
3546 
rx_Data_Present_Pre_reg: unisim.vcomponents.FDRE
3547 
     port map (
3548 
      C => s_axi_aclk,
3549 
      CE => '1',
3550 
      D => \INFERRED_GEN.cnt_i_reg[4]_0\,
3551 
      Q => rx_Data_Present_Pre,
3552 
      R => '0'
3553 
    );
3554 
\status_reg_reg[1]\: unisim.vcomponents.FDRE
3555 
    generic map(
3556 
      INIT => '0'
3557 
    )
3558 
        port map (
3559 
      C => s_axi_aclk,
3560 
      CE => '1',
3561 
      D => status_reg_reg0,
3562 
      Q => \^status_reg\(1),
3563 
      R => '0'
3564 
    );
3565 
\status_reg_reg[2]\: unisim.vcomponents.FDRE
3566 
    generic map(
3567 
      INIT => '0'
3568 
    )
3569 
        port map (
3570 
      C => s_axi_aclk,
3571 
      CE => '1',
3572 
      D => UARTLITE_RX_I_n_4,
3573 
      Q => \^status_reg\(0),
3574 
      R => '0'
3575 
    );
3576 
tx_Buffer_Empty_Pre_reg: unisim.vcomponents.FDRE
3577 
     port map (
3578 
      C => s_axi_aclk,
3579 
      CE => '1',
3580 
      D => \INFERRED_GEN.cnt_i_reg[4]\,
3581 
      Q => tx_Buffer_Empty_Pre,
3582 
      R => '0'
3583 
    );
3584 
end STRUCTURE;
3585 
library IEEE;
3586 
use IEEE.STD_LOGIC_1164.ALL;
3587 
library UNISIM;
3588 
use UNISIM.VCOMPONENTS.ALL;
3589 
entity axi_uartlite_module_sim_axi_uartlite is
3590 
  port (
3591 
    s_axi_aclk : in STD_LOGIC;
3592 
    s_axi_aresetn : in STD_LOGIC;
3593 
    interrupt : out STD_LOGIC;
3594 
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
3595 
    s_axi_awvalid : in STD_LOGIC;
3596 
    s_axi_awready : out STD_LOGIC;
3597 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
3598 
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
3599 
    s_axi_wvalid : in STD_LOGIC;
3600 
    s_axi_wready : out STD_LOGIC;
3601 
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
3602 
    s_axi_bvalid : out STD_LOGIC;
3603 
    s_axi_bready : in STD_LOGIC;
3604 
    s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
3605 
    s_axi_arvalid : in STD_LOGIC;
3606 
    s_axi_arready : out STD_LOGIC;
3607 
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
3608 
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
3609 
    s_axi_rvalid : out STD_LOGIC;
3610 
    s_axi_rready : in STD_LOGIC;
3611 
    rx : in STD_LOGIC;
3612 
    tx : out STD_LOGIC
3613 
  );
3614 
  attribute C_BAUDRATE : integer;
3615 
  attribute C_BAUDRATE of axi_uartlite_module_sim_axi_uartlite : entity is 38400;
3616 
  attribute C_DATA_BITS : integer;
3617 
  attribute C_DATA_BITS of axi_uartlite_module_sim_axi_uartlite : entity is 8;
3618 
  attribute C_FAMILY : string;
3619 
  attribute C_FAMILY of axi_uartlite_module_sim_axi_uartlite : entity is "kintex7";
3620 
  attribute C_ODD_PARITY : integer;
3621 
  attribute C_ODD_PARITY of axi_uartlite_module_sim_axi_uartlite : entity is 0;
3622 
  attribute C_S_AXI_ACLK_FREQ_HZ : integer;
3623 
  attribute C_S_AXI_ACLK_FREQ_HZ of axi_uartlite_module_sim_axi_uartlite : entity is 100000000;
3624 
  attribute C_S_AXI_ADDR_WIDTH : integer;
3625 
  attribute C_S_AXI_ADDR_WIDTH of axi_uartlite_module_sim_axi_uartlite : entity is 4;
3626 
  attribute C_S_AXI_DATA_WIDTH : integer;
3627 
  attribute C_S_AXI_DATA_WIDTH of axi_uartlite_module_sim_axi_uartlite : entity is 32;
3628 
  attribute C_USE_PARITY : integer;
3629 
  attribute C_USE_PARITY of axi_uartlite_module_sim_axi_uartlite : entity is 0;
3630 
  attribute downgradeipidentifiedwarnings : string;
3631 
  attribute downgradeipidentifiedwarnings of axi_uartlite_module_sim_axi_uartlite : entity is "yes";
3632 
end axi_uartlite_module_sim_axi_uartlite;
3633 
 
3634 
architecture STRUCTURE of axi_uartlite_module_sim_axi_uartlite is
3635 
  signal \<const0>\ : STD_LOGIC;
3636 
  signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
3637 
  signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
3638 
  signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
3639 
  signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
3640 
  signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
3641 
  signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
3642 
  signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
3643 
  signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
3644 
  signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
3645 
  signal \UARTLITE_RX_I/rx_Data_Empty\ : STD_LOGIC;
3646 
  signal \UARTLITE_TX_I/fifo_wr\ : STD_LOGIC;
3647 
  signal bus2ip_rdce : STD_LOGIC_VECTOR ( 1 to 1 );
3648 
  signal bus2ip_reset : STD_LOGIC;
3649 
  signal enable_interrupts : STD_LOGIC;
3650 
  signal reset_RX_FIFO : STD_LOGIC;
3651 
  signal reset_TX_FIFO : STD_LOGIC;
3652 
  signal rx_Buffer_Full : STD_LOGIC;
3653 
  signal rx_Data : STD_LOGIC_VECTOR ( 0 to 7 );
3654 
  signal \^s_axi_awready\ : STD_LOGIC;
3655 
  signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
3656 
  signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
3657 
  signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
3658 
  signal status_reg : STD_LOGIC_VECTOR ( 1 to 2 );
3659 
  signal tx_Buffer_Empty : STD_LOGIC;
3660 
  signal tx_Buffer_Full : STD_LOGIC;
3661 
  attribute max_fanout : string;
3662 
  attribute max_fanout of s_axi_aclk : signal is "10000";
3663 
  attribute max_fanout of s_axi_aresetn : signal is "10000";
3664 
begin
3665 
  s_axi_awready <= \^s_axi_awready\;
3666 
  s_axi_bresp(1) <= \^s_axi_bresp\(1);
3667 
  s_axi_bresp(0) <= \<const0>\;
3668 
  s_axi_rdata(31) <= \<const0>\;
3669 
  s_axi_rdata(30) <= \<const0>\;
3670 
  s_axi_rdata(29) <= \<const0>\;
3671 
  s_axi_rdata(28) <= \<const0>\;
3672 
  s_axi_rdata(27) <= \<const0>\;
3673 
  s_axi_rdata(26) <= \<const0>\;
3674 
  s_axi_rdata(25) <= \<const0>\;
3675 
  s_axi_rdata(24) <= \<const0>\;
3676 
  s_axi_rdata(23) <= \<const0>\;
3677 
  s_axi_rdata(22) <= \<const0>\;
3678 
  s_axi_rdata(21) <= \<const0>\;
3679 
  s_axi_rdata(20) <= \<const0>\;
3680 
  s_axi_rdata(19) <= \<const0>\;
3681 
  s_axi_rdata(18) <= \<const0>\;
3682 
  s_axi_rdata(17) <= \<const0>\;
3683 
  s_axi_rdata(16) <= \<const0>\;
3684 
  s_axi_rdata(15) <= \<const0>\;
3685 
  s_axi_rdata(14) <= \<const0>\;
3686 
  s_axi_rdata(13) <= \<const0>\;
3687 
  s_axi_rdata(12) <= \<const0>\;
3688 
  s_axi_rdata(11) <= \<const0>\;
3689 
  s_axi_rdata(10) <= \<const0>\;
3690 
  s_axi_rdata(9) <= \<const0>\;
3691 
  s_axi_rdata(8) <= \<const0>\;
3692 
  s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
3693 
  s_axi_rresp(1) <= \^s_axi_rresp\(1);
3694 
  s_axi_rresp(0) <= \<const0>\;
3695 
  s_axi_wready <= \^s_axi_awready\;
3696 
AXI_LITE_IPIF_I: entity work.axi_uartlite_module_sim_axi_lite_ipif
3697 
     port map (
3698 
      Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
3699 
      FIFO_Full_reg => AXI_LITE_IPIF_I_n_13,
3700 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
3701 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
3702 
      \INFERRED_GEN.cnt_i_reg[2]\ => AXI_LITE_IPIF_I_n_11,
3703 
      \INFERRED_GEN.cnt_i_reg[2]_0\ => AXI_LITE_IPIF_I_n_16,
3704 
      \INFERRED_GEN.cnt_i_reg[4]\(0) => tx_Buffer_Empty,
3705 
      Q(0) => \UARTLITE_RX_I/rx_Data_Empty\,
3706 
      bus2ip_rdce(0) => bus2ip_rdce(1),
3707 
      bus2ip_reset => bus2ip_reset,
3708 
      enable_interrupts => enable_interrupts,
3709 
      enable_interrupts_reg => AXI_LITE_IPIF_I_n_18,
3710 
      fifo_wr => \UARTLITE_TX_I/fifo_wr\,
3711 
      \out\(7) => rx_Data(0),
3712 
      \out\(6) => rx_Data(1),
3713 
      \out\(5) => rx_Data(2),
3714 
      \out\(4) => rx_Data(3),
3715 
      \out\(3) => rx_Data(4),
3716 
      \out\(2) => rx_Data(5),
3717 
      \out\(1) => rx_Data(6),
3718 
      \out\(0) => rx_Data(7),
3719 
      reset_RX_FIFO => reset_RX_FIFO,
3720 
      reset_TX_FIFO => reset_TX_FIFO,
3721 
      rx_Buffer_Full => rx_Buffer_Full,
3722 
      rx_Data_Present_Pre_reg => AXI_LITE_IPIF_I_n_12,
3723 
      s_axi_aclk => s_axi_aclk,
3724 
      s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
3725 
      s_axi_aresetn => s_axi_aresetn,
3726 
      s_axi_arready => s_axi_arready,
3727 
      s_axi_arvalid => s_axi_arvalid,
3728 
      s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
3729 
      s_axi_awready => \^s_axi_awready\,
3730 
      s_axi_awvalid => s_axi_awvalid,
3731 
      s_axi_bready => s_axi_bready,
3732 
      s_axi_bresp(0) => \^s_axi_bresp\(1),
3733 
      s_axi_bvalid => s_axi_bvalid,
3734 
      s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
3735 
      s_axi_rready => s_axi_rready,
3736 
      s_axi_rresp(0) => \^s_axi_rresp\(1),
3737 
      s_axi_rvalid => s_axi_rvalid,
3738 
      s_axi_wdata(2) => s_axi_wdata(4),
3739 
      s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0),
3740 
      s_axi_wvalid => s_axi_wvalid,
3741 
      status_reg(1) => status_reg(1),
3742 
      status_reg(0) => status_reg(2),
3743 
      tx_Buffer_Empty_Pre_reg => AXI_LITE_IPIF_I_n_17,
3744 
      tx_Buffer_Full => tx_Buffer_Full
3745 
    );
3746 
GND: unisim.vcomponents.GND
3747 
     port map (
3748 
      G => \<const0>\
3749 
    );
3750 
UARTLITE_CORE_I: entity work.axi_uartlite_module_sim_uartlite_core
3751 
     port map (
3752 
      Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
3753 
      Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_11,
3754 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
3755 
      \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_13,
3756 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
3757 
      \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI_LITE_IPIF_I_n_16,
3758 
      \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ => AXI_LITE_IPIF_I_n_18,
3759 
      \INFERRED_GEN.cnt_i_reg[2]\(0) => tx_Buffer_Empty,
3760 
      \INFERRED_GEN.cnt_i_reg[4]\ => AXI_LITE_IPIF_I_n_17,
3761 
      \INFERRED_GEN.cnt_i_reg[4]_0\ => AXI_LITE_IPIF_I_n_12,
3762 
      Q(0) => \UARTLITE_RX_I/rx_Data_Empty\,
3763 
      bus2ip_rdce(0) => bus2ip_rdce(1),
3764 
      bus2ip_reset => bus2ip_reset,
3765 
      enable_interrupts => enable_interrupts,
3766 
      fifo_wr => \UARTLITE_TX_I/fifo_wr\,
3767 
      interrupt => interrupt,
3768 
      \out\(7) => rx_Data(0),
3769 
      \out\(6) => rx_Data(1),
3770 
      \out\(5) => rx_Data(2),
3771 
      \out\(4) => rx_Data(3),
3772 
      \out\(3) => rx_Data(4),
3773 
      \out\(2) => rx_Data(5),
3774 
      \out\(1) => rx_Data(6),
3775 
      \out\(0) => rx_Data(7),
3776 
      reset_RX_FIFO => reset_RX_FIFO,
3777 
      reset_TX_FIFO => reset_TX_FIFO,
3778 
      rx => rx,
3779 
      rx_Buffer_Full => rx_Buffer_Full,
3780 
      s_axi_aclk => s_axi_aclk,
3781 
      s_axi_aresetn => s_axi_aresetn,
3782 
      s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
3783 
      status_reg(1) => status_reg(1),
3784 
      status_reg(0) => status_reg(2),
3785 
      tx => tx,
3786 
      tx_Buffer_Full => tx_Buffer_Full
3787 
    );
3788 
end STRUCTURE;
3789 
library IEEE;
3790 
use IEEE.STD_LOGIC_1164.ALL;
3791 
library UNISIM;
3792 
use UNISIM.VCOMPONENTS.ALL;
3793 
entity axi_uartlite_module_sim is
3794 
  port (
3795 
    s_axi_aclk : in STD_LOGIC;
3796 
    s_axi_aresetn : in STD_LOGIC;
3797 
    interrupt : out STD_LOGIC;
3798 
    s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
3799 
    s_axi_awvalid : in STD_LOGIC;
3800 
    s_axi_awready : out STD_LOGIC;
3801 
    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
3802 
    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
3803 
    s_axi_wvalid : in STD_LOGIC;
3804 
    s_axi_wready : out STD_LOGIC;
3805 
    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
3806 
    s_axi_bvalid : out STD_LOGIC;
3807 
    s_axi_bready : in STD_LOGIC;
3808 
    s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
3809 
    s_axi_arvalid : in STD_LOGIC;
3810 
    s_axi_arready : out STD_LOGIC;
3811 
    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
3812 
    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
3813 
    s_axi_rvalid : out STD_LOGIC;
3814 
    s_axi_rready : in STD_LOGIC;
3815 
    rx : in STD_LOGIC;
3816 
    tx : out STD_LOGIC
3817 
  );
3818 
  attribute NotValidForBitStream : boolean;
3819 
  attribute NotValidForBitStream of axi_uartlite_module_sim : entity is true;
3820 
  attribute CHECK_LICENSE_TYPE : string;
3821 
  attribute CHECK_LICENSE_TYPE of axi_uartlite_module_sim : entity is "axi_uartlite_module,axi_uartlite,{}";
3822 
  attribute downgradeipidentifiedwarnings : string;
3823 
  attribute downgradeipidentifiedwarnings of axi_uartlite_module_sim : entity is "yes";
3824 
  attribute x_core_info : string;
3825 
  attribute x_core_info of axi_uartlite_module_sim : entity is "axi_uartlite,Vivado 2017.4";
3826 
end axi_uartlite_module_sim;
3827 
 
3828 
architecture STRUCTURE of axi_uartlite_module_sim is
3829 
  attribute C_BAUDRATE : integer;
3830 
  attribute C_BAUDRATE of U0 : label is 38400;
3831 
  attribute C_DATA_BITS : integer;
3832 
  attribute C_DATA_BITS of U0 : label is 8;
3833 
  attribute C_FAMILY : string;
3834 
  attribute C_FAMILY of U0 : label is "kintex7";
3835 
  attribute C_ODD_PARITY : integer;
3836 
  attribute C_ODD_PARITY of U0 : label is 0;
3837 
  attribute C_S_AXI_ACLK_FREQ_HZ : integer;
3838 
  attribute C_S_AXI_ACLK_FREQ_HZ of U0 : label is 100000000;
3839 
  attribute C_S_AXI_ADDR_WIDTH : integer;
3840 
  attribute C_S_AXI_ADDR_WIDTH of U0 : label is 4;
3841 
  attribute C_S_AXI_DATA_WIDTH : integer;
3842 
  attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
3843 
  attribute C_USE_PARITY : integer;
3844 
  attribute C_USE_PARITY of U0 : label is 0;
3845 
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
3846 
  attribute x_interface_info : string;
3847 
  attribute x_interface_info of interrupt : signal is "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
3848 
  attribute x_interface_parameter : string;
3849 
  attribute x_interface_parameter of interrupt : signal is "XIL_INTERFACENAME INTERRUPT, SENSITIVITY EDGE_RISING, PortWidth 1";
3850 
  attribute x_interface_info of rx : signal is "xilinx.com:interface:uart:1.0 UART RxD";
3851 
  attribute x_interface_parameter of rx : signal is "XIL_INTERFACENAME UART, BOARD.ASSOCIATED_PARAM UARTLITE_BOARD_INTERFACE";
3852 
  attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 ACLK CLK";
3853 
  attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000";
3854 
  attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 ARESETN RST";
3855 
  attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME ARESETN, POLARITY ACTIVE_LOW";
3856 
  attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
3857 
  attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
3858 
  attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
3859 
  attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
3860 
  attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
3861 
  attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
3862 
  attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
3863 
  attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
3864 
  attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
3865 
  attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
3866 
  attribute x_interface_info of tx : signal is "xilinx.com:interface:uart:1.0 UART TxD";
3867 
  attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
3868 
  attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
3869 
  attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
3870 
  attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
3871 
  attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
3872 
  attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
3873 
  attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
3874 
  attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
3875 
begin
3876 
U0: entity work.axi_uartlite_module_sim_axi_uartlite
3877 
     port map (
3878 
      interrupt => interrupt,
3879 
      rx => rx,
3880 
      s_axi_aclk => s_axi_aclk,
3881 
      s_axi_araddr(3 downto 0) => s_axi_araddr(3 downto 0),
3882 
      s_axi_aresetn => s_axi_aresetn,
3883 
      s_axi_arready => s_axi_arready,
3884 
      s_axi_arvalid => s_axi_arvalid,
3885 
      s_axi_awaddr(3 downto 0) => s_axi_awaddr(3 downto 0),
3886 
      s_axi_awready => s_axi_awready,
3887 
      s_axi_awvalid => s_axi_awvalid,
3888 
      s_axi_bready => s_axi_bready,
3889 
      s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
3890 
      s_axi_bvalid => s_axi_bvalid,
3891 
      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
3892 
      s_axi_rready => s_axi_rready,
3893 
      s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
3894 
      s_axi_rvalid => s_axi_rvalid,
3895 
      s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
3896 
      s_axi_wready => s_axi_wready,
3897 
      s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
3898 
      s_axi_wvalid => s_axi_wvalid,
3899 
      tx => tx
3900 
    );
3901 
end STRUCTURE;

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