URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [clk_gen/] [clk_gen.xci] - Blame information for rev 2

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  xilinx.com
  xci
  unknown
  1.0
  
    
      clk_gen
      
      
        false
        100000000
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        0000
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        Input Clock   Freq (MHz)    Input Jitter (UI)
        __primary_________200.000____________0.010
        no_secondary_input_clock 
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        Units_MHz
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        1
         Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
          Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
        clk_out1___100.000______0.000______50.0______112.316_____89.971
        no_CLK_OUT2_output
        no_CLK_OUT3_output
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        0
        0
        WAVEFORM
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        false
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        1
        0.000
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        0.000
        CLKFBOUT
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        1
        No notes
        0.010
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        1
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        200.000
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        100.0
        0
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        100.000
        0.010
        10.000
        clk_in2
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        4000
        0.004
        STATUS
        11
        32
        100.0
        100.0
        100.0
        100.0
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        0
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        1
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        50.0
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        100.0
        0.010
        BUFG
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        0.0
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        0.0
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        0.0
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        0.000
        1
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        0.0
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        0.0
        50.000
        100.000
        0.000
        1
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        600.000
        sys_diff_clock
        Custom
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        false
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        false
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        false
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        false
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        false
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        false
        CLK_VALID
        auto
        clk_gen
        daddr
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        den
        Custom
        Custom
        din
        dout
        drdy
        dwe
        false
        false
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        FDBK_AUTO
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        locked
        OPTIMIZED
        5.000
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        1
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        0.000
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        1
        0.500
        0.000
        false
        false
        ZHOLD
        1
        None
        0.010
        0.010
        false
        1
        false
        false
        WAVEFORM
        false
        UNKNOWN
        OPTIMIZED
        4
        0.000
        10.000
        1
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        0.000
        1
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        0.000
        1
        0.500
        0.000
        1
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        0.000
        1
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        0.000
        1
        0.500
        0.000
        CLKFBOUT
        SYSTEM_SYNCHRONOUS
        1
        None
        0.010
        power_down
        1
        clk_in1
        MMCM
        mmcm_adv
        200.000
        0.010
        10.000
        Differential_clock_capable_pin
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        psdone
        psen
        psincdec
        100.0
        REL_PRIMARY
        Custom
        reset
        ACTIVE_HIGH
        100.000
        0.010
        10.000
        clk_in2
        Single_ended_clock_capable_pin
        CENTER_HIGH
        250
        0.004
        STATUS
        empty
        100.0
        100.0
        100.0
        100.0
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        false
        false
        false
        false
        false
        false
        true
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        false
        true
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        false
        false
        true
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        true
        false
        false
        false
        kintex7
        xilinx.com:kc705:part0:1.5
        xc7k325t
        ffg900
        VERILOG
        
        MIXED
        -2
        
        TRUE
        TRUE
        IP_Flow
        3
        TRUE
        .
        
        .
        2017.4
        OUT_OF_CONTEXT
      
      
        
          
            
            
            
            
            
            
            
            
            
            
          
        
      
    
  


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Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [clk_gen/] [clk_gen.xci] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	vv_gulyaev
2
3			`xilinx.com`
4			`xci`
5			`unknown`
6			`1.0`
7
8
9			`clk_gen`
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67			`cddcreq`
68			`0000`
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70			`clkfb_in_n`
71			`clkfb_in`
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161			`50.000`
162			`false`
163			`100.000`
164			`0.000`
165			`50.000`
166			`100.000`
167			`0.000`
168			`1`
169			`0`
170			`VCO`
171			`clk_in_sel`
172			`clk_out1`
173			`clk_out2`
174			`clk_out3`
175			`clk_out4`
176			`clk_out5`
177			`clk_out6`
178			`clk_out7`
179			`CLK_VALID`
180			`NA`
181			`daddr`
182			`dclk`
183			`den`
184			`din`
185			`0000`
186			`1`
187			`1.0`
188			`1.0`
189			`1.0`
190			`1.0`
191			`1.0`
192			`1.0`
193			`dout`
194			`drdy`
195			`dwe`
196			`0`
197			`0`
198			`0`
199			`0`
200			`0`
201			`0`
202			`0`
203			`0`
204			`FDBK_AUTO`
205			`0000`
206			`0000`
207			`0`
208			`Input Clock Freq (MHz) Input Jitter (UI)`
209			`__primary_________200.000____________0.010`
210			`no_secondary_input_clock`
211			`input_clk_stopped`
212			`0`
213			`Units_MHz`
214			`No_Jitter`
215			`locked`
216			`0000`
217			`0000`
218			`0000`
219			`false`
220			`false`
221			`false`
222			`false`
223			`false`
224			`false`
225			`false`
226			`false`
227			`OPTIMIZED`
228			`5.000`
229			`0.000`
230			`FALSE`
231			`5.000`
232			`10.0`
233			`10.000`
234			`0.500`
235			`0.000`
236			`FALSE`
237			`1`
238			`0.500`
239			`0.000`
240			`FALSE`
241			`1`
242			`0.500`
243			`0.000`
244			`FALSE`
245			`1`
246			`0.500`
247			`0.000`
248			`FALSE`
249			`FALSE`
250			`1`
251			`0.500`
252			`0.000`
253			`FALSE`
254			`1`
255			`0.500`
256			`0.000`
257			`FALSE`
258			`1`
259			`0.500`
260			`0.000`
261			`FALSE`
262			`FALSE`
263			`ZHOLD`
264			`1`
265			`None`
266			`0.010`
267			`0.010`
268			`FALSE`
269			`1`
270			`Output Output Phase Duty Cycle Pk-to-Pk Phase`
271			`Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)`
272			`clk_out1___100.000______0.000______50.0______112.316_____89.971`
273			`no_CLK_OUT2_output`
274			`no_CLK_OUT3_output`
275			`no_CLK_OUT4_output`
276			`no_CLK_OUT5_output`
277			`no_CLK_OUT6_output`
278			`no_CLK_OUT7_output`
279			`0`
280			`0`
281			`WAVEFORM`
282			`UNKNOWN`
283			`false`
284			`false`
285			`false`
286			`false`
287			`false`
288			`OPTIMIZED`
289			`1`
290			`0.000`
291			`1.000`
292			`1`
293			`0.500`
294			`0.000`
295			`1`
296			`0.500`
297			`0.000`
298			`1`
299			`0.500`
300			`0.000`
301			`1`
302			`0.500`
303			`0.000`
304			`1`
305			`0.500`
306			`0.000`
307			`1`
308			`0.500`
309			`0.000`
310			`CLKFBOUT`
311			`SYSTEM_SYNCHRONOUS`
312			`1`
313			`No notes`
314			`0.010`
315			`power_down`
316			`0000`
317			`1`
318			`clk_in1`
319			`MMCM`
320			`AUTO`
321			`200.000`
322			`0.010`
323			`10.000`
324			`Differential_clock_capable_pin`
325			`psclk`
326			`psdone`
327			`psen`
328			`psincdec`
329			`100.0`
330			`0`
331			`reset`
332			`100.000`
333			`0.010`
334			`10.000`
335			`clk_in2`
336			`Single_ended_clock_capable_pin`
337			`CENTER_HIGH`
338			`4000`
339			`0.004`
340			`STATUS`
341			`11`
342			`32`
343			`100.0`
344			`100.0`
345			`100.0`
346			`100.0`
347			`0`
348			`0`
349			`0`
350			`0`
351			`0`
352			`0`
353			`0`
354			`0`
355			`0`
356			`0`
357			`0`
358			`1`
359			`0`
360			`0`
361			`1`
362			`0`
363			`0`
364			`0`
365			`1`
366			`0`
367			`1`
368			`0`
369			`0`
370			`0`
371			`clk_gen`
372			`MMCM`
373			`false`
374			`empty`
375			`cddcdone`
376			`cddcreq`
377			`clkfb_in_n`
378			`clkfb_in`
379			`clkfb_in_p`
380			`SINGLE`
381			`clkfb_out_n`
382			`clkfb_out`
383			`clkfb_out_p`
384			`clkfb_stopped`
385			`50.0`
386			`0.010`
387			`100.0`
388			`0.010`
389			`BUFG`
390			`112.316`
391			`false`
392			`89.971`
393			`50.000`
394			`100.000`
395			`0.000`
396			`1`
397			`true`
398			`BUFG`
399			`0.0`
400			`false`
401			`0.0`
402			`50.000`
403			`100.000`
404			`0.000`
405			`1`
406			`false`
407			`BUFG`
408			`0.0`
409			`false`
410			`0.0`
411			`50.000`
412			`100.000`
413			`0.000`
414			`1`
415			`false`
416			`BUFG`
417			`0.0`
418			`false`
419			`0.0`
420			`50.000`
421			`100.000`
422			`0.000`
423			`1`
424			`false`
425			`BUFG`
426			`0.0`
427			`false`
428			`0.0`
429			`50.000`
430			`100.000`
431			`0.000`
432			`1`
433			`false`
434			`BUFG`
435			`0.0`
436			`false`
437			`0.0`
438			`50.000`
439			`100.000`
440			`0.000`
441			`1`
442			`false`
443			`BUFG`
444			`0.0`
445			`false`
446			`0.0`
447			`50.000`
448			`100.000`
449			`0.000`
450			`1`
451			`false`
452			`600.000`
453			`sys_diff_clock`
454			`Custom`
455			`clk_in_sel`
456			`clk_out1`
457			`false`
458			`clk_out2`
459			`false`
460			`clk_out3`
461			`false`
462			`clk_out4`
463			`false`
464			`clk_out5`
465			`false`
466			`clk_out6`
467			`false`
468			`clk_out7`
469			`false`
470			`CLK_VALID`
471			`auto`
472			`clk_gen`
473			`daddr`
474			`dclk`
475			`den`
476			`Custom`
477			`Custom`
478			`din`
479			`dout`
480			`drdy`
481			`dwe`
482			`false`
483			`false`
484			`false`
485			`false`
486			`false`
487			`false`
488			`false`
489			`false`
490			`false`
491			`FDBK_AUTO`
492			`input_clk_stopped`
493			`frequency`
494			`Enable_AXI`
495			`Units_MHz`
496			`Units_UI`
497			`UI`
498			`No_Jitter`
499			`locked`
500			`OPTIMIZED`
501			`5.000`
502			`0.000`
503			`false`
504			`5.000`
505			`10.0`
506			`10.000`
507			`0.500`
508			`0.000`
509			`false`
510			`1`
511			`0.500`
512			`0.000`
513			`false`
514			`1`
515			`0.500`
516			`0.000`
517			`false`
518			`1`
519			`0.500`
520			`0.000`
521			`false`
522			`false`
523			`1`
524			`0.500`
525			`0.000`
526			`false`
527			`1`
528			`0.500`
529			`0.000`
530			`false`
531			`1`
532			`0.500`
533			`0.000`
534			`false`
535			`false`
536			`ZHOLD`
537			`1`
538			`None`
539			`0.010`
540			`0.010`
541			`false`
542			`1`
543			`false`
544			`false`
545			`WAVEFORM`
546			`false`
547			`UNKNOWN`
548			`OPTIMIZED`
549			`4`
550			`0.000`
551			`10.000`
552			`1`
553			`0.500`
554			`0.000`
555			`1`
556			`0.500`
557			`0.000`
558			`1`
559			`0.500`
560			`0.000`
561			`1`
562			`0.500`
563			`0.000`
564			`1`
565			`0.500`
566			`0.000`
567			`1`
568			`0.500`
569			`0.000`
570			`CLKFBOUT`
571			`SYSTEM_SYNCHRONOUS`
572			`1`
573			`None`
574			`0.010`
575			`power_down`
576			`1`
577			`clk_in1`
578			`MMCM`
579			`mmcm_adv`
580			`200.000`
581			`0.010`
582			`10.000`
583			`Differential_clock_capable_pin`
584			`psclk`
585			`psdone`
586			`psen`
587			`psincdec`
588			`100.0`
589			`REL_PRIMARY`
590			`Custom`
591			`reset`
592			`ACTIVE_HIGH`
593			`100.000`
594			`0.010`
595			`10.000`
596			`clk_in2`
597			`Single_ended_clock_capable_pin`
598			`CENTER_HIGH`
599			`250`
600			`0.004`
601			`STATUS`
602			`empty`
603			`100.0`
604			`100.0`
605			`100.0`
606			`100.0`
607			`false`
608			`false`
609			`false`
610			`false`
611			`false`
612			`false`
613			`false`
614			`true`
615			`false`
616			`false`
617			`true`
618			`false`
619			`false`
620			`false`
621			`true`
622			`false`
623			`true`
624			`false`
625			`false`
626			`false`
627			`kintex7`
628			`xilinx.com:kc705:part0:1.5`
629			`xc7k325t`
630			`ffg900`
631			`VERILOG`
632
633			`MIXED`
634			`-2`
635
636			`TRUE`
637			`TRUE`
638			`IP_Flow`
639			`3`
640			`TRUE`
641			`.`
642
643			`.`
644			`2017.4`
645			`OUT_OF_CONTEXT`
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665