OpenCores
URL https://opencores.org/ocsvn/aes-128-ecb-encoder/aes-128-ecb-encoder/trunk

Subversion Repositories aes-128-ecb-encoder

[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.srcs/] [sources_1/] [ip/] [clk_gen/] [clk_gen.xml] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev
2
3 
  xilinx.com
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  customized_ip
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  clk_gen
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  1.0
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      s_axi_lite
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      S_AXI_LITE
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            ARADDR
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            s_axi_araddr
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            ARREADY
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            s_axi_arready
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            ARVALID
34
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            s_axi_arvalid
37
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            AWADDR
42
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            s_axi_awaddr
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            AWREADY
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            s_axi_awready
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            AWVALID
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            s_axi_awvalid
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            BREADY
66
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            s_axi_bready
69
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            BRESP
74
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            s_axi_bresp
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            BVALID
82
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            s_axi_bvalid
85
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            RDATA
90
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            s_axi_rdata
93
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            RREADY
98
99
100 
            s_axi_rready
101
102
103
104
105 
            RRESP
106
107
108 
            s_axi_rresp
109
110
111
112
113 
            RVALID
114
115
116 
            s_axi_rvalid
117
118
119
120
121 
            WDATA
122
123
124 
            s_axi_wdata
125
126
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128
129 
            WREADY
130
131
132 
            s_axi_wready
133
134
135
136
137 
            WSTRB
138
139
140 
            s_axi_wstrb
141
142
143
144
145 
            WVALID
146
147
148 
            s_axi_wvalid
149
150
151
152
153
154 
          DATA_WIDTH
155 
          1
156
157
158 
              none
159
160
161
162
163 
          PROTOCOL
164 
          AXI4LITE
165
166
167 
              none
168
169
170
171
172 
          FREQ_HZ
173 
          100000000
174
175
176 
              none
177
178
179
180
181 
          ID_WIDTH
182 
          0
183
184
185 
              none
186
187
188
189
190 
          ADDR_WIDTH
191 
          1
192
193
194 
              none
195
196
197
198
199 
          AWUSER_WIDTH
200 
          0
201
202
203 
              none
204
205
206
207
208 
          ARUSER_WIDTH
209 
          0
210
211
212 
              none
213
214
215
216
217 
          WUSER_WIDTH
218 
          0
219
220
221 
              none
222
223
224
225
226 
          RUSER_WIDTH
227 
          0
228
229
230 
              none
231
232
233
234
235 
          BUSER_WIDTH
236 
          0
237
238
239 
              none
240
241
242
243
244 
          READ_WRITE_MODE
245 
          READ_WRITE
246
247
248 
              none
249
250
251
252
253 
          HAS_BURST
254 
          0
255
256
257 
              none
258
259
260
261
262 
          HAS_LOCK
263 
          0
264
265
266 
              none
267
268
269
270
271 
          HAS_PROT
272 
          0
273
274
275 
              none
276
277
278
279
280 
          HAS_CACHE
281 
          0
282
283
284 
              none
285
286
287
288
289 
          HAS_QOS
290 
          0
291
292
293 
              none
294
295
296
297
298 
          HAS_REGION
299 
          0
300
301
302 
              none
303
304
305
306
307 
          HAS_WSTRB
308 
          0
309
310
311 
              none
312
313
314
315
316 
          HAS_BRESP
317 
          0
318
319
320 
              none
321
322
323
324
325 
          HAS_RRESP
326 
          0
327
328
329 
              none
330
331
332
333
334 
          SUPPORTS_NARROW_BURST
335 
          0
336
337
338 
              none
339
340
341
342
343 
          NUM_READ_OUTSTANDING
344 
          1
345
346
347 
              none
348
349
350
351
352 
          NUM_WRITE_OUTSTANDING
353 
          1
354
355
356 
              none
357
358
359
360
361 
          MAX_BURST_LENGTH
362 
          1
363
364
365 
              none
366
367
368
369
370 
          PHASE
371 
          0.000
372
373
374 
              none
375
376
377
378
379 
          CLK_DOMAIN
380
381
382
383 
              none
384
385
386
387
388 
          NUM_READ_THREADS
389 
          1
390
391
392 
              none
393
394
395
396
397 
          NUM_WRITE_THREADS
398 
          1
399
400
401 
              none
402
403
404
405
406 
          RUSER_BITS_PER_BYTE
407 
          0
408
409
410 
              none
411
412
413
414
415 
          WUSER_BITS_PER_BYTE
416 
          0
417
418
419 
              none
420
421
422
423
424
425
426
427 
            false
428
429
430
431
432
433 
      s_axi_aclk
434 
      s_axi_aclk
435
436
437
438
439
440
441 
            CLK
442
443
444 
            s_axi_aclk
445
446
447
448
449
450 
          ASSOCIATED_BUSIF
451 
          s_axi_lite
452
453
454 
          ASSOCIATED_RESET
455 
          aresetn
456
457
458 
          FREQ_HZ
459 
          100000000
460
461
462 
              none
463
464
465
466
467 
          PHASE
468 
          0.000
469
470
471 
              none
472
473
474
475
476 
          CLK_DOMAIN
477
478
479
480 
              none
481
482
483
484
485
486
487
488 
            false
489
490
491
492
493
494 
      ref_clk
495 
      ref_clk
496
497
498
499
500
501
502 
            CLK
503
504
505 
            ref_clk
506
507
508
509
510
511 
          FREQ_HZ
512 
          100000000
513
514
515 
              none
516
517
518
519
520 
          PHASE
521 
          0.000
522
523
524 
              none
525
526
527
528
529 
          CLK_DOMAIN
530
531
532
533 
              none
534
535
536
537
538 
          ASSOCIATED_BUSIF
539
540
541
542 
              none
543
544
545
546
547 
          ASSOCIATED_RESET
548
549
550
551 
              none
552
553
554
555
556
557
558
559 
            false
560
561
562
563
564
565 
      s_axi_resetn
566 
      S_AXI_RESETN
567
568
569
570
571
572
573 
            RST
574
575
576 
            s_axi_aresetn
577
578
579
580
581
582 
          ASSOCIATED_RESET
583 
          aresetn
584
585
586 
          POLARITY
587 
          ACTIVE_LOW
588
589
590
591
592
593 
            false
594
595
596
597
598
599 
      intr
600 
      Intr
601
602
603
604
605
606
607 
            INTERRUPT
608
609
610 
            ip2intc_irpt
611
612
613
614
615
616 
          SENSITIVITY
617 
          LEVEL_HIGH
618
619
620 
              none
621
622
623
624
625 
          PortWidth
626 
          1
627
628
629 
              none
630
631
632
633
634
635
636
637 
            false
638
639
640
641
642
643 
      CLK_IN1_D
644 
      CLK_IN1_D
645 
      Differential Clock input
646
647
648
649
650
651
652 
            CLK_N
653
654
655 
            clk_in1_n
656
657
658
659
660 
            CLK_P
661
662
663 
            clk_in1_p
664
665
666
667
668
669 
          BOARD.ASSOCIATED_PARAM
670 
          CLK_IN1_BOARD_INTERFACE
671
672
673
674 
                required
675
676
677
678
679
680 
          CAN_DEBUG
681 
          false
682
683
684 
              none
685
686
687
688
689 
          FREQ_HZ
690 
          100000000
691
692
693 
              none
694
695
696
697
698
699
700
701 
            true
702
703
704
705
706
707 
      CLK_IN2_D
708 
      CLK_IN2_D
709 
      Differential Clock input
710
711
712
713
714
715
716 
            CLK_N
717
718
719 
            clk_in2_n
720
721
722
723
724 
            CLK_P
725
726
727 
            clk_in2_p
728
729
730
731
732
733 
          BOARD.ASSOCIATED_PARAM
734 
          CLK_IN2_BOARD_INTERFACE
735
736
737
738 
                required
739
740
741
742
743
744 
          CAN_DEBUG
745 
          false
746
747
748 
              none
749
750
751
752
753 
          FREQ_HZ
754 
          100000000
755
756
757 
              none
758
759
760
761
762
763
764
765 
            false
766
767
768
769
770
771 
      CLKFB_IN_D
772 
      CLKFB_IN_D
773 
      Differential Feedback Clock input
774
775
776
777
778
779
780 
            CLK_N
781
782
783 
            clkfb_in_n
784
785
786
787
788 
            CLK_P
789
790
791 
            clkfb_in_p
792
793
794
795
796
797 
          CAN_DEBUG
798 
          false
799
800
801 
              none
802
803
804
805
806 
          FREQ_HZ
807 
          100000000
808
809
810 
              none
811
812
813
814
815
816
817
818 
            false
819
820
821
822
823
824 
      CLKFB_OUT_D
825 
      CLKFB_OUT_D
826 
      Differential Feeback Clock Output
827
828
829
830
831
832
833 
            CLK_N
834
835
836 
            clkfb_out_n
837
838
839
840
841 
            CLK_P
842
843
844 
            clkfb_out_p
845
846
847
848
849
850 
          CAN_DEBUG
851 
          false
852
853
854 
              none
855
856
857
858
859 
          FREQ_HZ
860 
          100000000
861
862
863 
              none
864
865
866
867
868
869
870
871 
            false
872
873
874
875
876
877 
      reset
878 
      reset
879
880
881
882
883
884
885 
            RST
886
887
888 
            reset
889
890
891
892
893
894 
          POLARITY
895 
          ACTIVE_HIGH
896
897
898 
          BOARD.ASSOCIATED_PARAM
899 
          RESET_BOARD_INTERFACE
900
901
902
903
904
905 
            true
906
907
908
909
910
911 
      resetn
912 
      resetn
913
914
915
916
917
918
919 
            RST
920
921
922 
            resetn
923
924
925
926
927
928 
          POLARITY
929 
          ACTIVE_LOW
930
931
932 
          BOARD.ASSOCIATED_PARAM
933 
          RESET_BOARD_INTERFACE
934
935
936
937
938
939 
            false
940
941
942
943
944
945 
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946
947
948
949
950
951
952 
            CLK_OUT1
953
954
955 
            clk_out1
956
957
958
959
960
961 
          FREQ_HZ
962 
          100000000
963
964
965 
              none
966
967
968
969
970 
          PHASE
971 
          0.000
972
973
974 
              none
975
976
977
978
979 
          CLK_DOMAIN
980
981
982
983 
              none
984
985
986
987
988 
          ASSOCIATED_BUSIF
989
990
991
992 
              none
993
994
995
996
997 
          ASSOCIATED_RESET
998
999
1000
1001 
              none
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011 
        xilinx_elaborateports
1012 
        Elaborate Ports
1013 
        :vivado.xilinx.com:elaborate.ports
1014
1015
1016 
            outputProductCRC
1017 
            7:439537f4
1018
1019
1020
1021
1022 
        xilinx_veriloginstantiationtemplate
1023 
        Verilog Instantiation Template
1024 
        verilogSource:vivado.xilinx.com:synthesis.template
1025 
        verilog
1026
1027 
          xilinx_veriloginstantiationtemplate_view_fileset
1028
1029
1030
1031 
            GENtimestamp
1032 
            Thu Jul 23 06:42:01 UTC 2020
1033
1034
1035 
            outputProductCRC
1036 
            7:315bff31
1037
1038
1039
1040
1041 
        xilinx_anylanguagesynthesis
1042 
        Synthesis
1043 
        :vivado.xilinx.com:synthesis
1044
1045 
          xilinx_anylanguagesynthesis_view_fileset
1046
1047
1048
1049 
            GENtimestamp
1050 
            Thu Jul 23 06:42:09 UTC 2020
1051
1052
1053 
            outputProductCRC
1054 
            7:315bff31
1055
1056
1057
1058
1059 
        xilinx_anylanguagesynthesiswrapper
1060 
        Synthesis Wrapper
1061 
        :vivado.xilinx.com:synthesis.wrapper
1062
1063 
          xilinx_anylanguagesynthesiswrapper_view_fileset
1064
1065
1066
1067 
            GENtimestamp
1068 
            Thu Jul 23 06:42:09 UTC 2020
1069
1070
1071 
            outputProductCRC
1072 
            7:315bff31
1073
1074
1075
1076
1077 
        xilinx_anylanguagebehavioralsimulation
1078 
        Simulation
1079 
        :vivado.xilinx.com:simulation
1080
1081 
          xilinx_anylanguagebehavioralsimulation_view_fileset
1082
1083
1084
1085 
            GENtimestamp
1086 
            Thu Jul 23 06:42:09 UTC 2020
1087
1088
1089 
            outputProductCRC
1090 
            7:ffbdd639
1091
1092
1093
1094
1095 
        xilinx_anylanguagesimulationwrapper
1096 
        Simulation Wrapper
1097 
        :vivado.xilinx.com:simulation.wrapper
1098
1099 
          xilinx_anylanguagesimulationwrapper_view_fileset
1100
1101
1102
1103 
            GENtimestamp
1104 
            Thu Jul 23 06:42:09 UTC 2020
1105
1106
1107 
            outputProductCRC
1108 
            7:ffbdd639
1109
1110
1111
1112
1113 
        xilinx_implementation
1114 
        Implementation
1115 
        :vivado.xilinx.com:implementation
1116
1117 
          xilinx_implementation_view_fileset
1118
1119
1120
1121 
            GENtimestamp
1122 
            Thu Jul 23 06:42:10 UTC 2020
1123
1124
1125 
            outputProductCRC
1126 
            7:315bff31
1127
1128
1129
1130
1131 
        xilinx_versioninformation
1132 
        Version Information
1133 
        :vivado.xilinx.com:docs.versioninfo
1134
1135 
          xilinx_versioninformation_view_fileset
1136
1137
1138
1139 
            GENtimestamp
1140 
            Thu Jul 23 06:42:10 UTC 2020
1141
1142
1143 
            outputProductCRC
1144 
            7:315bff31
1145
1146
1147
1148
1149 
        xilinx_externalfiles
1150 
        External Files
1151 
        :vivado.xilinx.com:external.files
1152
1153 
          xilinx_externalfiles_view_fileset
1154
1155
1156
1157 
            GENtimestamp
1158 
            Wed Jul 29 12:22:05 UTC 2020
1159
1160
1161 
            outputProductCRC
1162 
            7:315bff31
1163
1164
1165
1166
1167
1168
1169 
        s_axi_aclk
1170
1171 
          in
1172
1173
1174 
              std_logic
1175 
              xilinx_anylanguagesynthesis
1176 
              xilinx_anylanguagebehavioralsimulation
1177
1178
1179
1180 
            0
1181
1182
1183
1184
1185
1186 
              false
1187
1188
1189
1190
1191
1192 
        s_axi_aresetn
1193
1194 
          in
1195
1196
1197 
              std_logic
1198 
              xilinx_anylanguagesynthesis
1199 
              xilinx_anylanguagebehavioralsimulation
1200
1201
1202
1203 
            0
1204
1205
1206
1207
1208
1209 
              false
1210
1211
1212
1213
1214
1215 
        s_axi_awaddr
1216
1217 
          in
1218
1219 
            10
1220 
            0
1221
1222
1223
1224 
              std_logic_vector
1225 
              xilinx_anylanguagesynthesis
1226 
              xilinx_anylanguagebehavioralsimulation
1227
1228
1229
1230 
            0
1231
1232
1233
1234
1235
1236 
              false
1237
1238
1239
1240
1241
1242 
        s_axi_awvalid
1243
1244 
          in
1245
1246
1247 
              std_logic
1248 
              xilinx_anylanguagesynthesis
1249 
              xilinx_anylanguagebehavioralsimulation
1250
1251
1252
1253 
            0
1254
1255
1256
1257
1258
1259 
              false
1260
1261
1262
1263
1264
1265 
        s_axi_awready
1266
1267 
          out
1268
1269
1270 
              std_logic
1271 
              xilinx_anylanguagesynthesis
1272 
              xilinx_anylanguagebehavioralsimulation
1273
1274
1275
1276
1277
1278
1279 
              false
1280
1281
1282
1283
1284
1285 
        s_axi_wdata
1286
1287 
          in
1288
1289 
            31
1290 
            0
1291
1292
1293
1294 
              std_logic_vector
1295 
              xilinx_anylanguagesynthesis
1296 
              xilinx_anylanguagebehavioralsimulation
1297
1298
1299
1300 
            0
1301
1302
1303
1304
1305
1306 
              false
1307
1308
1309
1310
1311
1312 
        s_axi_wstrb
1313
1314 
          in
1315
1316 
            3
1317 
            0
1318
1319
1320
1321 
              std_logic_vector
1322 
              xilinx_anylanguagesynthesis
1323 
              xilinx_anylanguagebehavioralsimulation
1324
1325
1326
1327 
            0
1328
1329
1330
1331
1332
1333 
              false
1334
1335
1336
1337
1338
1339 
        s_axi_wvalid
1340
1341 
          in
1342
1343
1344 
              std_logic
1345 
              xilinx_anylanguagesynthesis
1346 
              xilinx_anylanguagebehavioralsimulation
1347
1348
1349
1350 
            0
1351
1352
1353
1354
1355
1356 
              false
1357
1358
1359
1360
1361
1362 
        s_axi_wready
1363
1364 
          out
1365
1366
1367 
              std_logic
1368 
              xilinx_anylanguagesynthesis
1369 
              xilinx_anylanguagebehavioralsimulation
1370
1371
1372
1373
1374
1375
1376 
              false
1377
1378
1379
1380
1381
1382 
        s_axi_bresp
1383
1384 
          out
1385
1386 
            1
1387 
            0
1388
1389
1390
1391 
              std_logic_vector
1392 
              xilinx_anylanguagesynthesis
1393 
              xilinx_anylanguagebehavioralsimulation
1394
1395
1396
1397
1398
1399
1400 
              false
1401
1402
1403
1404
1405
1406 
        s_axi_bvalid
1407
1408 
          out
1409
1410
1411 
              std_logic
1412 
              xilinx_anylanguagesynthesis
1413 
              xilinx_anylanguagebehavioralsimulation
1414
1415
1416
1417
1418
1419
1420 
              false
1421
1422
1423
1424
1425
1426 
        s_axi_bready
1427
1428 
          in
1429
1430
1431 
              std_logic
1432 
              xilinx_anylanguagesynthesis
1433 
              xilinx_anylanguagebehavioralsimulation
1434
1435
1436
1437 
            0
1438
1439
1440
1441
1442
1443 
              false
1444
1445
1446
1447
1448
1449 
        s_axi_araddr
1450
1451 
          in
1452
1453 
            10
1454 
            0
1455
1456
1457
1458 
              std_logic_vector
1459 
              xilinx_anylanguagesynthesis
1460 
              xilinx_anylanguagebehavioralsimulation
1461
1462
1463
1464 
            0
1465
1466
1467
1468
1469
1470 
              false
1471
1472
1473
1474
1475
1476 
        s_axi_arvalid
1477
1478 
          in
1479
1480
1481 
              std_logic
1482 
              xilinx_anylanguagesynthesis
1483 
              xilinx_anylanguagebehavioralsimulation
1484
1485
1486
1487 
            0
1488
1489
1490
1491
1492
1493 
              false
1494
1495
1496
1497
1498
1499 
        s_axi_arready
1500
1501 
          out
1502
1503
1504 
              std_logic
1505 
              xilinx_anylanguagesynthesis
1506 
              xilinx_anylanguagebehavioralsimulation
1507
1508
1509
1510
1511
1512
1513 
              false
1514
1515
1516
1517
1518
1519 
        s_axi_rdata
1520
1521 
          out
1522
1523 
            31
1524 
            0
1525
1526
1527
1528 
              std_logic_vector
1529 
              xilinx_anylanguagesynthesis
1530 
              xilinx_anylanguagebehavioralsimulation
1531
1532
1533
1534
1535
1536
1537 
              false
1538
1539
1540
1541
1542
1543 
        s_axi_rresp
1544
1545 
          out
1546
1547 
            1
1548 
            0
1549
1550
1551
1552 
              std_logic_vector
1553 
              xilinx_anylanguagesynthesis
1554 
              xilinx_anylanguagebehavioralsimulation
1555
1556
1557
1558
1559
1560
1561 
              false
1562
1563
1564
1565
1566
1567 
        s_axi_rvalid
1568
1569 
          out
1570
1571
1572 
              std_logic
1573 
              xilinx_anylanguagesynthesis
1574 
              xilinx_anylanguagebehavioralsimulation
1575
1576
1577
1578
1579
1580
1581 
              false
1582
1583
1584
1585
1586
1587 
        s_axi_rready
1588
1589 
          in
1590
1591
1592 
              std_logic
1593 
              xilinx_anylanguagesynthesis
1594 
              xilinx_anylanguagebehavioralsimulation
1595
1596
1597
1598 
            0
1599
1600
1601
1602
1603
1604 
              false
1605
1606
1607
1608
1609
1610 
        clk_in1_p
1611
1612 
          in
1613
1614
1615 
              std_logic
1616 
              xilinx_anylanguagesynthesis
1617 
              xilinx_anylanguagebehavioralsimulation
1618
1619
1620
1621 
            0
1622
1623
1624
1625
1626
1627 
              true
1628
1629
1630
1631
1632
1633 
        clk_in1_n
1634
1635 
          in
1636
1637
1638 
              std_logic
1639 
              xilinx_anylanguagesynthesis
1640 
              xilinx_anylanguagebehavioralsimulation
1641
1642
1643
1644 
            0
1645
1646
1647
1648
1649
1650 
              true
1651
1652
1653
1654
1655
1656 
        clk_in2_p
1657
1658 
          in
1659
1660
1661 
              std_logic
1662 
              xilinx_anylanguagesynthesis
1663 
              xilinx_anylanguagebehavioralsimulation
1664
1665
1666
1667 
            0
1668
1669
1670
1671
1672
1673 
              false
1674
1675
1676
1677
1678
1679 
        clk_in2_n
1680
1681 
          in
1682
1683
1684 
              std_logic
1685 
              xilinx_anylanguagesynthesis
1686 
              xilinx_anylanguagebehavioralsimulation
1687
1688
1689
1690 
            0
1691
1692
1693
1694
1695
1696 
              false
1697
1698
1699
1700
1701
1702 
        clkfb_in_p
1703
1704 
          in
1705
1706
1707 
              std_logic
1708 
              xilinx_anylanguagesynthesis
1709 
              xilinx_anylanguagebehavioralsimulation
1710
1711
1712
1713 
            0
1714
1715
1716
1717
1718
1719 
              false
1720
1721
1722
1723
1724
1725 
        clkfb_in_n
1726
1727 
          in
1728
1729
1730 
              std_logic
1731 
              xilinx_anylanguagesynthesis
1732 
              xilinx_anylanguagebehavioralsimulation
1733
1734
1735
1736 
            0
1737
1738
1739
1740
1741
1742 
              false
1743
1744
1745
1746
1747
1748 
        clkfb_out_p
1749
1750 
          out
1751
1752
1753 
              std_logic
1754 
              xilinx_anylanguagesynthesis
1755 
              xilinx_anylanguagebehavioralsimulation
1756
1757
1758
1759
1760
1761
1762 
              false
1763
1764
1765
1766
1767
1768 
        clkfb_out_n
1769
1770 
          out
1771
1772
1773 
              std_logic
1774 
              xilinx_anylanguagesynthesis
1775 
              xilinx_anylanguagebehavioralsimulation
1776
1777
1778
1779
1780
1781
1782 
              false
1783
1784
1785
1786
1787
1788 
        reset
1789
1790 
          in
1791
1792
1793 
              std_logic
1794 
              xilinx_anylanguagesynthesis
1795 
              xilinx_anylanguagebehavioralsimulation
1796
1797
1798
1799 
            0
1800
1801
1802
1803
1804
1805 
              true
1806
1807
1808
1809
1810
1811 
        resetn
1812
1813 
          in
1814
1815
1816 
              std_logic
1817 
              xilinx_anylanguagesynthesis
1818 
              xilinx_anylanguagebehavioralsimulation
1819
1820
1821
1822 
            0
1823
1824
1825
1826
1827
1828 
              false
1829
1830
1831
1832
1833
1834 
        ref_clk
1835
1836 
          in
1837
1838
1839 
              std_logic
1840 
              xilinx_anylanguagesynthesis
1841 
              xilinx_anylanguagebehavioralsimulation
1842
1843
1844
1845 
            0
1846
1847
1848
1849
1850
1851 
              false
1852
1853
1854
1855
1856
1857 
        clk_stop
1858
1859 
          out
1860
1861 
            3
1862 
            0
1863
1864
1865
1866 
              std_logic_vector
1867 
              xilinx_anylanguagesynthesis
1868 
              xilinx_anylanguagebehavioralsimulation
1869
1870
1871
1872 
            0
1873
1874
1875
1876
1877
1878 
              false
1879
1880
1881
1882
1883
1884 
        clk_glitch
1885
1886 
          out
1887
1888 
            3
1889 
            0
1890
1891
1892
1893 
              std_logic_vector
1894 
              xilinx_anylanguagesynthesis
1895 
              xilinx_anylanguagebehavioralsimulation
1896
1897
1898
1899 
            0
1900
1901
1902
1903
1904
1905 
              false
1906
1907
1908
1909
1910
1911 
        interrupt
1912
1913 
          out
1914
1915
1916 
              std_logic
1917 
              xilinx_anylanguagesynthesis
1918 
              xilinx_anylanguagebehavioralsimulation
1919
1920
1921
1922 
            0
1923
1924
1925
1926
1927
1928 
              false
1929
1930
1931
1932
1933
1934 
        clk_oor
1935
1936 
          out
1937
1938 
            3
1939 
            0
1940
1941
1942
1943 
              std_logic_vector
1944 
              xilinx_anylanguagesynthesis
1945 
              xilinx_anylanguagebehavioralsimulation
1946
1947
1948
1949 
            0
1950
1951
1952
1953
1954
1955 
              false
1956
1957
1958
1959
1960
1961 
        user_clk0
1962
1963 
          in
1964
1965
1966 
              std_logic
1967 
              xilinx_anylanguagesynthesis
1968 
              xilinx_anylanguagebehavioralsimulation
1969
1970
1971
1972 
            0
1973
1974
1975
1976
1977
1978 
              false
1979
1980
1981
1982
1983
1984 
        user_clk1
1985
1986 
          in
1987
1988
1989 
              std_logic
1990 
              xilinx_anylanguagesynthesis
1991 
              xilinx_anylanguagebehavioralsimulation
1992
1993
1994
1995 
            0
1996
1997
1998
1999
2000
2001 
              false
2002
2003
2004
2005
2006
2007 
        user_clk2
2008
2009 
          in
2010
2011
2012 
              std_logic
2013 
              xilinx_anylanguagesynthesis
2014 
              xilinx_anylanguagebehavioralsimulation
2015
2016
2017
2018 
            0
2019
2020
2021
2022
2023
2024 
              false
2025
2026
2027
2028
2029
2030 
        user_clk3
2031
2032 
          in
2033
2034
2035 
              std_logic
2036 
              xilinx_anylanguagesynthesis
2037 
              xilinx_anylanguagebehavioralsimulation
2038
2039
2040
2041 
            0
2042
2043
2044
2045
2046
2047 
              false
2048
2049
2050
2051
2052
2053 
        clk_out1
2054
2055 
          out
2056
2057
2058 
              std_logic
2059 
              xilinx_anylanguagesynthesis
2060 
              xilinx_anylanguagebehavioralsimulation
2061
2062
2063
2064
2065
2066 
        locked
2067
2068 
          out
2069
2070
2071 
              std_logic
2072 
              xilinx_anylanguagesynthesis
2073 
              xilinx_anylanguagebehavioralsimulation
2074
2075
2076
2077
2078
2079
2080
2081 
        C_CLKOUT2_USED
2082 
        0
2083
2084
2085 
        C_USER_CLK_FREQ0
2086 
        100.0
2087
2088
2089 
        C_AUTO_PRIMITIVE
2090 
        MMCM
2091
2092
2093 
        C_USER_CLK_FREQ1
2094 
        100.0
2095
2096
2097 
        C_USER_CLK_FREQ2
2098 
        100.0
2099
2100
2101 
        C_USER_CLK_FREQ3
2102 
        100.0
2103
2104
2105 
        C_ENABLE_CLOCK_MONITOR
2106 
        0
2107
2108
2109 
        C_ENABLE_USER_CLOCK0
2110 
        0
2111
2112
2113 
        C_ENABLE_USER_CLOCK1
2114 
        0
2115
2116
2117 
        C_ENABLE_USER_CLOCK2
2118 
        0
2119
2120
2121 
        C_ENABLE_USER_CLOCK3
2122 
        0
2123
2124
2125 
        C_Enable_PLL0
2126 
        0
2127
2128
2129 
        C_Enable_PLL1
2130 
        0
2131
2132
2133 
        C_REF_CLK_FREQ
2134 
        100.0
2135
2136
2137 
        C_PRECISION
2138 
        1
2139
2140
2141 
        C_CLKOUT3_USED
2142 
        0
2143
2144
2145 
        C_CLKOUT4_USED
2146 
        0
2147
2148
2149 
        C_CLKOUT5_USED
2150 
        0
2151
2152
2153 
        C_CLKOUT6_USED
2154 
        0
2155
2156
2157 
        C_CLKOUT7_USED
2158 
        0
2159
2160
2161 
        C_USE_CLKOUT1_BAR
2162 
        0
2163
2164
2165 
        C_USE_CLKOUT2_BAR
2166 
        0
2167
2168
2169 
        C_USE_CLKOUT3_BAR
2170 
        0
2171
2172
2173 
        C_USE_CLKOUT4_BAR
2174 
        0
2175
2176
2177 
        c_component_name
2178 
        clk_gen
2179
2180
2181 
        C_PLATFORM
2182 
        UNKNOWN
2183
2184
2185 
        C_USE_FREQ_SYNTH
2186 
        1
2187
2188
2189 
        C_USE_PHASE_ALIGNMENT
2190 
        1
2191
2192
2193 
        C_PRIM_IN_JITTER
2194 
        0.010
2195
2196
2197 
        C_SECONDARY_IN_JITTER
2198 
        0.010
2199
2200
2201 
        C_JITTER_SEL
2202 
        No_Jitter
2203
2204
2205 
        C_USE_MIN_POWER
2206 
        0
2207
2208
2209 
        C_USE_MIN_O_JITTER
2210 
        0
2211
2212
2213 
        C_USE_MAX_I_JITTER
2214 
        0
2215
2216
2217 
        C_USE_DYN_PHASE_SHIFT
2218 
        0
2219
2220
2221 
        C_USE_INCLK_SWITCHOVER
2222 
        0
2223
2224
2225 
        C_USE_DYN_RECONFIG
2226 
        0
2227
2228
2229 
        C_USE_SPREAD_SPECTRUM
2230 
        0
2231
2232
2233 
        C_USE_FAST_SIMULATION
2234 
        0
2235
2236
2237 
        C_PRIMTYPE_SEL
2238 
        AUTO
2239
2240
2241 
        C_USE_CLK_VALID
2242 
        0
2243
2244
2245 
        C_PRIM_IN_FREQ
2246 
        200.000
2247
2248
2249 
        C_PRIM_IN_TIMEPERIOD
2250 
        10.000
2251
2252
2253 
        C_IN_FREQ_UNITS
2254 
        Units_MHz
2255
2256
2257 
        C_SECONDARY_IN_FREQ
2258 
        100.000
2259
2260
2261 
        C_SECONDARY_IN_TIMEPERIOD
2262 
        10.000
2263
2264
2265 
        C_FEEDBACK_SOURCE
2266 
        FDBK_AUTO
2267
2268
2269 
        C_PRIM_SOURCE
2270 
        Differential_clock_capable_pin
2271
2272
2273 
        C_PHASESHIFT_MODE
2274 
        WAVEFORM
2275
2276
2277 
        C_SECONDARY_SOURCE
2278 
        Single_ended_clock_capable_pin
2279
2280
2281 
        C_CLKFB_IN_SIGNALING
2282 
        SINGLE
2283
2284
2285 
        C_USE_RESET
2286 
        1
2287
2288
2289 
        C_RESET_LOW
2290 
        0
2291
2292
2293 
        C_USE_LOCKED
2294 
        1
2295
2296
2297 
        C_USE_INCLK_STOPPED
2298 
        0
2299
2300
2301 
        C_USE_CLKFB_STOPPED
2302 
        0
2303
2304
2305 
        C_USE_POWER_DOWN
2306 
        0
2307
2308
2309 
        C_USE_STATUS
2310 
        0
2311
2312
2313 
        C_USE_FREEZE
2314 
        0
2315
2316
2317 
        C_NUM_OUT_CLKS
2318 
        1
2319
2320
2321 
        C_CLKOUT1_DRIVES
2322 
        BUFG
2323
2324
2325 
        C_CLKOUT2_DRIVES
2326 
        BUFG
2327
2328
2329 
        C_CLKOUT3_DRIVES
2330 
        BUFG
2331
2332
2333 
        C_CLKOUT4_DRIVES
2334 
        BUFG
2335
2336
2337 
        C_CLKOUT5_DRIVES
2338 
        BUFG
2339
2340
2341 
        C_CLKOUT6_DRIVES
2342 
        BUFG
2343
2344
2345 
        C_CLKOUT7_DRIVES
2346 
        BUFG
2347
2348
2349 
        C_INCLK_SUM_ROW0
2350 
        Input Clock   Freq (MHz)    Input Jitter (UI)
2351
2352
2353 
        C_INCLK_SUM_ROW1
2354 
        __primary_________200.000____________0.010
2355
2356
2357 
        C_INCLK_SUM_ROW2
2358 
        no_secondary_input_clock
2359
2360
2361 
        C_OUTCLK_SUM_ROW0A
2362 
        C Outclk Sum Row0a
2363 
         Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
2364
2365
2366 
        C_OUTCLK_SUM_ROW0B
2367 
          Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
2368
2369
2370 
        C_OUTCLK_SUM_ROW1
2371 
        clk_out1___100.000______0.000______50.0______112.316_____89.971
2372
2373
2374 
        C_OUTCLK_SUM_ROW2
2375 
        no_CLK_OUT2_output
2376
2377
2378 
        C_OUTCLK_SUM_ROW3
2379 
        no_CLK_OUT3_output
2380
2381
2382 
        C_OUTCLK_SUM_ROW4
2383 
        no_CLK_OUT4_output
2384
2385
2386 
        C_OUTCLK_SUM_ROW5
2387 
        no_CLK_OUT5_output
2388
2389
2390 
        C_OUTCLK_SUM_ROW6
2391 
        no_CLK_OUT6_output
2392
2393
2394 
        C_OUTCLK_SUM_ROW7
2395 
        no_CLK_OUT7_output
2396
2397
2398 
        C_CLKOUT1_REQUESTED_OUT_FREQ
2399 
        100.000
2400
2401
2402 
        C_CLKOUT2_REQUESTED_OUT_FREQ
2403 
        100.000
2404
2405
2406 
        C_CLKOUT3_REQUESTED_OUT_FREQ
2407 
        100.000
2408
2409
2410 
        C_CLKOUT4_REQUESTED_OUT_FREQ
2411 
        100.000
2412
2413
2414 
        C_CLKOUT5_REQUESTED_OUT_FREQ
2415 
        100.000
2416
2417
2418 
        C_CLKOUT6_REQUESTED_OUT_FREQ
2419 
        100.000
2420
2421
2422 
        C_CLKOUT7_REQUESTED_OUT_FREQ
2423 
        100.000
2424
2425
2426 
        C_CLKOUT1_REQUESTED_PHASE
2427 
        0.000
2428
2429
2430 
        C_CLKOUT2_REQUESTED_PHASE
2431 
        0.000
2432
2433
2434 
        C_CLKOUT3_REQUESTED_PHASE
2435 
        0.000
2436
2437
2438 
        C_CLKOUT4_REQUESTED_PHASE
2439 
        0.000
2440
2441
2442 
        C_CLKOUT5_REQUESTED_PHASE
2443 
        0.000
2444
2445
2446 
        C_CLKOUT6_REQUESTED_PHASE
2447 
        0.000
2448
2449
2450 
        C_CLKOUT7_REQUESTED_PHASE
2451 
        0.000
2452
2453
2454 
        C_CLKOUT1_REQUESTED_DUTY_CYCLE
2455 
        50.000
2456
2457
2458 
        C_CLKOUT2_REQUESTED_DUTY_CYCLE
2459 
        50.000
2460
2461
2462 
        C_CLKOUT3_REQUESTED_DUTY_CYCLE
2463 
        50.000
2464
2465
2466 
        C_CLKOUT4_REQUESTED_DUTY_CYCLE
2467 
        50.000
2468
2469
2470 
        C_CLKOUT5_REQUESTED_DUTY_CYCLE
2471 
        50.000
2472
2473
2474 
        C_CLKOUT6_REQUESTED_DUTY_CYCLE
2475 
        50.000
2476
2477
2478 
        C_CLKOUT7_REQUESTED_DUTY_CYCLE
2479 
        50.000
2480
2481
2482 
        C_CLKOUT1_OUT_FREQ
2483 
        100.000
2484
2485
2486 
        C_CLKOUT2_OUT_FREQ
2487 
        100.000
2488
2489
2490 
        C_CLKOUT3_OUT_FREQ
2491 
        100.000
2492
2493
2494 
        C_CLKOUT4_OUT_FREQ
2495 
        100.000
2496
2497
2498 
        C_CLKOUT5_OUT_FREQ
2499 
        100.000
2500
2501
2502 
        C_CLKOUT6_OUT_FREQ
2503 
        100.000
2504
2505
2506 
        C_CLKOUT7_OUT_FREQ
2507 
        100.000
2508
2509
2510 
        C_CLKOUT1_PHASE
2511 
        0.000
2512
2513
2514 
        C_CLKOUT2_PHASE
2515 
        0.000
2516
2517
2518 
        C_CLKOUT3_PHASE
2519 
        0.000
2520
2521
2522 
        C_CLKOUT4_PHASE
2523 
        0.000
2524
2525
2526 
        C_CLKOUT5_PHASE
2527 
        0.000
2528
2529
2530 
        C_CLKOUT6_PHASE
2531 
        0.000
2532
2533
2534 
        C_CLKOUT7_PHASE
2535 
        0.000
2536
2537
2538 
        C_CLKOUT1_DUTY_CYCLE
2539 
        50.0
2540
2541
2542 
        C_CLKOUT2_DUTY_CYCLE
2543 
        50.000
2544
2545
2546 
        C_CLKOUT3_DUTY_CYCLE
2547 
        50.000
2548
2549
2550 
        C_CLKOUT4_DUTY_CYCLE
2551 
        50.000
2552
2553
2554 
        C_CLKOUT5_DUTY_CYCLE
2555 
        50.000
2556
2557
2558 
        C_CLKOUT6_DUTY_CYCLE
2559 
        50.000
2560
2561
2562 
        C_CLKOUT7_DUTY_CYCLE
2563 
        50.000
2564
2565
2566 
        C_USE_SAFE_CLOCK_STARTUP
2567 
        0
2568
2569
2570 
        C_USE_CLOCK_SEQUENCING
2571 
        0
2572
2573
2574 
        C_CLKOUT1_SEQUENCE_NUMBER
2575 
        1
2576
2577
2578 
        C_CLKOUT2_SEQUENCE_NUMBER
2579 
        1
2580
2581
2582 
        C_CLKOUT3_SEQUENCE_NUMBER
2583 
        1
2584
2585
2586 
        C_CLKOUT4_SEQUENCE_NUMBER
2587 
        1
2588
2589
2590 
        C_CLKOUT5_SEQUENCE_NUMBER
2591 
        1
2592
2593
2594 
        C_CLKOUT6_SEQUENCE_NUMBER
2595 
        1
2596
2597
2598 
        C_CLKOUT7_SEQUENCE_NUMBER
2599 
        1
2600
2601
2602 
        C_MMCM_NOTES
2603 
        None
2604
2605
2606 
        C_MMCM_BANDWIDTH
2607 
        OPTIMIZED
2608
2609
2610 
        C_MMCM_CLKFBOUT_MULT_F
2611 
        5.000
2612
2613
2614 
        C_MMCM_CLKIN1_PERIOD
2615 
        5.000
2616
2617
2618 
        C_MMCM_CLKIN2_PERIOD
2619 
        10.0
2620
2621
2622 
        C_MMCM_CLKOUT4_CASCADE
2623 
        FALSE
2624
2625
2626 
        C_MMCM_CLOCK_HOLD
2627 
        FALSE
2628
2629
2630 
        C_MMCM_COMPENSATION
2631 
        ZHOLD
2632
2633
2634 
        C_MMCM_DIVCLK_DIVIDE
2635 
        1
2636
2637
2638 
        C_MMCM_REF_JITTER1
2639 
        0.010
2640
2641
2642 
        C_MMCM_REF_JITTER2
2643 
        0.010
2644
2645
2646 
        C_MMCM_STARTUP_WAIT
2647 
        FALSE
2648
2649
2650 
        C_MMCM_CLKOUT0_DIVIDE_F
2651 
        10.000
2652
2653
2654 
        C_MMCM_CLKOUT1_DIVIDE
2655 
        1
2656
2657
2658 
        C_MMCM_CLKOUT2_DIVIDE
2659 
        1
2660
2661
2662 
        C_MMCM_CLKOUT3_DIVIDE
2663 
        1
2664
2665
2666 
        C_MMCM_CLKOUT4_DIVIDE
2667 
        1
2668
2669
2670 
        C_MMCM_CLKOUT5_DIVIDE
2671 
        1
2672
2673
2674 
        C_MMCM_CLKOUT6_DIVIDE
2675 
        1
2676
2677
2678 
        C_MMCM_CLKOUT0_DUTY_CYCLE
2679 
        0.500
2680
2681
2682 
        C_MMCM_CLKOUT1_DUTY_CYCLE
2683 
        0.500
2684
2685
2686 
        C_MMCM_CLKOUT2_DUTY_CYCLE
2687 
        0.500
2688
2689
2690 
        C_MMCM_CLKOUT3_DUTY_CYCLE
2691 
        0.500
2692
2693
2694 
        C_MMCM_CLKOUT4_DUTY_CYCLE
2695 
        0.500
2696
2697
2698 
        C_MMCM_CLKOUT5_DUTY_CYCLE
2699 
        0.500
2700
2701
2702 
        C_MMCM_CLKOUT6_DUTY_CYCLE
2703 
        0.500
2704
2705
2706 
        C_MMCM_CLKFBOUT_PHASE
2707 
        0.000
2708
2709
2710 
        C_MMCM_CLKOUT0_PHASE
2711 
        0.000
2712
2713
2714 
        C_MMCM_CLKOUT1_PHASE
2715 
        0.000
2716
2717
2718 
        C_MMCM_CLKOUT2_PHASE
2719 
        0.000
2720
2721
2722 
        C_MMCM_CLKOUT3_PHASE
2723 
        0.000
2724
2725
2726 
        C_MMCM_CLKOUT4_PHASE
2727 
        0.000
2728
2729
2730 
        C_MMCM_CLKOUT5_PHASE
2731 
        0.000
2732
2733
2734 
        C_MMCM_CLKOUT6_PHASE
2735 
        0.000
2736
2737
2738 
        C_MMCM_CLKFBOUT_USE_FINE_PS
2739 
        FALSE
2740
2741
2742 
        C_MMCM_CLKOUT0_USE_FINE_PS
2743 
        FALSE
2744
2745
2746 
        C_MMCM_CLKOUT1_USE_FINE_PS
2747 
        FALSE
2748
2749
2750 
        C_MMCM_CLKOUT2_USE_FINE_PS
2751 
        FALSE
2752
2753
2754 
        C_MMCM_CLKOUT3_USE_FINE_PS
2755 
        FALSE
2756
2757
2758 
        C_MMCM_CLKOUT4_USE_FINE_PS
2759 
        FALSE
2760
2761
2762 
        C_MMCM_CLKOUT5_USE_FINE_PS
2763 
        FALSE
2764
2765
2766 
        C_MMCM_CLKOUT6_USE_FINE_PS
2767 
        FALSE
2768
2769
2770 
        C_PLL_NOTES
2771 
        No notes
2772
2773
2774 
        C_PLL_BANDWIDTH
2775 
        OPTIMIZED
2776
2777
2778 
        C_PLL_CLK_FEEDBACK
2779 
        CLKFBOUT
2780
2781
2782 
        C_PLL_CLKFBOUT_MULT
2783 
        1
2784
2785
2786 
        C_PLL_CLKIN_PERIOD
2787 
        1.000
2788
2789
2790 
        C_PLL_COMPENSATION
2791 
        SYSTEM_SYNCHRONOUS
2792
2793
2794 
        C_PLL_DIVCLK_DIVIDE
2795 
        1
2796
2797
2798 
        C_PLL_REF_JITTER
2799 
        0.010
2800
2801
2802 
        C_PLL_CLKOUT0_DIVIDE
2803 
        1
2804
2805
2806 
        C_PLL_CLKOUT1_DIVIDE
2807 
        1
2808
2809
2810 
        C_PLL_CLKOUT2_DIVIDE
2811 
        1
2812
2813
2814 
        C_PLL_CLKOUT3_DIVIDE
2815 
        1
2816
2817
2818 
        C_PLL_CLKOUT4_DIVIDE
2819 
        1
2820
2821
2822 
        C_PLL_CLKOUT5_DIVIDE
2823 
        1
2824
2825
2826 
        C_PLL_CLKOUT0_DUTY_CYCLE
2827 
        0.500
2828
2829
2830 
        C_PLL_CLKOUT1_DUTY_CYCLE
2831 
        0.500
2832
2833
2834 
        C_PLL_CLKOUT2_DUTY_CYCLE
2835 
        0.500
2836
2837
2838 
        C_PLL_CLKOUT3_DUTY_CYCLE
2839 
        0.500
2840
2841
2842 
        C_PLL_CLKOUT4_DUTY_CYCLE
2843 
        0.500
2844
2845
2846 
        C_PLL_CLKOUT5_DUTY_CYCLE
2847 
        0.500
2848
2849
2850 
        C_PLL_CLKFBOUT_PHASE
2851 
        0.000
2852
2853
2854 
        C_PLL_CLKOUT0_PHASE
2855 
        0.000
2856
2857
2858 
        C_PLL_CLKOUT1_PHASE
2859 
        0.000
2860
2861
2862 
        C_PLL_CLKOUT2_PHASE
2863 
        0.000
2864
2865
2866 
        C_PLL_CLKOUT3_PHASE
2867 
        0.000
2868
2869
2870 
        C_PLL_CLKOUT4_PHASE
2871 
        0.000
2872
2873
2874 
        C_PLL_CLKOUT5_PHASE
2875 
        0.000
2876
2877
2878 
        C_CLOCK_MGR_TYPE
2879 
        NA
2880
2881
2882 
        C_OVERRIDE_MMCM
2883 
        0
2884
2885
2886 
        C_OVERRIDE_PLL
2887 
        0
2888
2889
2890 
        C_PRIMARY_PORT
2891 
        clk_in1
2892
2893
2894 
        C_SECONDARY_PORT
2895 
        clk_in2
2896
2897
2898 
        C_CLK_OUT1_PORT
2899 
        clk_out1
2900
2901
2902 
        C_CLK_OUT2_PORT
2903 
        clk_out2
2904
2905
2906 
        C_CLK_OUT3_PORT
2907 
        clk_out3
2908
2909
2910 
        C_CLK_OUT4_PORT
2911 
        clk_out4
2912
2913
2914 
        C_CLK_OUT5_PORT
2915 
        clk_out5
2916
2917
2918 
        C_CLK_OUT6_PORT
2919 
        clk_out6
2920
2921
2922 
        C_CLK_OUT7_PORT
2923 
        clk_out7
2924
2925
2926 
        C_RESET_PORT
2927 
        reset
2928
2929
2930 
        C_LOCKED_PORT
2931 
        locked
2932
2933
2934 
        C_CLKFB_IN_PORT
2935 
        clkfb_in
2936
2937
2938 
        C_CLKFB_IN_P_PORT
2939 
        clkfb_in_p
2940
2941
2942 
        C_CLKFB_IN_N_PORT
2943 
        clkfb_in_n
2944
2945
2946 
        C_CLKFB_OUT_PORT
2947 
        clkfb_out
2948
2949
2950 
        C_CLKFB_OUT_P_PORT
2951 
        clkfb_out_p
2952
2953
2954 
        C_CLKFB_OUT_N_PORT
2955 
        clkfb_out_n
2956
2957
2958 
        C_POWER_DOWN_PORT
2959 
        power_down
2960
2961
2962 
        C_DADDR_PORT
2963 
        daddr
2964
2965
2966 
        C_DCLK_PORT
2967 
        dclk
2968
2969
2970 
        C_DRDY_PORT
2971 
        drdy
2972
2973
2974 
        C_DWE_PORT
2975 
        dwe
2976
2977
2978 
        C_DIN_PORT
2979 
        din
2980
2981
2982 
        C_DOUT_PORT
2983 
        dout
2984
2985
2986 
        C_DEN_PORT
2987 
        den
2988
2989
2990 
        C_PSCLK_PORT
2991 
        psclk
2992
2993
2994 
        C_PSEN_PORT
2995 
        psen
2996
2997
2998 
        C_PSINCDEC_PORT
2999 
        psincdec
3000
3001
3002 
        C_PSDONE_PORT
3003 
        psdone
3004
3005
3006 
        C_CLK_VALID_PORT
3007 
        CLK_VALID
3008
3009
3010 
        C_STATUS_PORT
3011 
        STATUS
3012
3013
3014 
        C_CLK_IN_SEL_PORT
3015 
        clk_in_sel
3016
3017
3018 
        C_INPUT_CLK_STOPPED_PORT
3019 
        input_clk_stopped
3020
3021
3022 
        C_CLKFB_STOPPED_PORT
3023 
        clkfb_stopped
3024
3025
3026 
        C_CLKIN1_JITTER_PS
3027 
        50.0
3028
3029
3030 
        C_CLKIN2_JITTER_PS
3031 
        100.0
3032
3033
3034 
        C_PRIMITIVE
3035 
        MMCM
3036
3037
3038 
        C_SS_MODE
3039 
        CENTER_HIGH
3040
3041
3042 
        C_SS_MOD_PERIOD
3043 
        4000
3044
3045
3046 
        C_SS_MOD_TIME
3047 
        0.004
3048
3049
3050 
        C_HAS_CDDC
3051 
        0
3052
3053
3054 
        C_CDDCDONE_PORT
3055 
        cddcdone
3056
3057
3058 
        C_CDDCREQ_PORT
3059 
        cddcreq
3060
3061
3062 
        C_CLKOUTPHY_MODE
3063 
        VCO
3064
3065
3066 
        C_ENABLE_CLKOUTPHY
3067 
        0
3068
3069
3070 
        C_INTERFACE_SELECTION
3071 
        0
3072
3073
3074 
        C_S_AXI_ADDR_WIDTH
3075 
        C S Axi Addr Width
3076 
        11
3077
3078
3079 
        C_S_AXI_DATA_WIDTH
3080 
        C S Axi Data Width
3081 
        32
3082
3083
3084 
        C_POWER_REG
3085 
        0000
3086
3087
3088 
        C_CLKOUT0_1
3089 
        0000
3090
3091
3092 
        C_CLKOUT0_2
3093 
        0000
3094
3095
3096 
        C_CLKOUT1_1
3097 
        0000
3098
3099
3100 
        C_CLKOUT1_2
3101 
        0000
3102
3103
3104 
        C_CLKOUT2_1
3105 
        0000
3106
3107
3108 
        C_CLKOUT2_2
3109 
        0000
3110
3111
3112 
        C_CLKOUT3_1
3113 
        0000
3114
3115
3116 
        C_CLKOUT3_2
3117 
        0000
3118
3119
3120 
        C_CLKOUT4_1
3121 
        0000
3122
3123
3124 
        C_CLKOUT4_2
3125 
        0000
3126
3127
3128 
        C_CLKOUT5_1
3129 
        0000
3130
3131
3132 
        C_CLKOUT5_2
3133 
        0000
3134
3135
3136 
        C_CLKOUT6_1
3137 
        0000
3138
3139
3140 
        C_CLKOUT6_2
3141 
        0000
3142
3143
3144 
        C_CLKFBOUT_1
3145 
        0000
3146
3147
3148 
        C_CLKFBOUT_2
3149 
        0000
3150
3151
3152 
        C_DIVCLK
3153 
        0000
3154
3155
3156 
        C_LOCK_1
3157 
        0000
3158
3159
3160 
        C_LOCK_2
3161 
        0000
3162
3163
3164 
        C_LOCK_3
3165 
        0000
3166
3167
3168 
        C_FILTER_1
3169 
        0000
3170
3171
3172 
        C_FILTER_2
3173 
        0000
3174
3175
3176 
        C_DIVIDE1_AUTO
3177 
        1
3178
3179
3180 
        C_DIVIDE2_AUTO
3181 
        1.0
3182
3183
3184 
        C_DIVIDE3_AUTO
3185 
        1.0
3186
3187
3188 
        C_DIVIDE4_AUTO
3189 
        1.0
3190
3191
3192 
        C_DIVIDE5_AUTO
3193 
        1.0
3194
3195
3196 
        C_DIVIDE6_AUTO
3197 
        1.0
3198
3199
3200 
        C_DIVIDE7_AUTO
3201 
        1.0
3202
3203
3204 
        C_PLLBUFGCEDIV
3205 
        false
3206
3207
3208 
        C_MMCMBUFGCEDIV
3209 
        false
3210
3211
3212 
        C_PLLBUFGCEDIV1
3213 
        false
3214
3215
3216 
        C_PLLBUFGCEDIV2
3217 
        false
3218
3219
3220 
        C_PLLBUFGCEDIV3
3221 
        false
3222
3223
3224 
        C_PLLBUFGCEDIV4
3225 
        false
3226
3227
3228 
        C_MMCMBUFGCEDIV1
3229 
        false
3230
3231
3232 
        C_MMCMBUFGCEDIV2
3233 
        false
3234
3235
3236 
        C_MMCMBUFGCEDIV3
3237 
        false
3238
3239
3240 
        C_MMCMBUFGCEDIV4
3241 
        false
3242
3243
3244 
        C_MMCMBUFGCEDIV5
3245 
        false
3246
3247
3248 
        C_MMCMBUFGCEDIV6
3249 
        false
3250
3251
3252 
        C_MMCMBUFGCEDIV7
3253 
        false
3254
3255
3256 
        C_CLKOUT1_MATCHED_ROUTING
3257 
        false
3258
3259
3260 
        C_CLKOUT2_MATCHED_ROUTING
3261 
        false
3262
3263
3264 
        C_CLKOUT3_MATCHED_ROUTING
3265 
        false
3266
3267
3268 
        C_CLKOUT4_MATCHED_ROUTING
3269 
        false
3270
3271
3272 
        C_CLKOUT5_MATCHED_ROUTING
3273 
        false
3274
3275
3276 
        C_CLKOUT6_MATCHED_ROUTING
3277 
        false
3278
3279
3280 
        C_CLKOUT7_MATCHED_ROUTING
3281 
        false
3282
3283
3284 
        C_CLKOUT0_ACTUAL_FREQ
3285 
        100.000
3286
3287
3288 
        C_CLKOUT1_ACTUAL_FREQ
3289 
        100.000
3290
3291
3292 
        C_CLKOUT2_ACTUAL_FREQ
3293 
        100.000
3294
3295
3296 
        C_CLKOUT3_ACTUAL_FREQ
3297 
        100.000
3298
3299
3300 
        C_CLKOUT4_ACTUAL_FREQ
3301 
        100.000
3302
3303
3304 
        C_CLKOUT5_ACTUAL_FREQ
3305 
        100.000
3306
3307
3308 
        C_CLKOUT6_ACTUAL_FREQ
3309 
        100.000
3310
3311
3312
3313
3314
3315 
      choice_list_1d3de01d
3316 
      WAVEFORM
3317 
      LATENCY
3318
3319
3320 
      choice_list_876bfc32
3321 
      UI
3322 
      PS
3323
3324
3325 
      choice_list_a9bdfce0
3326 
      LOW
3327 
      HIGH
3328 
      OPTIMIZED
3329
3330
3331 
      choice_list_b9d38208
3332 
      CLKFBOUT
3333 
      CLKOUT0
3334
3335
3336 
      choice_list_ce26ebdb
3337 
      Custom
3338 
      reset
3339
3340
3341 
      choice_list_e099fe6c
3342 
      MMCM
3343 
      PLL
3344
3345
3346 
      choice_pairs_035ca1c3
3347 
      SYSTEM_SYNCHRONOUS
3348 
      SOURCE_SYNCHRONOUS
3349 
      INTERNAL
3350 
      EXTERNAL
3351
3352
3353 
      choice_pairs_0920eb1b
3354 
      Custom
3355 
      sys_diff_clock
3356
3357
3358 
      choice_pairs_11d71346
3359 
      Single_ended_clock_capable_pin
3360 
      Differential_clock_capable_pin
3361 
      Global_buffer
3362 
      No_buffer
3363
3364
3365 
      choice_pairs_15c806d5
3366 
      FDBK_AUTO
3367 
      FDBK_AUTO_OFFCHIP
3368 
      FDBK_ONCHIP
3369 
      FDBK_OFFCHIP
3370
3371
3372 
      choice_pairs_3c2d3ec7
3373 
      SINGLE
3374 
      DIFF
3375
3376
3377 
      choice_pairs_502d9f23
3378 
      ZHOLD
3379 
      EXTERNAL
3380 
      INTERNAL
3381 
      BUF_IN
3382
3383
3384 
      choice_pairs_66e4c81f
3385 
      BUFG
3386 
      BUFH
3387 
      BUFGCE
3388 
      BUFHCE
3389 
      No_buffer
3390
3391
3392 
      choice_pairs_77d3d587
3393 
      MMCM
3394 
      PLL
3395 
      BUFGCE_DIV
3396
3397
3398 
      choice_pairs_8b28f1f7
3399 
      Enable_AXI
3400 
      Enable_DRP
3401
3402
3403 
      choice_pairs_8eea9b32
3404 
      Units_MHz
3405 
      Units_ns
3406
3407
3408 
      choice_pairs_a4fbc00c
3409 
      ACTIVE_HIGH
3410 
      ACTIVE_LOW
3411
3412
3413 
      choice_pairs_a758bdcc
3414 
      Custom
3415 
      pcie_refclk
3416 
      sys_diff_clock
3417
3418
3419 
      choice_pairs_a8642b4c
3420 
      No_Jitter
3421 
      Min_O_Jitter
3422 
      Max_I_Jitter
3423
3424
3425 
      choice_pairs_c5ef7212
3426 
      Units_UI
3427 
      Units_ps
3428
3429
3430 
      choice_pairs_e1c87518
3431 
      REL_PRIMARY
3432 
      REL_SECONDARY
3433
3434
3435 
      choice_pairs_f4e10086
3436 
      CENTER_HIGH
3437 
      CENTER_LOW
3438 
      DOWN_HIGH
3439 
      DOWN_LOW
3440
3441
3442 
      choice_pairs_f669c2f5
3443 
      frequency
3444 
      Time
3445
3446
3447
3448
3449 
      xilinx_veriloginstantiationtemplate_view_fileset
3450
3451 
        clk_gen.veo
3452 
        verilogTemplate
3453
3454
3455
3456 
      xilinx_anylanguagesynthesis_view_fileset
3457
3458 
        clk_gen.xdc
3459 
        xdc
3460
3461 
          processing_order
3462 
          early
3463
3464
3465
3466 
        clk_gen_ooc.xdc
3467 
        xdc
3468 
        USED_IN_implementation
3469 
        USED_IN_out_of_context
3470 
        USED_IN_synthesis
3471
3472
3473 
        mmcm_pll_drp_func_7s_mmcm.vh
3474 
        verilogSource
3475 
        true
3476 
        clk_wiz_v5_4_3
3477
3478
3479 
        mmcm_pll_drp_func_7s_pll.vh
3480 
        verilogSource
3481 
        true
3482 
        clk_wiz_v5_4_3
3483
3484
3485 
        mmcm_pll_drp_func_us_mmcm.vh
3486 
        verilogSource
3487 
        true
3488 
        clk_wiz_v5_4_3
3489
3490
3491 
        mmcm_pll_drp_func_us_pll.vh
3492 
        verilogSource
3493 
        true
3494 
        clk_wiz_v5_4_3
3495
3496
3497 
        mmcm_pll_drp_func_us_plus_pll.vh
3498 
        verilogSource
3499 
        true
3500 
        clk_wiz_v5_4_3
3501
3502
3503 
        mmcm_pll_drp_func_us_plus_mmcm.vh
3504 
        verilogSource
3505 
        true
3506 
        clk_wiz_v5_4_3
3507
3508
3509 
        clk_gen_clk_wiz.v
3510 
        verilogSource
3511
3512
3513
3514 
      xilinx_anylanguagesynthesiswrapper_view_fileset
3515
3516 
        clk_gen.v
3517 
        verilogSource
3518
3519
3520
3521 
      xilinx_anylanguagebehavioralsimulation_view_fileset
3522
3523 
        mmcm_pll_drp_func_7s_mmcm.vh
3524 
        verilogSource
3525 
        USED_IN_ipstatic
3526 
        true
3527 
        clk_wiz_v5_4_3
3528
3529
3530 
        mmcm_pll_drp_func_7s_pll.vh
3531 
        verilogSource
3532 
        USED_IN_ipstatic
3533 
        true
3534 
        clk_wiz_v5_4_3
3535
3536
3537 
        mmcm_pll_drp_func_us_mmcm.vh
3538 
        verilogSource
3539 
        USED_IN_ipstatic
3540 
        true
3541 
        clk_wiz_v5_4_3
3542
3543
3544 
        mmcm_pll_drp_func_us_pll.vh
3545 
        verilogSource
3546 
        USED_IN_ipstatic
3547 
        true
3548 
        clk_wiz_v5_4_3
3549
3550
3551 
        mmcm_pll_drp_func_us_plus_pll.vh
3552 
        verilogSource
3553 
        USED_IN_ipstatic
3554 
        true
3555 
        clk_wiz_v5_4_3
3556
3557
3558 
        mmcm_pll_drp_func_us_plus_mmcm.vh
3559 
        verilogSource
3560 
        USED_IN_ipstatic
3561 
        true
3562 
        clk_wiz_v5_4_3
3563
3564
3565 
        clk_gen_clk_wiz.v
3566 
        verilogSource
3567
3568
3569
3570 
      xilinx_anylanguagesimulationwrapper_view_fileset
3571
3572 
        clk_gen.v
3573 
        verilogSource
3574
3575
3576
3577 
      xilinx_implementation_view_fileset
3578
3579 
        clk_gen_board.xdc
3580 
        xdc
3581 
        USED_IN_board
3582 
        USED_IN_implementation
3583 
        USED_IN_synthesis
3584
3585
3586
3587 
      xilinx_versioninformation_view_fileset
3588
3589 
        doc/clk_wiz_v5_4_changelog.txt
3590 
        text
3591
3592
3593
3594 
      xilinx_externalfiles_view_fileset
3595
3596 
        clk_gen.dcp
3597 
        dcp
3598 
        USED_IN_implementation
3599 
        USED_IN_synthesis
3600 
        xil_defaultlib
3601
3602
3603 
        clk_gen_stub.v
3604 
        verilogSource
3605 
        USED_IN_synth_blackbox_stub
3606 
        xil_defaultlib
3607
3608
3609 
        clk_gen_stub.vhdl
3610 
        vhdlSource
3611 
        USED_IN_synth_blackbox_stub
3612 
        xil_defaultlib
3613
3614
3615 
        clk_gen_sim_netlist.v
3616 
        verilogSource
3617 
        USED_IN_simulation
3618 
        USED_IN_single_language
3619 
        xil_defaultlib
3620
3621
3622 
        clk_gen_sim_netlist.vhdl
3623 
        vhdlSource
3624 
        USED_IN_simulation
3625 
        USED_IN_single_language
3626 
        xil_defaultlib
3627
3628
3629
3630 
  The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements.
3631
3632
3633 
      Component_Name
3634 
      clk_gen
3635
3636
3637 
      USER_CLK_FREQ0
3638 
      User Frequency(MHz)
3639 
      100.0
3640
3641
3642 
      USER_CLK_FREQ1
3643 
      User Frequency(MHz)
3644 
      100.0
3645
3646
3647 
      USER_CLK_FREQ2
3648 
      User Frequency(MHz)
3649 
      100.0
3650
3651
3652 
      USER_CLK_FREQ3
3653 
      User Frequency(MHz)
3654 
      100.0
3655
3656
3657 
      ENABLE_CLOCK_MONITOR
3658 
      Enable Clock Monitoring
3659 
      false
3660
3661
3662 
      ENABLE_USER_CLOCK0
3663 
      User Clock
3664 
      false
3665
3666
3667 
      ENABLE_USER_CLOCK1
3668 
      User Clock
3669 
      false
3670
3671
3672 
      ENABLE_USER_CLOCK2
3673 
      User Clock
3674 
      false
3675
3676
3677 
      ENABLE_USER_CLOCK3
3678 
      User Clock
3679 
      false
3680
3681
3682 
      Enable_PLL0
3683 
      User Clock
3684 
      false
3685
3686
3687 
      Enable_PLL1
3688 
      User Clock
3689 
      false
3690
3691
3692 
      REF_CLK_FREQ
3693 
      Reference Frequency(MHz)
3694 
      100.0
3695
3696
3697 
      PRECISION
3698 
      Tolerance(MHz)
3699 
      1
3700
3701
3702 
      PRIMITIVE
3703 
      Primitive
3704 
      MMCM
3705
3706
3707 
      PRIMTYPE_SEL
3708 
      Primtype Sel
3709 
      mmcm_adv
3710
3711
3712 
      CLOCK_MGR_TYPE
3713 
      Clock Mgr Type
3714 
      auto
3715
3716
3717 
      USE_FREQ_SYNTH
3718 
      true
3719
3720
3721 
      USE_SPREAD_SPECTRUM
3722 
      false
3723
3724
3725 
      USE_PHASE_ALIGNMENT
3726 
      true
3727
3728
3729 
      USE_MIN_POWER
3730 
      false
3731
3732
3733 
      USE_DYN_PHASE_SHIFT
3734 
      false
3735
3736
3737 
      USE_DYN_RECONFIG
3738 
      false
3739
3740
3741 
      JITTER_SEL
3742 
      No_Jitter
3743
3744
3745 
      PRIM_IN_FREQ
3746 
      200.000
3747
3748
3749 
      PRIM_IN_TIMEPERIOD
3750 
      10.000
3751
3752
3753 
      IN_FREQ_UNITS
3754 
      Units_MHz
3755
3756
3757 
      PHASESHIFT_MODE
3758 
      WAVEFORM
3759
3760
3761 
      IN_JITTER_UNITS
3762 
      Units_UI
3763
3764
3765 
      RELATIVE_INCLK
3766 
      REL_PRIMARY
3767
3768
3769 
      USE_INCLK_SWITCHOVER
3770 
      false
3771
3772
3773 
      SECONDARY_IN_FREQ
3774 
      100.000
3775
3776
3777 
      SECONDARY_IN_TIMEPERIOD
3778 
      10.000
3779
3780
3781 
      SECONDARY_PORT
3782 
      clk_in2
3783
3784
3785 
      SECONDARY_SOURCE
3786 
      Single_ended_clock_capable_pin
3787
3788
3789 
      JITTER_OPTIONS
3790 
      UI
3791
3792
3793 
      CLKIN1_UI_JITTER
3794 
      0.010
3795
3796
3797 
      CLKIN2_UI_JITTER
3798 
      0.010
3799
3800
3801 
      PRIM_IN_JITTER
3802 
      0.010
3803
3804
3805 
      SECONDARY_IN_JITTER
3806 
      0.010
3807
3808
3809 
      CLKIN1_JITTER_PS
3810 
      50.0
3811
3812
3813 
      CLKIN2_JITTER_PS
3814 
      100.0
3815
3816
3817 
      CLKOUT1_USED
3818 
      true
3819
3820
3821 
      CLKOUT2_USED
3822 
      false
3823
3824
3825 
      CLKOUT3_USED
3826 
      false
3827
3828
3829 
      CLKOUT4_USED
3830 
      false
3831
3832
3833 
      CLKOUT5_USED
3834 
      false
3835
3836
3837 
      CLKOUT6_USED
3838 
      false
3839
3840
3841 
      CLKOUT7_USED
3842 
      false
3843
3844
3845 
      NUM_OUT_CLKS
3846 
      1
3847
3848
3849 
      CLK_OUT1_USE_FINE_PS_GUI
3850 
      false
3851
3852
3853 
      CLK_OUT2_USE_FINE_PS_GUI
3854 
      false
3855
3856
3857 
      CLK_OUT3_USE_FINE_PS_GUI
3858 
      false
3859
3860
3861 
      CLK_OUT4_USE_FINE_PS_GUI
3862 
      false
3863
3864
3865 
      CLK_OUT5_USE_FINE_PS_GUI
3866 
      false
3867
3868
3869 
      CLK_OUT6_USE_FINE_PS_GUI
3870 
      false
3871
3872
3873 
      CLK_OUT7_USE_FINE_PS_GUI
3874 
      false
3875
3876
3877 
      PRIMARY_PORT
3878 
      clk_in1
3879
3880
3881 
      CLK_OUT1_PORT
3882 
      clk_out1
3883
3884
3885 
      CLK_OUT2_PORT
3886 
      clk_out2
3887
3888
3889 
      CLK_OUT3_PORT
3890 
      clk_out3
3891
3892
3893 
      CLK_OUT4_PORT
3894 
      clk_out4
3895
3896
3897 
      CLK_OUT5_PORT
3898 
      clk_out5
3899
3900
3901 
      CLK_OUT6_PORT
3902 
      clk_out6
3903
3904
3905 
      CLK_OUT7_PORT
3906 
      clk_out7
3907
3908
3909 
      DADDR_PORT
3910 
      daddr
3911
3912
3913 
      DCLK_PORT
3914 
      dclk
3915
3916
3917 
      DRDY_PORT
3918 
      drdy
3919
3920
3921 
      DWE_PORT
3922 
      dwe
3923
3924
3925 
      DIN_PORT
3926 
      din
3927
3928
3929 
      DOUT_PORT
3930 
      dout
3931
3932
3933 
      DEN_PORT
3934 
      den
3935
3936
3937 
      PSCLK_PORT
3938 
      psclk
3939
3940
3941 
      PSEN_PORT
3942 
      psen
3943
3944
3945 
      PSINCDEC_PORT
3946 
      psincdec
3947
3948
3949 
      PSDONE_PORT
3950 
      psdone
3951
3952
3953 
      CLKOUT1_REQUESTED_OUT_FREQ
3954 
      100.000
3955
3956
3957 
      CLKOUT1_REQUESTED_PHASE
3958 
      0.000
3959
3960
3961 
      CLKOUT1_REQUESTED_DUTY_CYCLE
3962 
      50.000
3963
3964
3965 
      CLKOUT2_REQUESTED_OUT_FREQ
3966 
      100.000
3967
3968
3969 
      CLKOUT2_REQUESTED_PHASE
3970 
      0.000
3971
3972
3973 
      CLKOUT2_REQUESTED_DUTY_CYCLE
3974 
      50.000
3975
3976
3977 
      CLKOUT3_REQUESTED_OUT_FREQ
3978 
      100.000
3979
3980
3981 
      CLKOUT3_REQUESTED_PHASE
3982 
      0.000
3983
3984
3985 
      CLKOUT3_REQUESTED_DUTY_CYCLE
3986 
      50.000
3987
3988
3989 
      CLKOUT4_REQUESTED_OUT_FREQ
3990 
      100.000
3991
3992
3993 
      CLKOUT4_REQUESTED_PHASE
3994 
      0.000
3995
3996
3997 
      CLKOUT4_REQUESTED_DUTY_CYCLE
3998 
      50.000
3999
4000
4001 
      CLKOUT5_REQUESTED_OUT_FREQ
4002 
      100.000
4003
4004
4005 
      CLKOUT5_REQUESTED_PHASE
4006 
      0.000
4007
4008
4009 
      CLKOUT5_REQUESTED_DUTY_CYCLE
4010 
      50.000
4011
4012
4013 
      CLKOUT6_REQUESTED_OUT_FREQ
4014 
      100.000
4015
4016
4017 
      CLKOUT6_REQUESTED_PHASE
4018 
      0.000
4019
4020
4021 
      CLKOUT6_REQUESTED_DUTY_CYCLE
4022 
      50.000
4023
4024
4025 
      CLKOUT7_REQUESTED_OUT_FREQ
4026 
      100.000
4027
4028
4029 
      CLKOUT7_REQUESTED_PHASE
4030 
      0.000
4031
4032
4033 
      CLKOUT7_REQUESTED_DUTY_CYCLE
4034 
      50.000
4035
4036
4037 
      USE_MAX_I_JITTER
4038 
      false
4039
4040
4041 
      USE_MIN_O_JITTER
4042 
      false
4043
4044
4045 
      CLKOUT1_MATCHED_ROUTING
4046 
      false
4047
4048
4049 
      CLKOUT2_MATCHED_ROUTING
4050 
      false
4051
4052
4053 
      CLKOUT3_MATCHED_ROUTING
4054 
      false
4055
4056
4057 
      CLKOUT4_MATCHED_ROUTING
4058 
      false
4059
4060
4061 
      CLKOUT5_MATCHED_ROUTING
4062 
      false
4063
4064
4065 
      CLKOUT6_MATCHED_ROUTING
4066 
      false
4067
4068
4069 
      CLKOUT7_MATCHED_ROUTING
4070 
      false
4071
4072
4073 
      PRIM_SOURCE
4074 
      Differential_clock_capable_pin
4075
4076
4077 
      CLKOUT1_DRIVES
4078 
      BUFG
4079
4080
4081 
      CLKOUT2_DRIVES
4082 
      BUFG
4083
4084
4085 
      CLKOUT3_DRIVES
4086 
      BUFG
4087
4088
4089 
      CLKOUT4_DRIVES
4090 
      BUFG
4091
4092
4093 
      CLKOUT5_DRIVES
4094 
      BUFG
4095
4096
4097 
      CLKOUT6_DRIVES
4098 
      BUFG
4099
4100
4101 
      CLKOUT7_DRIVES
4102 
      BUFG
4103
4104
4105 
      FEEDBACK_SOURCE
4106 
      FDBK_AUTO
4107
4108
4109 
      CLKFB_IN_SIGNALING
4110 
      SINGLE
4111
4112
4113 
      CLKFB_IN_PORT
4114 
      clkfb_in
4115
4116
4117 
      CLKFB_IN_P_PORT
4118 
      clkfb_in_p
4119
4120
4121 
      CLKFB_IN_N_PORT
4122 
      clkfb_in_n
4123
4124
4125 
      CLKFB_OUT_PORT
4126 
      clkfb_out
4127
4128
4129 
      CLKFB_OUT_P_PORT
4130 
      clkfb_out_p
4131
4132
4133 
      CLKFB_OUT_N_PORT
4134 
      clkfb_out_n
4135
4136
4137 
      PLATFORM
4138 
      UNKNOWN
4139
4140
4141 
      SUMMARY_STRINGS
4142 
      empty
4143
4144
4145 
      USE_LOCKED
4146 
      true
4147
4148
4149 
      CALC_DONE
4150 
      empty
4151
4152
4153 
      USE_RESET
4154 
      true
4155
4156
4157 
      USE_POWER_DOWN
4158 
      false
4159
4160
4161 
      USE_STATUS
4162 
      false
4163
4164
4165 
      USE_FREEZE
4166 
      false
4167
4168
4169 
      USE_CLK_VALID
4170 
      false
4171
4172
4173 
      USE_INCLK_STOPPED
4174 
      false
4175
4176
4177 
      USE_CLKFB_STOPPED
4178 
      false
4179
4180
4181 
      RESET_PORT
4182 
      reset
4183
4184
4185 
      LOCKED_PORT
4186 
      locked
4187
4188
4189 
      POWER_DOWN_PORT
4190 
      power_down
4191
4192
4193 
      CLK_VALID_PORT
4194 
      CLK_VALID
4195
4196
4197 
      STATUS_PORT
4198 
      STATUS
4199
4200
4201 
      CLK_IN_SEL_PORT
4202 
      clk_in_sel
4203
4204
4205 
      INPUT_CLK_STOPPED_PORT
4206 
      input_clk_stopped
4207
4208
4209 
      CLKFB_STOPPED_PORT
4210 
      clkfb_stopped
4211
4212
4213 
      SS_MODE
4214 
      CENTER_HIGH
4215
4216
4217 
      SS_MOD_FREQ
4218 
      250
4219
4220
4221 
      SS_MOD_TIME
4222 
      0.004
4223
4224
4225 
      OVERRIDE_MMCM
4226 
      false
4227
4228
4229 
      MMCM_NOTES
4230 
      None
4231
4232
4233 
      MMCM_DIVCLK_DIVIDE
4234 
      1
4235
4236
4237 
      MMCM_BANDWIDTH
4238 
      OPTIMIZED
4239
4240
4241 
      MMCM_CLKFBOUT_MULT_F
4242 
      5.000
4243
4244
4245 
      MMCM_CLKFBOUT_PHASE
4246 
      0.000
4247
4248
4249 
      MMCM_CLKFBOUT_USE_FINE_PS
4250 
      false
4251
4252
4253 
      MMCM_CLKIN1_PERIOD
4254 
      5.000
4255
4256
4257 
      MMCM_CLKIN2_PERIOD
4258 
      10.0
4259
4260
4261 
      MMCM_CLKOUT4_CASCADE
4262 
      false
4263
4264
4265 
      MMCM_CLOCK_HOLD
4266 
      false
4267
4268
4269 
      MMCM_COMPENSATION
4270 
      ZHOLD
4271
4272
4273 
      MMCM_REF_JITTER1
4274 
      0.010
4275
4276
4277 
      MMCM_REF_JITTER2
4278 
      0.010
4279
4280
4281 
      MMCM_STARTUP_WAIT
4282 
      false
4283
4284
4285 
      MMCM_CLKOUT0_DIVIDE_F
4286 
      10.000
4287
4288
4289 
      MMCM_CLKOUT0_DUTY_CYCLE
4290 
      0.500
4291
4292
4293 
      MMCM_CLKOUT0_PHASE
4294 
      0.000
4295
4296
4297 
      MMCM_CLKOUT0_USE_FINE_PS
4298 
      false
4299
4300
4301 
      MMCM_CLKOUT1_DIVIDE
4302 
      1
4303
4304
4305 
      MMCM_CLKOUT1_DUTY_CYCLE
4306 
      0.500
4307
4308
4309 
      MMCM_CLKOUT1_PHASE
4310 
      0.000
4311
4312
4313 
      MMCM_CLKOUT1_USE_FINE_PS
4314 
      false
4315
4316
4317 
      MMCM_CLKOUT2_DIVIDE
4318 
      1
4319
4320
4321 
      MMCM_CLKOUT2_DUTY_CYCLE
4322 
      0.500
4323
4324
4325 
      MMCM_CLKOUT2_PHASE
4326 
      0.000
4327
4328
4329 
      MMCM_CLKOUT2_USE_FINE_PS
4330 
      false
4331
4332
4333 
      MMCM_CLKOUT3_DIVIDE
4334 
      1
4335
4336
4337 
      MMCM_CLKOUT3_DUTY_CYCLE
4338 
      0.500
4339
4340
4341 
      MMCM_CLKOUT3_PHASE
4342 
      0.000
4343
4344
4345 
      MMCM_CLKOUT3_USE_FINE_PS
4346 
      false
4347
4348
4349 
      MMCM_CLKOUT4_DIVIDE
4350 
      1
4351
4352
4353 
      MMCM_CLKOUT4_DUTY_CYCLE
4354 
      0.500
4355
4356
4357 
      MMCM_CLKOUT4_PHASE
4358 
      0.000
4359
4360
4361 
      MMCM_CLKOUT4_USE_FINE_PS
4362 
      false
4363
4364
4365 
      MMCM_CLKOUT5_DIVIDE
4366 
      1
4367
4368
4369 
      MMCM_CLKOUT5_DUTY_CYCLE
4370 
      0.500
4371
4372
4373 
      MMCM_CLKOUT5_PHASE
4374 
      0.000
4375
4376
4377 
      MMCM_CLKOUT5_USE_FINE_PS
4378 
      false
4379
4380
4381 
      MMCM_CLKOUT6_DIVIDE
4382 
      1
4383
4384
4385 
      MMCM_CLKOUT6_DUTY_CYCLE
4386 
      0.500
4387
4388
4389 
      MMCM_CLKOUT6_PHASE
4390 
      0.000
4391
4392
4393 
      MMCM_CLKOUT6_USE_FINE_PS
4394 
      false
4395
4396
4397 
      OVERRIDE_PLL
4398 
      false
4399
4400
4401 
      PLL_NOTES
4402 
      None
4403
4404
4405 
      PLL_BANDWIDTH
4406 
      OPTIMIZED
4407
4408
4409 
      PLL_CLKFBOUT_MULT
4410 
      4
4411
4412
4413 
      PLL_CLKFBOUT_PHASE
4414 
      0.000
4415
4416
4417 
      PLL_CLK_FEEDBACK
4418 
      CLKFBOUT
4419
4420
4421 
      PLL_DIVCLK_DIVIDE
4422 
      1
4423
4424
4425 
      PLL_CLKIN_PERIOD
4426 
      10.000
4427
4428
4429 
      PLL_COMPENSATION
4430 
      SYSTEM_SYNCHRONOUS
4431
4432
4433 
      PLL_REF_JITTER
4434 
      0.010
4435
4436
4437 
      PLL_CLKOUT0_DIVIDE
4438 
      1
4439
4440
4441 
      PLL_CLKOUT0_DUTY_CYCLE
4442 
      0.500
4443
4444
4445 
      PLL_CLKOUT0_PHASE
4446 
      0.000
4447
4448
4449 
      PLL_CLKOUT1_DIVIDE
4450 
      1
4451
4452
4453 
      PLL_CLKOUT1_DUTY_CYCLE
4454 
      0.500
4455
4456
4457 
      PLL_CLKOUT1_PHASE
4458 
      0.000
4459
4460
4461 
      PLL_CLKOUT2_DIVIDE
4462 
      1
4463
4464
4465 
      PLL_CLKOUT2_DUTY_CYCLE
4466 
      0.500
4467
4468
4469 
      PLL_CLKOUT2_PHASE
4470 
      0.000
4471
4472
4473 
      PLL_CLKOUT3_DIVIDE
4474 
      1
4475
4476
4477 
      PLL_CLKOUT3_DUTY_CYCLE
4478 
      0.500
4479
4480
4481 
      PLL_CLKOUT3_PHASE
4482 
      0.000
4483
4484
4485 
      PLL_CLKOUT4_DIVIDE
4486 
      1
4487
4488
4489 
      PLL_CLKOUT4_DUTY_CYCLE
4490 
      0.500
4491
4492
4493 
      PLL_CLKOUT4_PHASE
4494 
      0.000
4495
4496
4497 
      PLL_CLKOUT5_DIVIDE
4498 
      1
4499
4500
4501 
      PLL_CLKOUT5_DUTY_CYCLE
4502 
      0.500
4503
4504
4505 
      PLL_CLKOUT5_PHASE
4506 
      0.000
4507
4508
4509 
      RESET_TYPE
4510 
      Reset Type
4511 
      ACTIVE_HIGH
4512
4513
4514 
      USE_SAFE_CLOCK_STARTUP
4515 
      false
4516
4517
4518 
      USE_CLOCK_SEQUENCING
4519 
      false
4520
4521
4522 
      CLKOUT1_SEQUENCE_NUMBER
4523 
      1
4524
4525
4526 
      CLKOUT2_SEQUENCE_NUMBER
4527 
      1
4528
4529
4530 
      CLKOUT3_SEQUENCE_NUMBER
4531 
      1
4532
4533
4534 
      CLKOUT4_SEQUENCE_NUMBER
4535 
      1
4536
4537
4538 
      CLKOUT5_SEQUENCE_NUMBER
4539 
      1
4540
4541
4542 
      CLKOUT6_SEQUENCE_NUMBER
4543 
      1
4544
4545
4546 
      CLKOUT7_SEQUENCE_NUMBER
4547 
      1
4548
4549
4550 
      USE_BOARD_FLOW
4551 
      Generate Board based IO Constraints
4552 
      false
4553
4554
4555 
      CLK_IN1_BOARD_INTERFACE
4556 
      sys_diff_clock
4557
4558
4559 
      CLK_IN2_BOARD_INTERFACE
4560 
      Custom
4561
4562
4563 
      DIFF_CLK_IN1_BOARD_INTERFACE
4564 
      Custom
4565
4566
4567 
      DIFF_CLK_IN2_BOARD_INTERFACE
4568 
      Custom
4569
4570
4571 
      AUTO_PRIMITIVE
4572 
      MMCM
4573
4574
4575 
      RESET_BOARD_INTERFACE
4576 
      Custom
4577
4578
4579 
      ENABLE_CDDC
4580 
      false
4581
4582
4583 
      CDDCDONE_PORT
4584 
      cddcdone
4585
4586
4587 
      CDDCREQ_PORT
4588 
      cddcreq
4589
4590
4591 
      ENABLE_CLKOUTPHY
4592 
      false
4593
4594
4595 
      CLKOUTPHY_REQUESTED_FREQ
4596 
      600.000
4597
4598
4599 
      CLKOUT1_JITTER
4600 
      Clkout1 Jitter
4601 
      112.316
4602
4603
4604 
      CLKOUT1_PHASE_ERROR
4605 
      Clkout1 Phase
4606 
      89.971
4607
4608
4609 
      CLKOUT2_JITTER
4610 
      Clkout2 Jitter
4611 
      0.0
4612
4613
4614 
      CLKOUT2_PHASE_ERROR
4615 
      Clkout2 Phase
4616 
      0.0
4617
4618
4619 
      CLKOUT3_JITTER
4620 
      Clkout3 Jitter
4621 
      0.0
4622
4623
4624 
      CLKOUT3_PHASE_ERROR
4625 
      Clkout3 Phase
4626 
      0.0
4627
4628
4629 
      CLKOUT4_JITTER
4630 
      Clkout4 Jitter
4631 
      0.0
4632
4633
4634 
      CLKOUT4_PHASE_ERROR
4635 
      Clkout4 Phase
4636 
      0.0
4637
4638
4639 
      CLKOUT5_JITTER
4640 
      Clkout5 Jitter
4641 
      0.0
4642
4643
4644 
      CLKOUT5_PHASE_ERROR
4645 
      Clkout5 Phase
4646 
      0.0
4647
4648
4649 
      CLKOUT6_JITTER
4650 
      Clkout6 Jitter
4651 
      0.0
4652
4653
4654 
      CLKOUT6_PHASE_ERROR
4655 
      Clkout6 Phase
4656 
      0.0
4657
4658
4659 
      CLKOUT7_JITTER
4660 
      Clkout7 Jitter
4661 
      0.0
4662
4663
4664 
      CLKOUT7_PHASE_ERROR
4665 
      Clkout7 Phase
4666 
      0.0
4667
4668
4669 
      INPUT_MODE
4670 
      frequency
4671
4672
4673 
      INTERFACE_SELECTION
4674 
      Enable_AXI
4675
4676
4677 
      AXI_DRP
4678 
      Write DRP registers
4679 
      false
4680
4681
4682 
      PHASE_DUTY_CONFIG
4683 
      Phase Duty Cycle Config
4684 
      false
4685
4686
4687
4688
4689 
      Clocking Wizard
4690
4691 
        XPM_CDC
4692
4693 
      3
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708 
      2017.4
4709
4710
4711
4712
4713
4714
4715
4716

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