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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

// --------------------------------------------------------------------------------

// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017

// Date        : Thu Jul 23 09:43:35 2020

// Host        : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)

// Command     : write_verilog -force -mode synth_stub -rename_top clk_gen -prefix

//               clk_gen_ clk_gen_stub.v

// Design      : clk_gen

// Purpose     : Stub declaration of top-level module interface

// Device      : xc7k325tffg900-2

// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.

// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.

// Please paste the declaration into a Verilog source file or add the file as an additional source.

module clk_gen(clk_out1, reset, locked, clk_in1_p, clk_in1_n)

/* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1_p,clk_in1_n" */;

  output clk_out1;

  input reset;

  output locked;

  input clk_in1_p;

  input clk_in1_n;

endmodule