Subversion Repositories aes-128-ecb-encoder

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

-- --------------------------------------------------------------------------------

-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017

-- Date        : Thu Jul 23 09:43:35 2020

-- Host        : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)

-- Command     : write_vhdl -force -mode synth_stub -rename_top clk_gen -prefix

--               clk_gen_ clk_gen_stub.vhdl

-- Design      : clk_gen

-- Purpose     : Stub declaration of top-level module interface

-- Device      : xc7k325tffg900-2

-- --------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity clk_gen is

  Port (

    clk_out1 : out STD_LOGIC;

    reset : in STD_LOGIC;

    locked : out STD_LOGIC;

    clk_in1_p : in STD_LOGIC;

    clk_in1_n : in STD_LOGIC

  );

end clk_gen;

architecture stub of clk_gen is

attribute syn_black_box : boolean;

attribute black_box_pad_pin : string;

attribute syn_black_box of stub : architecture is true;

attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1_p,clk_in1_n";

begin

end;