Subversion Repositories aes-128-ecb-encoder

2017.4:

 * Version 5.4 (Rev. 3)

 * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL

 * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 CR-991054

2017.3:

 * Version 5.4 (Rev. 2)

 * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices

2017.2:

 * Version 5.4 (Rev. 1)

 * General: Internal GUI changes. No effect on the customer design.

2017.1:

 * Version 5.4

 * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.

 * Other: Added support for new zynq ultrascale plus devices.

2016.4:

 * Version 5.3 (Rev. 3)

 * Bug Fix: Internal GUI issues are fixed.

2016.3:

 * Version 5.3 (Rev. 2)

 * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.

 * Feature Enhancement: Added Matched Routing Option for better timing solutions.

 * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.

 * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user

 * Other: Added support for Spartan7 devices.

2016.2:

 * Version 5.3 (Rev. 1)

 * Internal register bit update, no effect on customer designs.

2016.1:

 * Version 5.3

 * Added Clock Monitor Feature as part of clocking wizard

 * DRP registers can be directly written through AXI without resource utilization

 * Changes to HDL library management to support Vivado IP simulation library

2015.4.2:

 * Version 5.2 (Rev. 1)

 * No changes

2015.4.1:

 * Version 5.2 (Rev. 1)

 * No changes

2015.4:

 * Version 5.2 (Rev. 1)

 * Internal device family change, no functional changes

2015.3:

 * Version 5.2

 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

 * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported

 * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature

 * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format

 * Example design and simulation files are delivered in verilog only

2015.2.1:

 * Version 5.1 (Rev. 6)

 * No changes

2015.2:

 * Version 5.1 (Rev. 6)

 * No changes

2015.1:

 * Version 5.1 (Rev. 6)

 * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices

 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:

 * Version 5.1 (Rev. 5)

 * No changes

2014.4:

 * Version 5.1 (Rev. 5)

 * Internal device family change, no functional changes

 * updates related to the source selection based on board interface for zed board

2014.3:

 * Version 5.1 (Rev. 4)

 * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface

2014.2:

 * Version 5.1 (Rev. 3)

 * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065

2014.1:

 * Version 5.1 (Rev. 2)

 * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock

 * Internal device family name change, no functional changes

2013.4:

 * Version 5.1 (Rev. 1)

 * Added support for Ultrascale devices

 * Updated Board Flow GUI to select the clock interfaces

 * Fixed issue with Stub file parameter error for BUFR output driver

2013.3:

 * Version 5.1

 * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL

 * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies

 * Fixed precision issues between displayed and actual frequencies

 * Added tool tips to GUI

 * Added Jitter and Phase error values to IP properties

 * Added support for Cadence IES and Synopsys VCS simulators

 * Reduced warnings in synthesis and simulation

 * Enhanced support for IP Integrator

2013.2:

 * Version 5.0 (Rev. 1)

 * Fixed issue with clock constraints for multiple instances of clocking wizard

 * Updated Life-Cycle status of devices

2013.1:

 * Version 5.0

 * Lower case ports for Verilog

 * Added Safe Clock Startup and Clock Sequencing

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