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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [vivado.log] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev 
#-----------------------------------------------------------
2 
# Vivado v2017.4 (64-bit)
3 
# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
5 
# Start of session at: Thu Jul 30 13:33:37 2020
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# Process ID: 8661
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# Current directory: /home/user/aes128/fpga/aes128_ecb_2017
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# Command line: vivado
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# Log file: /home/user/aes128/fpga/aes128_ecb_2017/vivado.log
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# Journal file: /home/user/aes128/fpga/aes128_ecb_2017/vivado.jou
11 
#-----------------------------------------------------------
12 
start_gui
13 
open_project /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
14 
Scanning sources...
15 
Finished scanning sources
16 
INFO: [IP_Flow 19-234] Refreshing IP repositories
17 
INFO: [IP_Flow 19-1704] No user IP repositories specified
18 
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
19 
update_compile_order -fileset sources_1
20 
open_run impl_1
21 
INFO: [Netlist 29-17] Analyzing 920 Unisim elements for replacement
22 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
23 
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
24 
INFO: [Device 21-403] Loading part xc7k325tffg900-2
25 
INFO: [Project 1-570] Preparing netlist for logic optimization
26 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap_board.xdc]
27 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap_board.xdc]
28 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap_early.xdc]
29 
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
30 
INFO: [Timing 38-2] Deriving generated clocks [/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
31 
get_clocks: Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 6946.168 ; gain = 540.656 ; free physical = 2369 ; free virtual = 7494
32 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap_early.xdc]
33 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap.xdc]
34 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp0/aes128_ecb_fpga_wrap.xdc]
35 
Reading XDEF placement.
36 
Reading placer database...
37 
Reading XDEF routing.
38 
Read XDEF File: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6951.168 ; gain = 5.000 ; free physical = 2364 ; free virtual = 7489
39 
Restored from archive | CPU: 0.170000 secs | Memory: 4.382431 MB |
40 
Finished XDEF File Restore: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 6951.168 ; gain = 5.000 ; free physical = 2364 ; free virtual = 7489
41 
INFO: [Project 1-111] Unisim Transformation Summary:
42 
No Unisim elements were transformed.
43 
 
44 
open_run: Time (s): cpu = 00:00:30 ; elapsed = 00:00:41 . Memory (MB): peak = 7149.465 ; gain = 1021.266 ; free physical = 2265 ; free virtual = 7384
45 
open_hw
46 
connect_hw_server
47 
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
48 
INFO: [Labtools 27-2222] Launching hw_server...
49 
INFO: [Labtools 27-2221] Launch Output:
50 
 
51 
****** Xilinx hw_server v2017.4
52 
  **** Build date : Dec 15 2017-21:02:11
53 
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
54 
 
55 
 
56 
connect_hw_server: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 7149.465 ; gain = 0.000 ; free physical = 2204 ; free virtual = 7334
57 
open_hw_target
58 
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
59 
ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601.
60 
Check cable connectivity and that the target board is powered up then
61 
use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
62 
ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors.
63 
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
64 
disconnect_hw_server localhost:3121
65 
connect_hw_server
66 
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
67 
connect_hw_server: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 7149.465 ; gain = 0.000 ; free physical = 2202 ; free virtual = 7330
68 
open_hw_target
69 
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
70 
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
71 
current_hw_device [get_hw_devices xc7k325t_0]
72 
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7k325t_0] 0]
73 
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
74 
WARNING: [Labtools 27-3361] The debug hub core was not detected.
75 
Resolution:
76 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
77 
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
78 
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
79 
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {28f00ap30t-bpi-x16}] 0]
80 
set_property PROBES.FILE {} [get_hw_devices xc7k325t_0]
81 
set_property FULL_PROBES.FILE {} [get_hw_devices xc7k325t_0]
82 
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
83 
program_hw_devices -disable_eos_check [get_hw_devices xc7k325t_0]
84 
INFO: [Labtools 27-3164] End of startup status: HIGH
85 
program_hw_devices: Time (s): cpu = 00:00:32 ; elapsed = 00:00:32 . Memory (MB): peak = 7621.066 ; gain = 0.000 ; free physical = 1704 ; free virtual = 6833
86 
refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
87 
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
88 
WARNING: [Labtools 27-3361] The debug hub core was not detected.
89 
Resolution:
90 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
91 
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
92 
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
93 
close_hw
94 
reset_run synth_1
95 
launch_runs impl_1 -to_step write_bitstream -jobs 2
96 
[Thu Jul 30 13:52:01 2020] Launched synth_1...
97 
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
98 
[Thu Jul 30 13:52:01 2020] Launched impl_1...
99 
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
100 
open_hw
101 
connect_hw_server
102 
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
103 
INFO: [Labtools 27-2222] Launching hw_server...
104 
INFO: [Labtools 27-2221] Launch Output:
105 
 
106 
****** Xilinx hw_server v2017.4
107 
  **** Build date : Dec 15 2017-21:02:11
108 
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
109 
 
110 
 
111 
open_hw_target
112 
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
113 
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
114 
current_hw_device [get_hw_devices xc7k325t_0]
115 
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7k325t_0] 0]
116 
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
117 
WARNING: [Labtools 27-3361] The debug hub core was not detected.
118 
Resolution:
119 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
120 
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
121 
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
122 
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {28f00ap30t-bpi-x16}] 0]
123 
set_property PROBES.FILE {} [get_hw_devices xc7k325t_0]
124 
set_property FULL_PROBES.FILE {} [get_hw_devices xc7k325t_0]
125 
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
126 
program_hw_devices [get_hw_devices xc7k325t_0]
127 
INFO: [Labtools 27-3164] End of startup status: HIGH
128 
program_hw_devices: Time (s): cpu = 00:00:32 ; elapsed = 00:00:32 . Memory (MB): peak = 7720.871 ; gain = 0.000 ; free physical = 3185 ; free virtual = 6778
129 
refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
130 
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
131 
WARNING: [Labtools 27-3361] The debug hub core was not detected.
132 
Resolution:
133 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
134 
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
135 
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
136 
close_hw
137 
close_design
138 
close_project
139 
open_project /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
140 
Scanning sources...
141 
Finished scanning sources
142 
INFO: [IP_Flow 19-234] Refreshing IP repositories
143 
INFO: [IP_Flow 19-1704] No user IP repositories specified
144 
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
145 
update_compile_order -fileset sources_1
146 
close_project
147 
create_project uart_lb_test /home/user/aes128/fpga/uart_lb_test -part xc7k325tffg900-2
148 
INFO: [IP_Flow 19-234] Refreshing IP repositories
149 
INFO: [IP_Flow 19-1704] No user IP repositories specified
150 
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
151 
set_property board_part xilinx.com:kc705:part0:1.5 [current_project]
152 
close [ open /home/user/aes128/fpga/uart_lb_test/src/top_wrap.v w ]
153 
add_files /home/user/aes128/fpga/uart_lb_test/src/top_wrap.v
154 
update_compile_order -fileset sources_1
155 
file mkdir /home/user/aes128/fpga/uart_lb_test/uart_lb_test.srcs/constrs_1
156 
close [ open /home/user/aes128/fpga/uart_lb_test/uart_lb_test.srcs/constrs_1/pinout.sdc w ]
157 
add_files -fileset constrs_1 /home/user/aes128/fpga/uart_lb_test/uart_lb_test.srcs/constrs_1/pinout.sdc
158 
launch_runs impl_1 -jobs 2
159 
[Thu Jul 30 14:10:31 2020] Launched synth_1...
160 
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/synth_1/runme.log
161 
[Thu Jul 30 14:10:31 2020] Launched impl_1...
162 
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/impl_1/runme.log
163 
launch_runs impl_1 -to_step write_bitstream -jobs 2
164 
[Thu Jul 30 14:13:11 2020] Launched impl_1...
165 
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/impl_1/runme.log
166 
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
167 
reset_run impl_1 -prev_step
168 
launch_runs impl_1 -to_step write_bitstream -jobs 2
169 
[Thu Jul 30 14:16:51 2020] Launched impl_1...
170 
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/impl_1/runme.log
171 
open_run impl_1
172 
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
173 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
174 
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
175 
INFO: [Project 1-570] Preparing netlist for logic optimization
176 
Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp3/top_wrap.xdc]
177 
Finished Parsing XDC File [/home/user/aes128/fpga/aes128_ecb_2017/.Xil/Vivado-8661-orme22/dcp3/top_wrap.xdc]
178 
Reading XDEF placement.
179 
Reading placer database...
180 
Reading XDEF routing.
181 
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7722.867 ; gain = 0.000 ; free physical = 3169 ; free virtual = 6792
182 
Restored from archive | CPU: 0.000000 secs | Memory: 0.015068 MB |
183 
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7722.867 ; gain = 0.000 ; free physical = 3169 ; free virtual = 6792
184 
INFO: [Project 1-111] Unisim Transformation Summary:
185 
No Unisim elements were transformed.
186 
 
187 
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
188 
reset_run synth_1
189 
launch_runs impl_1 -to_step write_bitstream -jobs 2
190 
[Thu Jul 30 14:20:03 2020] Launched synth_1...
191 
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/synth_1/runme.log
192 
[Thu Jul 30 14:20:03 2020] Launched impl_1...
193 
Run output will be captured here: /home/user/aes128/fpga/uart_lb_test/uart_lb_test.runs/impl_1/runme.log
194 
close_project
195 
open_project /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.xpr
196 
Scanning sources...
197 
Finished scanning sources
198 
INFO: [IP_Flow 19-234] Refreshing IP repositories
199 
INFO: [IP_Flow 19-1704] No user IP repositories specified
200 
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
201 
update_compile_order -fileset sources_1
202 
open_hw
203 
connect_hw_server
204 
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
205 
INFO: [Labtools 27-2222] Launching hw_server...
206 
INFO: [Labtools 27-2221] Launch Output:
207 
 
208 
****** Xilinx hw_server v2017.4
209 
  **** Build date : Dec 15 2017-21:02:11
210 
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
211 
 
212 
 
213 
open_hw_target
214 
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
215 
set_property PROGRAM.FILE {/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit} [get_hw_devices xc7k325t_0]
216 
current_hw_device [get_hw_devices xc7k325t_0]
217 
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7k325t_0] 0]
218 
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
219 
WARNING: [Labtools 27-3361] The debug hub core was not detected.
220 
Resolution:
221 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
222 
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
223 
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
224 
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {28f00ap30t-bpi-x16}] 0]
225 
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
226 
reset_run impl_1 -prev_step
227 
launch_runs impl_1 -to_step write_bitstream -jobs 2
228 
[Thu Jul 30 15:31:01 2020] Launched impl_1...
229 
Run output will be captured here: /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
230 
write_cfgmem  -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit" } -force -file "/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.mcs"
231 
Command: write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit" } -force -file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.mcs
232 
Creating config memory files...
233 
INFO: [Writecfgmem 68-23] Start address provided has been multiplied by a factor of 2 due to the use of interface BPIX16.
234 
Creating bitstream load up from address 0x00000000
235 
Loading bitfile /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit
236 
Writing file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.mcs
237 
Writing log file /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.prm
238 
===================================
239 
Configuration Memory information
240 
===================================
241 
File Format        MCS
242 
Interface          BPIX16
243 
Size               128M
244 
Start Address      0x00000000
245 
End Address        0x07FFFFFF
246 
 
247 
Addr1         Addr2         Date                    File(s)
248 
0x00000000    0x00AE9D9B    Jul 30 15:32:06 2020    /home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit
249 
1 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
250 
write_cfgmem completed successfully
251 
set_property PROGRAM.ADDRESS_RANGE  {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
252 
set_property PROGRAM.FILES [list "/home/user/aes128/fpga/aes128_ecb_2017/aes128_ecb.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
253 
set_property PROGRAM.PRM_FILE {} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
254 
set_property PROGRAM.BPI_RS_PINS {none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
255 
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
256 
set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
257 
set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
258 
set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
259 
set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
260 
set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
261 
startgroup
262 
if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE  [lindex [get_hw_devices xc7k325t_0] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]]]] }  { create_hw_bitstream -hw_device [lindex [get_hw_devices xc7k325t_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xc7k325t_0] 0]]; program_hw_devices [lindex [get_hw_devices xc7k325t_0] 0]; };
263 
INFO: [Labtools 27-3164] End of startup status: HIGH
264 
program_hw_devices: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 7722.867 ; gain = 0.000 ; free physical = 2434 ; free virtual = 6398
265 
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7k325t_0] 0]]
266 
Mfg ID : 89   Memory Type : 8962   Memory Capacity : 0   Device ID 1 : 0   Device ID 2 : 0
267 
Performing Erase Operation...
268 
Erase Operation successful.
269 
Performing Program and Verify Operations...
270 
Program/Verify Operation successful.
271 
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
272 
program_hw_cfgmem: Time (s): cpu = 00:00:14 ; elapsed = 00:04:28 . Memory (MB): peak = 7722.867 ; gain = 0.000 ; free physical = 2427 ; free virtual = 6380
273 
endgroup
274 
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
275 
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
276 
INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
277 
WARNING: [Labtools 27-3361] The debug hub core was not detected.
278 
Resolution:
279 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
280 
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
281 
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
282 
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
283 
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Xilinx/000014d2ca8601
284 
exit
285 
INFO: [Common 17-206] Exiting Vivado at Thu Jul 30 15:42:17 2020...

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