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vv_gulyaev |
#-----------------------------------------------------------
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# Vivado v2017.4 (64-bit)
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# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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# Start of session at: Mon Jul 27 14:17:14 2020
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# Process ID: 17813
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# Current directory: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb
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# Command line: vivado
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# Log file: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/vivado.log
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# Journal file: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/vivado.jou
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#-----------------------------------------------------------
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start_gui
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open_project /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.xpr
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update_compile_order -fileset sources_1
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open_run synth_1 -name synth_1
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close_design
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close [ open /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/timings.xdc w ]
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add_files -fileset constrs_1 /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/timings.xdc
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set_property target_constrs_file /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/timings.xdc [current_fileset -constrset]
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reset_run synth_1
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launch_runs synth_1 -jobs 16
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wait_on_run synth_1
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open_run synth_1 -name synth_1
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set_input_delay -clock [get_clocks [list [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]] 5.0 [get_ports uart_rx]
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set_output_delay -clock [get_clocks [list [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]] 5.0 [get_ports -regexp -filter { NAME =~ ".*" && DIRECTION == "OUT" }]
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save_constraints
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close_design
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reset_run synth_1
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launch_runs impl_1 -jobs 16
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wait_on_run impl_1
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open_run impl_1
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reset_run synth_1
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launch_runs impl_1 -jobs 16
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wait_on_run impl_1
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report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
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refresh_design
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report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
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write_verilog ./netlist/aes128_ecb_wrap.v
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write_sdf ./netlist/aes128_ecb_wrap.sdf
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write_sdf -help
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write_sdf ./netlist/uartlite.sdf -cell uartlite
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write_verilog -help
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write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim
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write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim -force
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write_verilog -help
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write_sdf -help
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write_sdf ./netlist/aes128_ecb_wrap.sdf -mode timesim
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write_sdf ./netlist/aes128_ecb_wrap.sdf -mode timesim -force
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write_sdf ./netlist/uartlite.sdf -cell uartlite -mode timesim -force
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write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim -force -sdf_file ./netlist/aes128_ecb_wrap.sdf
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write_verilog -help
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write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim -force -sdf_file ./netlist/aes128_ecb_wrap.sdf -sdf_anno 1
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write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim -force
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compile_simlib -simulator ies -simulator_exec_path {/opt/cad/Cadence/IC6/XCELIUMMAIN18.09.005_/bin} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
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compile_simlib -simulator ies -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/bin} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
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compile_simlib -help
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compile_simlib -simulator ies -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/tools.lnx86/bin/64bit} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
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compile_simlib -help
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compile_simlib -simulator xrun -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/tools.lnx86/bin/64bit} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
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compile_simlib -simulator xsim -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/tools.lnx86/bin/64bit} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
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compile_simlib -simulator ies -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/tools.lnx86/bin/64bit} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
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copy_ip -name axi_uartlite_module_sim -dir /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip [get_ips axi_uartlite_module]
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update_compile_order -fileset sources_1
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generate_target all [get_files /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci]
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catch { config_ip_cache -export [get_ips -all axi_uartlite_module_sim] }
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export_ip_user_files -of_objects [get_files /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci] -no_script -sync -force -quiet
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create_ip_run [get_files -of_objects [get_fileset sources_1] /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci]
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export_simulation -of_objects [get_files /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci] -directory /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.ip_user_files/sim_scripts -ip_user_files_dir /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.ip_user_files -ipstatic_source_dir /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.ip_user_files/ipstatic -lib_map_path [list {modelsim=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/modelsim} {questa=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/questa} {ies=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/ies} {vcs=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/vcs} {riviera=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
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set_property used_in_synthesis false [get_files /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci]
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set_property used_in_implementation false [get_files /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci]
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close_project
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open_project /ssd/v.gulyaev/usb_otg/fpga/vivado_proj/otg_and_dev.xpr
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update_compile_order -fileset sources_1
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