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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [vivado_17813.backup.log] - Blame information for rev 2

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Line No. Rev Author Line
1 2 vv_gulyaev 
#-----------------------------------------------------------
2 
# Vivado v2017.4 (64-bit)
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# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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# Start of session at: Mon Jul 27 14:17:14 2020
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# Process ID: 17813
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# Current directory: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb
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# Command line: vivado
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# Log file: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/vivado.log
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# Journal file: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/vivado.jou
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#-----------------------------------------------------------
12 
start_gui
13 
open_project /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.xpr
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
18 
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip'.
19 
open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:07 . Memory (MB): peak = 6355.180 ; gain = 112.898 ; free physical = 63973 ; free virtual = 105017
20 
update_compile_order -fileset sources_1
21 
open_run synth_1 -name synth_1
22 
Design is defaulting to impl run constrset: constrs_1
23 
Design is defaulting to synth run part: xc7k325tffg900-2
24 
INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen'
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INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite'
26 
INFO: [Netlist 29-17] Analyzing 911 Unisim elements for replacement
27 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
28 
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
29 
INFO: [Device 21-403] Loading part xc7k325tffg900-2
30 
INFO: [Project 1-570] Preparing netlist for logic optimization
31 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst'
32 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst'
33 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
34 
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
35 
INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
36 
get_clocks: Time (s): cpu = 00:00:17 ; elapsed = 00:00:34 . Memory (MB): peak = 7256.945 ; gain = 597.508 ; free physical = 63177 ; free virtual = 104349
37 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
38 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'uartlite/U0'
39 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'uartlite/U0'
40 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'uartlite/U0'
41 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'uartlite/U0'
42 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
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Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
44 
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
45 
INFO: [Project 1-111] Unisim Transformation Summary:
46 
No Unisim elements were transformed.
47 
 
48 
open_run: Time (s): cpu = 00:00:49 ; elapsed = 00:01:13 . Memory (MB): peak = 7381.996 ; gain = 1004.809 ; free physical = 63009 ; free virtual = 104187
49 
close_design
50 
close [ open /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/timings.xdc w ]
51 
add_files -fileset constrs_1 /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/timings.xdc
52 
set_property target_constrs_file /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/timings.xdc [current_fileset -constrset]
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reset_run synth_1
54 
launch_runs synth_1 -jobs 16
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[Mon Jul 27 14:20:37 2020] Launched synth_1...
56 
Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/synth_1/runme.log
57 
open_run synth_1 -name synth_1
58 
Design is defaulting to impl run constrset: constrs_1
59 
Design is defaulting to synth run part: xc7k325tffg900-2
60 
INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.dcp' for cell 'clkgen'
61 
INFO: [Project 1-454] Reading design checkpoint '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.dcp' for cell 'uartlite'
62 
INFO: [Netlist 29-17] Analyzing 911 Unisim elements for replacement
63 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
64 
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
65 
INFO: [Project 1-570] Preparing netlist for logic optimization
66 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst'
67 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen_board.xdc] for cell 'clkgen/inst'
68 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
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INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
70 
INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
71 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc] for cell 'clkgen/inst'
72 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'uartlite/U0'
73 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module_board.xdc] for cell 'uartlite/U0'
74 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'uartlite/U0'
75 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module/axi_uartlite_module.xdc] for cell 'uartlite/U0'
76 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
77 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/pinout.xdc]
78 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/timings.xdc]
79 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/constrs_1/new/timings.xdc]
80 
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
81 
INFO: [Project 1-111] Unisim Transformation Summary:
82 
No Unisim elements were transformed.
83 
 
84 
INFO: [Timing 38-35] Done setting XDC timing constraints.
85 
set_input_delay -clock [get_clocks [list  [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]] 5.0 [get_ports uart_rx]
86 
set_output_delay -clock [get_clocks [list  [get_clocks -of_objects [get_pins clkgen/inst/mmcm_adv_inst/CLKOUT0]]]] 5.0 [get_ports -regexp -filter { NAME =~  ".*" && DIRECTION == "OUT" }]
87 
save_constraints
88 
close_design
89 
reset_run synth_1
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launch_runs impl_1 -jobs 16
91 
[Mon Jul 27 14:44:36 2020] Launched synth_1...
92 
Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/synth_1/runme.log
93 
[Mon Jul 27 14:44:36 2020] Launched impl_1...
94 
Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/impl_1/runme.log
95 
open_run impl_1
96 
INFO: [Netlist 29-17] Analyzing 911 Unisim elements for replacement
97 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
98 
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
99 
INFO: [Project 1-570] Preparing netlist for logic optimization
100 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp10/aes128_ecb_fpga_wrap_board.xdc]
101 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp10/aes128_ecb_fpga_wrap_board.xdc]
102 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp10/aes128_ecb_fpga_wrap_early.xdc]
103 
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
104 
INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
105 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp10/aes128_ecb_fpga_wrap_early.xdc]
106 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp10/aes128_ecb_fpga_wrap.xdc]
107 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp10/aes128_ecb_fpga_wrap.xdc]
108 
Reading XDEF placement.
109 
Reading placer database...
110 
Reading XDEF routing.
111 
Read XDEF File: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 7427.301 ; gain = 0.000 ; free physical = 59793 ; free virtual = 104050
112 
Restored from archive | CPU: 0.240000 secs | Memory: 4.186943 MB |
113 
Finished XDEF File Restore: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 7427.301 ; gain = 0.000 ; free physical = 59793 ; free virtual = 104050
114 
INFO: [Project 1-111] Unisim Transformation Summary:
115 
No Unisim elements were transformed.
116 
 
117 
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
118 
reset_run synth_1
119 
launch_runs impl_1 -jobs 16
120 
[Mon Jul 27 14:54:52 2020] Launched synth_1...
121 
Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/synth_1/runme.log
122 
[Mon Jul 27 14:54:52 2020] Launched impl_1...
123 
Run output will be captured here: /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.runs/impl_1/runme.log
124 
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
125 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
126 
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
127 
refresh_design
128 
INFO: [Netlist 29-17] Analyzing 911 Unisim elements for replacement
129 
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
130 
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
131 
INFO: [Project 1-570] Preparing netlist for logic optimization
132 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp13/aes128_ecb_fpga_wrap_board.xdc]
133 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp13/aes128_ecb_fpga_wrap_board.xdc]
134 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp13/aes128_ecb_fpga_wrap_early.xdc]
135 
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
136 
INFO: [Timing 38-2] Deriving generated clocks [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
137 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp13/aes128_ecb_fpga_wrap_early.xdc]
138 
Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp13/aes128_ecb_fpga_wrap.xdc]
139 
Finished Parsing XDC File [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/.Xil/Vivado-17813-gigant.modulew.local/dcp13/aes128_ecb_fpga_wrap.xdc]
140 
Reading XDEF placement.
141 
Reading placer database...
142 
Reading XDEF routing.
143 
Read XDEF File: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 7509.332 ; gain = 0.000 ; free physical = 57386 ; free virtual = 102688
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Restored from archive | CPU: 0.260000 secs | Memory: 4.221275 MB |
145 
Finished XDEF File Restore: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.24 . Memory (MB): peak = 7509.332 ; gain = 0.000 ; free physical = 57386 ; free virtual = 102688
146 
refresh_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 7553.523 ; gain = 44.191 ; free physical = 57308 ; free virtual = 102605
147 
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
148 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
149 
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
150 
write_verilog ./netlist/aes128_ecb_wrap.v
151 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/aes128_ecb_wrap.v
152 
write_sdf ./netlist/aes128_ecb_wrap.sdf
153 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/aes128_ecb_wrap.sdf
154 
write_sdf -help
155 
write_sdf
156 
 
157 
Description:
158 
write_sdf command generates flat sdf delay files for event simulation
159 
 
160 
Syntax:
161 
write_sdf  [-process_corner ] [-cell ] [-rename_top ] [-force]
162 
           [-mode ] [-quiet] [-verbose]
163 
 
164 
Usage:
165 
  Name               Description
166 
  ------------------------------
167 
  [-process_corner]  Specify process corner for which SDF delays are
168 
                     required; Values: slow, fast
169 
                     Default: slow
170 
  [-cell]            Root of the design to write, e.g. des.subblk.cpu
171 
                     Default: whole design
172 
  [-rename_top]      Replace name of top module with custom name e.g. netlist
173 
                     Default: new top module name
174 
  [-force]           Overwrite existing SDF file
175 
  [-mode]            Specify sta (Static Timing Analysis) or timesim (Timing
176 
                     Simulation) mode for SDF
177 
                     Default: timesim
178 
  [-quiet]           Ignore command errors
179 
  [-verbose]         Suspend message limits during command execution
180 
               File name
181 
 
182 
Categories:
183 
FileIO, Simulation, Timing
184 
 
185 
Description:
186 
 
187 
  Writes the timing delays for cells in the design to a Standard Delay Format
188 
  (SDF) file.
189 
 
190 
  The output SDF file can be used by the write_verilog command to create
191 
  Verilog netlists for static timing analysis and timing simulation.
192 
 
193 
Arguments:
194 
 
195 
  -process_corner [ fast | slow ] - (Optional) Write delays for a specified
196 
  process corner. Delays are greater in the slow process corner than in the
197 
  fast process corner. Valid values are `slow` or `fast`. By default, the SDF
198 
  file is written for the slow process corner.
199 
 
200 
  -cell  - (Optional) Write the SDF file from a specific cell of the
201 
  design hierarchy. The default is to create an SDF file for the whole
202 
  design.
203 
 
204 
  -rename_top  - (Optional) Rename the top module in the output SDF file
205 
  as specified.
206 
 
207 
  -force - (Optional) Forces the overwrite of an existing SDF file of the
208 
  same name.
209 
 
210 
  -mode [ timesim | sta ]- (Optional) Specifies the mode to use when writing
211 
  the SDF file. Valid values are:
212 
 
213 
   *  timesim - Output an SDF file to be used for timing simulation. This is
214 
      the default setting.
215 
 
216 
   *  sta - Output an SDF file to be used for static timing analysis (STA).
217 
 
218 
  -quiet - (Optional) Execute the command quietly, returning no messages from
219 
  the command. The command also returns TCL_OK regardless of any errors
220 
  encountered during execution.
221 
 
222 
  Note: Any errors encountered on the command-line, while launching the
223 
  command, will be returned. Only errors occurring inside the command will be
224 
  trapped.
225 
 
226 
  -verbose - (Optional) Temporarily override any message limits and return
227 
  all messages from this command.
228 
 
229 
  Note: Message limits can be defined with the set_msg_config command.
230 
 
231 
   - (Required) The file name of the SDF file to write. The SDF file is
232 
  referenced in the Verilog netlist by the use of the -sdf_anno and -sdf_file
233 
  arguments of the write_verilog command.
234 
 
235 
  Note: If the path is not specified as part of the file name, the file will
236 
  be written into the current working directory, or the directory from which
237 
  the tool was launched.
238 
 
239 
Examples:
240 
 
241 
  The following example writes an SDF file to the specified directory:
242 
 
243 
    write_sdf C:/Data/FPGA_Design/designOut.sdf
244 
 
245 
See Also:
246 
 
247 
   *  write_verilog
248 
write_sdf ./netlist/uartlite.sdf  -cell uartlite
249 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/uartlite.sdf
250 
write_verilog  -help
251 
write_verilog
252 
 
253 
Description:
254 
Export the current netlist in Verilog format
255 
 
256 
Syntax:
257 
write_verilog  [-cell ] [-mode ] [-lib] [-port_diff_buffers]
258 
               [-write_all_overrides] [-keep_vcc_gnd] [-rename_top ]
259 
               [-sdf_anno ] [-sdf_file ] [-force]
260 
               [-include_xilinx_libs] [-logic_function_stripped] [-quiet]
261 
               [-verbose]
262 
 
263 
Returns:
264 
the name of the output file or directory
265 
 
266 
Usage:
267 
  Name                        Description
268 
  ---------------------------------------
269 
  [-cell]                     Root of the design to write, e.g.
270 
                              des.subblk.cpu
271 
                              Default: whole design
272 
  [-mode]                     Values: design, pin_planning, synth_stub, sta,
273 
                              funcsim, timesim
274 
                              Default: design
275 
  [-lib]                      Write each library into a separate file
276 
  [-port_diff_buffers]        Output differential buffers when writing in
277 
                              -port mode
278 
  [-write_all_overrides]      Write parameter overrides on Xilinx primitives
279 
                              even if the override value is the same as the
280 
                              default value
281 
  [-keep_vcc_gnd]             Don't replace VCC/GND instances by literal
282 
                              constants on load terminals.  For simulation
283 
                              modes only.
284 
  [-rename_top]               Replace top module name with custom name e.g.
285 
                              netlist
286 
                              Default: new top module name
287 
  [-sdf_anno]                 Specify if sdf_annotate system task statement
288 
                              is generated
289 
  [-sdf_file]                 Full path to sdf file location
290 
                              Default: .sdf
291 
  [-force]                    Overwrite existing file
292 
  [-include_xilinx_libs]      Include simulation models directly in netlist
293 
                              instead of linking to library
294 
  [-logic_function_stripped]  Convert INIT strings on LUTs & RAMBs to fixed
295 
                              values.  Resulting netlist will not behave
296 
                              correctly.
297 
  [-quiet]                    Ignore command errors
298 
  [-verbose]                  Suspend message limits during command execution
299 
                        Which file to write
300 
 
301 
Categories:
302 
FileIO, Simulation
303 
 
304 
Description:
305 
 
306 
  Write a Verilog netlist of the current design or from a specific cell of
307 
  the design to the specified file or directory. The output is a IEEE
308 
  1364-2001 compliant Verilog HDL file that contains netlist information
309 
  obtained from the input design files.
310 
 
311 
  You can output a complete netlist of the design or specific cell, or output
312 
  a port list for the design, or a Verilog netlist for simulation or static
313 
  timing analysis.
314 
 
315 
Arguments:
316 
 
317 
  -cell  - (Optional) Write the Verilog netlist from a specified cell or
318 
  block level of the design hierarchy. The output Verilog file or files will
319 
  only include information contained within the specified cell or module.
320 
 
321 
  -mode  - (Optional) The mode to use when writing the Verilog file. By
322 
  default, the Verilog netlist is written for the whole design. Valid mode
323 
  values are:
324 
 
325 
   *  design - Output a Verilog netlist for the whole design. This acts as a
326 
      snapshot of the design, including all post placement, implementation,
327 
      and routing information in the netlist.
328 
 
329 
   *  pin_planning - Output only the I/O ports for the top-level of the design.
330 
 
331 
   *  synth_stub - Output the ports from the top-level of the design for use
332 
      as a synthesis stub.
333 
 
334 
   *  sta - Output a Verilog netlist to be used for static timing analysis
335 
      (STA).
336 
 
337 
   *  funcsim - Output a Verilog netlist to be used for functional
338 
      simulation. The output netlist is not suitable for synthesis.
339 
 
340 
   *  timesim - Output a Verilog netlist to be used for timing simulation.
341 
      The output netlist is not suitable for synthesis.
342 
 
343 
  -lib - (Optional) Create a separate Verilog file for each library used by
344 
  the design.
345 
 
346 
  Note: The -library option can only be used for simulation. Vivado synthesis
347 
  will treat all Verilog files as being in the default work library.
348 
 
349 
  -port_diff_buffers - (Optional) Add the differential pair buffers and
350 
  internal wires associated with those buffers into the output ports list.
351 
  This argument is only valid when -mode pin_planning or -mode synth_stub is
352 
  specified.
353 
 
354 
  -write_all_overrides [ true | false ] - (Optional) Write parameter
355 
  overrides, in the design to the Verilog output even if the value of the
356 
  parameter is the same as the defined primitive default value. If the option
357 
  is false then parameter values which are equivalent to the primitive
358 
  defaults are not output to the Verilog file. Setting this option to true
359 
  will not change the result but makes the output Verilog more verbose.
360 
 
361 
  -keep_vcc_gnd - (Optional) By default, when writing a nelist for
362 
  simulation, or from an IP Integrator block design, the Vivado Design Suite
363 
  replaces VCC and GND primitives, and the nets they drive, with literal
364 
  constants on each of the loads on the net. The -keep_vcc_gnd option
365 
  disables this default behavior and preserves the VCC or GND primitives.
366 
 
367 
  -rename_top  - (Optional) Rename the top module in the output as
368 
  specified. This option only works with -mode funcsim or -mode timesim to
369 
  allow the Verilog netlist to plug into top-level simulation test benches.
370 
 
371 
  -sdf_anno [ true | false ] - (Optional) Add the $sdf_annotate statement to
372 
  the Verilog netlist. Valid values are true (or 1) and false (or 0). This
373 
  option only works with -mode timesim, and is set to false by default.
374 
 
375 
  -sdf_file  - (Optional) The path and filename of the SDF file to use
376 
  when writing the $sdf_annotate statement into the output Verilog file. When
377 
  not specified, the SDF file is assumed to have the same name and path as
378 
  the Verilog output specified by , with a file extension of .sdf. The
379 
  SDF file must be separately written to the specified file path and name
380 
  using the write_sdf command.
381 
 
382 
  -force - (Optional) Overwrite the Verilog files if they already exists.
383 
 
384 
  -include_xilinx_libs - (Optional) Write the simulation models directly in
385 
  the output netlist file rather than pointing to the libraries by reference.
386 
 
387 
  -logic_function_stripped - (Optional) Hides the INIT values for LUTs & RAMs
388 
  by converting them to fixed values in order to create a netlist for debug
389 
  purposes that will not behave properly in simulation or synthesis.
390 
 
391 
  -quiet - (Optional) Execute the command quietly, returning no messages from
392 
  the command. The command also returns TCL_OK regardless of any errors
393 
  encountered during execution.
394 
 
395 
  Note: Any errors encountered on the command-line, while launching the
396 
  command, will be returned. Only errors occurring inside the command will be
397 
  trapped.
398 
 
399 
  -verbose - (Optional) Temporarily override any message limits and return
400 
  all messages from this command.
401 
 
402 
  Note: Message limits can be defined with the set_msg_config command.
403 
 
404 
   - (Required) The path and filename of the Verilog file to write. The
405 
  path is optional, but if one is not provided the Verilog file will be
406 
  written to the current working directory, or the directory from which the
407 
  Vivado tool was launched.
408 
 
409 
Examples:
410 
 
411 
  The following example writes a Verilog simulation netlist file for the
412 
  whole design to the specified file and path:
413 
 
414 
    write_verilog C:/Data/my_verilog.v
415 
 
416 
  In the following example, because the -mode timesim and -sdf_anno options
417 
  are specified, the $sdf_annotate statement will be added to the Verilog
418 
  netlist. However, since the -sdf_file option is not specified, the SDF file
419 
  is assumed to have the same name as the Verilog output file, with an .sdf
420 
  file extension:
421 
 
422 
    write_verilog C:/Data/my_verilog.net -mode timesim -sdf_anno true
423 
 
424 
  Note: The SDF filename written to the $sdf_annotate statement will be
425 
  my_verilog.sdf.
426 
 
427 
  In the following example, the functional simulation mode is specified, the
428 
  option to keep VCC and GND primitives in the output simulation netlist is
429 
  enabled, and the output file is specified:
430 
 
431 
    write_verilog -mode funcsim -keep_vcc_gnd out.v
432 
 
433 
See Also:
434 
 
435 
   *  write_sdf
436 
   *  write_vhdl
437 
write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim
438 
ERROR: [Common 17-176] Overwrite of existing file isn't enabled.  Please specify -force to overwrite file  [/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/aes128_ecb_wrap.v]
439 
write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim -force
440 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/aes128_ecb_wrap.v
441 
write_verilog  -help
442 
write_verilog
443 
 
444 
Description:
445 
Export the current netlist in Verilog format
446 
 
447 
Syntax:
448 
write_verilog  [-cell ] [-mode ] [-lib] [-port_diff_buffers]
449 
               [-write_all_overrides] [-keep_vcc_gnd] [-rename_top ]
450 
               [-sdf_anno ] [-sdf_file ] [-force]
451 
               [-include_xilinx_libs] [-logic_function_stripped] [-quiet]
452 
               [-verbose]
453 
 
454 
Returns:
455 
the name of the output file or directory
456 
 
457 
Usage:
458 
  Name                        Description
459 
  ---------------------------------------
460 
  [-cell]                     Root of the design to write, e.g.
461 
                              des.subblk.cpu
462 
                              Default: whole design
463 
  [-mode]                     Values: design, pin_planning, synth_stub, sta,
464 
                              funcsim, timesim
465 
                              Default: design
466 
  [-lib]                      Write each library into a separate file
467 
  [-port_diff_buffers]        Output differential buffers when writing in
468 
                              -port mode
469 
  [-write_all_overrides]      Write parameter overrides on Xilinx primitives
470 
                              even if the override value is the same as the
471 
                              default value
472 
  [-keep_vcc_gnd]             Don't replace VCC/GND instances by literal
473 
                              constants on load terminals.  For simulation
474 
                              modes only.
475 
  [-rename_top]               Replace top module name with custom name e.g.
476 
                              netlist
477 
                              Default: new top module name
478 
  [-sdf_anno]                 Specify if sdf_annotate system task statement
479 
                              is generated
480 
  [-sdf_file]                 Full path to sdf file location
481 
                              Default: .sdf
482 
  [-force]                    Overwrite existing file
483 
  [-include_xilinx_libs]      Include simulation models directly in netlist
484 
                              instead of linking to library
485 
  [-logic_function_stripped]  Convert INIT strings on LUTs & RAMBs to fixed
486 
                              values.  Resulting netlist will not behave
487 
                              correctly.
488 
  [-quiet]                    Ignore command errors
489 
  [-verbose]                  Suspend message limits during command execution
490 
                        Which file to write
491 
 
492 
Categories:
493 
FileIO, Simulation
494 
 
495 
Description:
496 
 
497 
  Write a Verilog netlist of the current design or from a specific cell of
498 
  the design to the specified file or directory. The output is a IEEE
499 
  1364-2001 compliant Verilog HDL file that contains netlist information
500 
  obtained from the input design files.
501 
 
502 
  You can output a complete netlist of the design or specific cell, or output
503 
  a port list for the design, or a Verilog netlist for simulation or static
504 
  timing analysis.
505 
 
506 
Arguments:
507 
 
508 
  -cell  - (Optional) Write the Verilog netlist from a specified cell or
509 
  block level of the design hierarchy. The output Verilog file or files will
510 
  only include information contained within the specified cell or module.
511 
 
512 
  -mode  - (Optional) The mode to use when writing the Verilog file. By
513 
  default, the Verilog netlist is written for the whole design. Valid mode
514 
  values are:
515 
 
516 
   *  design - Output a Verilog netlist for the whole design. This acts as a
517 
      snapshot of the design, including all post placement, implementation,
518 
      and routing information in the netlist.
519 
 
520 
   *  pin_planning - Output only the I/O ports for the top-level of the design.
521 
 
522 
   *  synth_stub - Output the ports from the top-level of the design for use
523 
      as a synthesis stub.
524 
 
525 
   *  sta - Output a Verilog netlist to be used for static timing analysis
526 
      (STA).
527 
 
528 
   *  funcsim - Output a Verilog netlist to be used for functional
529 
      simulation. The output netlist is not suitable for synthesis.
530 
 
531 
   *  timesim - Output a Verilog netlist to be used for timing simulation.
532 
      The output netlist is not suitable for synthesis.
533 
 
534 
  -lib - (Optional) Create a separate Verilog file for each library used by
535 
  the design.
536 
 
537 
  Note: The -library option can only be used for simulation. Vivado synthesis
538 
  will treat all Verilog files as being in the default work library.
539 
 
540 
  -port_diff_buffers - (Optional) Add the differential pair buffers and
541 
  internal wires associated with those buffers into the output ports list.
542 
  This argument is only valid when -mode pin_planning or -mode synth_stub is
543 
  specified.
544 
 
545 
  -write_all_overrides [ true | false ] - (Optional) Write parameter
546 
  overrides, in the design to the Verilog output even if the value of the
547 
  parameter is the same as the defined primitive default value. If the option
548 
  is false then parameter values which are equivalent to the primitive
549 
  defaults are not output to the Verilog file. Setting this option to true
550 
  will not change the result but makes the output Verilog more verbose.
551 
 
552 
  -keep_vcc_gnd - (Optional) By default, when writing a nelist for
553 
  simulation, or from an IP Integrator block design, the Vivado Design Suite
554 
  replaces VCC and GND primitives, and the nets they drive, with literal
555 
  constants on each of the loads on the net. The -keep_vcc_gnd option
556 
  disables this default behavior and preserves the VCC or GND primitives.
557 
 
558 
  -rename_top  - (Optional) Rename the top module in the output as
559 
  specified. This option only works with -mode funcsim or -mode timesim to
560 
  allow the Verilog netlist to plug into top-level simulation test benches.
561 
 
562 
  -sdf_anno [ true | false ] - (Optional) Add the $sdf_annotate statement to
563 
  the Verilog netlist. Valid values are true (or 1) and false (or 0). This
564 
  option only works with -mode timesim, and is set to false by default.
565 
 
566 
  -sdf_file  - (Optional) The path and filename of the SDF file to use
567 
  when writing the $sdf_annotate statement into the output Verilog file. When
568 
  not specified, the SDF file is assumed to have the same name and path as
569 
  the Verilog output specified by , with a file extension of .sdf. The
570 
  SDF file must be separately written to the specified file path and name
571 
  using the write_sdf command.
572 
 
573 
  -force - (Optional) Overwrite the Verilog files if they already exists.
574 
 
575 
  -include_xilinx_libs - (Optional) Write the simulation models directly in
576 
  the output netlist file rather than pointing to the libraries by reference.
577 
 
578 
  -logic_function_stripped - (Optional) Hides the INIT values for LUTs & RAMs
579 
  by converting them to fixed values in order to create a netlist for debug
580 
  purposes that will not behave properly in simulation or synthesis.
581 
 
582 
  -quiet - (Optional) Execute the command quietly, returning no messages from
583 
  the command. The command also returns TCL_OK regardless of any errors
584 
  encountered during execution.
585 
 
586 
  Note: Any errors encountered on the command-line, while launching the
587 
  command, will be returned. Only errors occurring inside the command will be
588 
  trapped.
589 
 
590 
  -verbose - (Optional) Temporarily override any message limits and return
591 
  all messages from this command.
592 
 
593 
  Note: Message limits can be defined with the set_msg_config command.
594 
 
595 
   - (Required) The path and filename of the Verilog file to write. The
596 
  path is optional, but if one is not provided the Verilog file will be
597 
  written to the current working directory, or the directory from which the
598 
  Vivado tool was launched.
599 
 
600 
Examples:
601 
 
602 
  The following example writes a Verilog simulation netlist file for the
603 
  whole design to the specified file and path:
604 
 
605 
    write_verilog C:/Data/my_verilog.v
606 
 
607 
  In the following example, because the -mode timesim and -sdf_anno options
608 
  are specified, the $sdf_annotate statement will be added to the Verilog
609 
  netlist. However, since the -sdf_file option is not specified, the SDF file
610 
  is assumed to have the same name as the Verilog output file, with an .sdf
611 
  file extension:
612 
 
613 
    write_verilog C:/Data/my_verilog.net -mode timesim -sdf_anno true
614 
 
615 
  Note: The SDF filename written to the $sdf_annotate statement will be
616 
  my_verilog.sdf.
617 
 
618 
  In the following example, the functional simulation mode is specified, the
619 
  option to keep VCC and GND primitives in the output simulation netlist is
620 
  enabled, and the output file is specified:
621 
 
622 
    write_verilog -mode funcsim -keep_vcc_gnd out.v
623 
 
624 
See Also:
625 
 
626 
   *  write_sdf
627 
   *  write_vhdl
628 
write_sdf -help
629 
write_sdf
630 
 
631 
Description:
632 
write_sdf command generates flat sdf delay files for event simulation
633 
 
634 
Syntax:
635 
write_sdf  [-process_corner ] [-cell ] [-rename_top ] [-force]
636 
           [-mode ] [-quiet] [-verbose]
637 
 
638 
Usage:
639 
  Name               Description
640 
  ------------------------------
641 
  [-process_corner]  Specify process corner for which SDF delays are
642 
                     required; Values: slow, fast
643 
                     Default: slow
644 
  [-cell]            Root of the design to write, e.g. des.subblk.cpu
645 
                     Default: whole design
646 
  [-rename_top]      Replace name of top module with custom name e.g. netlist
647 
                     Default: new top module name
648 
  [-force]           Overwrite existing SDF file
649 
  [-mode]            Specify sta (Static Timing Analysis) or timesim (Timing
650 
                     Simulation) mode for SDF
651 
                     Default: timesim
652 
  [-quiet]           Ignore command errors
653 
  [-verbose]         Suspend message limits during command execution
654 
               File name
655 
 
656 
Categories:
657 
FileIO, Simulation, Timing
658 
 
659 
Description:
660 
 
661 
  Writes the timing delays for cells in the design to a Standard Delay Format
662 
  (SDF) file.
663 
 
664 
  The output SDF file can be used by the write_verilog command to create
665 
  Verilog netlists for static timing analysis and timing simulation.
666 
 
667 
Arguments:
668 
 
669 
  -process_corner [ fast | slow ] - (Optional) Write delays for a specified
670 
  process corner. Delays are greater in the slow process corner than in the
671 
  fast process corner. Valid values are `slow` or `fast`. By default, the SDF
672 
  file is written for the slow process corner.
673 
 
674 
  -cell  - (Optional) Write the SDF file from a specific cell of the
675 
  design hierarchy. The default is to create an SDF file for the whole
676 
  design.
677 
 
678 
  -rename_top  - (Optional) Rename the top module in the output SDF file
679 
  as specified.
680 
 
681 
  -force - (Optional) Forces the overwrite of an existing SDF file of the
682 
  same name.
683 
 
684 
  -mode [ timesim | sta ]- (Optional) Specifies the mode to use when writing
685 
  the SDF file. Valid values are:
686 
 
687 
   *  timesim - Output an SDF file to be used for timing simulation. This is
688 
      the default setting.
689 
 
690 
   *  sta - Output an SDF file to be used for static timing analysis (STA).
691 
 
692 
  -quiet - (Optional) Execute the command quietly, returning no messages from
693 
  the command. The command also returns TCL_OK regardless of any errors
694 
  encountered during execution.
695 
 
696 
  Note: Any errors encountered on the command-line, while launching the
697 
  command, will be returned. Only errors occurring inside the command will be
698 
  trapped.
699 
 
700 
  -verbose - (Optional) Temporarily override any message limits and return
701 
  all messages from this command.
702 
 
703 
  Note: Message limits can be defined with the set_msg_config command.
704 
 
705 
   - (Required) The file name of the SDF file to write. The SDF file is
706 
  referenced in the Verilog netlist by the use of the -sdf_anno and -sdf_file
707 
  arguments of the write_verilog command.
708 
 
709 
  Note: If the path is not specified as part of the file name, the file will
710 
  be written into the current working directory, or the directory from which
711 
  the tool was launched.
712 
 
713 
Examples:
714 
 
715 
  The following example writes an SDF file to the specified directory:
716 
 
717 
    write_sdf C:/Data/FPGA_Design/designOut.sdf
718 
 
719 
See Also:
720 
 
721 
   *  write_verilog
722 
write_sdf ./netlist/aes128_ecb_wrap.sdf -mode timesim
723 
ERROR: [Common 17-176] Overwrite of existing file isn't enabled.  Please specify -force to overwrite file  [./netlist/aes128_ecb_wrap.sdf]
724 
write_sdf ./netlist/aes128_ecb_wrap.sdf -mode timesim -force
725 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/aes128_ecb_wrap.sdf
726 
write_sdf ./netlist/uartlite.sdf  -cell uartlite -mode timesim -force
727 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/uartlite.sdf
728 
write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim -force -sdf_file ./netlist/aes128_ecb_wrap.sdf
729 
WARNING: [Vivado 12-1784] -sdf_file has no effect when sdf_anno is not enabled
730 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/aes128_ecb_wrap.v
731 
write_verilog  -help
732 
write_verilog
733 
 
734 
Description:
735 
Export the current netlist in Verilog format
736 
 
737 
Syntax:
738 
write_verilog  [-cell ] [-mode ] [-lib] [-port_diff_buffers]
739 
               [-write_all_overrides] [-keep_vcc_gnd] [-rename_top ]
740 
               [-sdf_anno ] [-sdf_file ] [-force]
741 
               [-include_xilinx_libs] [-logic_function_stripped] [-quiet]
742 
               [-verbose]
743 
 
744 
Returns:
745 
the name of the output file or directory
746 
 
747 
Usage:
748 
  Name                        Description
749 
  ---------------------------------------
750 
  [-cell]                     Root of the design to write, e.g.
751 
                              des.subblk.cpu
752 
                              Default: whole design
753 
  [-mode]                     Values: design, pin_planning, synth_stub, sta,
754 
                              funcsim, timesim
755 
                              Default: design
756 
  [-lib]                      Write each library into a separate file
757 
  [-port_diff_buffers]        Output differential buffers when writing in
758 
                              -port mode
759 
  [-write_all_overrides]      Write parameter overrides on Xilinx primitives
760 
                              even if the override value is the same as the
761 
                              default value
762 
  [-keep_vcc_gnd]             Don't replace VCC/GND instances by literal
763 
                              constants on load terminals.  For simulation
764 
                              modes only.
765 
  [-rename_top]               Replace top module name with custom name e.g.
766 
                              netlist
767 
                              Default: new top module name
768 
  [-sdf_anno]                 Specify if sdf_annotate system task statement
769 
                              is generated
770 
  [-sdf_file]                 Full path to sdf file location
771 
                              Default: .sdf
772 
  [-force]                    Overwrite existing file
773 
  [-include_xilinx_libs]      Include simulation models directly in netlist
774 
                              instead of linking to library
775 
  [-logic_function_stripped]  Convert INIT strings on LUTs & RAMBs to fixed
776 
                              values.  Resulting netlist will not behave
777 
                              correctly.
778 
  [-quiet]                    Ignore command errors
779 
  [-verbose]                  Suspend message limits during command execution
780 
                        Which file to write
781 
 
782 
Categories:
783 
FileIO, Simulation
784 
 
785 
Description:
786 
 
787 
  Write a Verilog netlist of the current design or from a specific cell of
788 
  the design to the specified file or directory. The output is a IEEE
789 
  1364-2001 compliant Verilog HDL file that contains netlist information
790 
  obtained from the input design files.
791 
 
792 
  You can output a complete netlist of the design or specific cell, or output
793 
  a port list for the design, or a Verilog netlist for simulation or static
794 
  timing analysis.
795 
 
796 
Arguments:
797 
 
798 
  -cell  - (Optional) Write the Verilog netlist from a specified cell or
799 
  block level of the design hierarchy. The output Verilog file or files will
800 
  only include information contained within the specified cell or module.
801 
 
802 
  -mode  - (Optional) The mode to use when writing the Verilog file. By
803 
  default, the Verilog netlist is written for the whole design. Valid mode
804 
  values are:
805 
 
806 
   *  design - Output a Verilog netlist for the whole design. This acts as a
807 
      snapshot of the design, including all post placement, implementation,
808 
      and routing information in the netlist.
809 
 
810 
   *  pin_planning - Output only the I/O ports for the top-level of the design.
811 
 
812 
   *  synth_stub - Output the ports from the top-level of the design for use
813 
      as a synthesis stub.
814 
 
815 
   *  sta - Output a Verilog netlist to be used for static timing analysis
816 
      (STA).
817 
 
818 
   *  funcsim - Output a Verilog netlist to be used for functional
819 
      simulation. The output netlist is not suitable for synthesis.
820 
 
821 
   *  timesim - Output a Verilog netlist to be used for timing simulation.
822 
      The output netlist is not suitable for synthesis.
823 
 
824 
  -lib - (Optional) Create a separate Verilog file for each library used by
825 
  the design.
826 
 
827 
  Note: The -library option can only be used for simulation. Vivado synthesis
828 
  will treat all Verilog files as being in the default work library.
829 
 
830 
  -port_diff_buffers - (Optional) Add the differential pair buffers and
831 
  internal wires associated with those buffers into the output ports list.
832 
  This argument is only valid when -mode pin_planning or -mode synth_stub is
833 
  specified.
834 
 
835 
  -write_all_overrides [ true | false ] - (Optional) Write parameter
836 
  overrides, in the design to the Verilog output even if the value of the
837 
  parameter is the same as the defined primitive default value. If the option
838 
  is false then parameter values which are equivalent to the primitive
839 
  defaults are not output to the Verilog file. Setting this option to true
840 
  will not change the result but makes the output Verilog more verbose.
841 
 
842 
  -keep_vcc_gnd - (Optional) By default, when writing a nelist for
843 
  simulation, or from an IP Integrator block design, the Vivado Design Suite
844 
  replaces VCC and GND primitives, and the nets they drive, with literal
845 
  constants on each of the loads on the net. The -keep_vcc_gnd option
846 
  disables this default behavior and preserves the VCC or GND primitives.
847 
 
848 
  -rename_top  - (Optional) Rename the top module in the output as
849 
  specified. This option only works with -mode funcsim or -mode timesim to
850 
  allow the Verilog netlist to plug into top-level simulation test benches.
851 
 
852 
  -sdf_anno [ true | false ] - (Optional) Add the $sdf_annotate statement to
853 
  the Verilog netlist. Valid values are true (or 1) and false (or 0). This
854 
  option only works with -mode timesim, and is set to false by default.
855 
 
856 
  -sdf_file  - (Optional) The path and filename of the SDF file to use
857 
  when writing the $sdf_annotate statement into the output Verilog file. When
858 
  not specified, the SDF file is assumed to have the same name and path as
859 
  the Verilog output specified by , with a file extension of .sdf. The
860 
  SDF file must be separately written to the specified file path and name
861 
  using the write_sdf command.
862 
 
863 
  -force - (Optional) Overwrite the Verilog files if they already exists.
864 
 
865 
  -include_xilinx_libs - (Optional) Write the simulation models directly in
866 
  the output netlist file rather than pointing to the libraries by reference.
867 
 
868 
  -logic_function_stripped - (Optional) Hides the INIT values for LUTs & RAMs
869 
  by converting them to fixed values in order to create a netlist for debug
870 
  purposes that will not behave properly in simulation or synthesis.
871 
 
872 
  -quiet - (Optional) Execute the command quietly, returning no messages from
873 
  the command. The command also returns TCL_OK regardless of any errors
874 
  encountered during execution.
875 
 
876 
  Note: Any errors encountered on the command-line, while launching the
877 
  command, will be returned. Only errors occurring inside the command will be
878 
  trapped.
879 
 
880 
  -verbose - (Optional) Temporarily override any message limits and return
881 
  all messages from this command.
882 
 
883 
  Note: Message limits can be defined with the set_msg_config command.
884 
 
885 
   - (Required) The path and filename of the Verilog file to write. The
886 
  path is optional, but if one is not provided the Verilog file will be
887 
  written to the current working directory, or the directory from which the
888 
  Vivado tool was launched.
889 
 
890 
Examples:
891 
 
892 
  The following example writes a Verilog simulation netlist file for the
893 
  whole design to the specified file and path:
894 
 
895 
    write_verilog C:/Data/my_verilog.v
896 
 
897 
  In the following example, because the -mode timesim and -sdf_anno options
898 
  are specified, the $sdf_annotate statement will be added to the Verilog
899 
  netlist. However, since the -sdf_file option is not specified, the SDF file
900 
  is assumed to have the same name as the Verilog output file, with an .sdf
901 
  file extension:
902 
 
903 
    write_verilog C:/Data/my_verilog.net -mode timesim -sdf_anno true
904 
 
905 
  Note: The SDF filename written to the $sdf_annotate statement will be
906 
  my_verilog.sdf.
907 
 
908 
  In the following example, the functional simulation mode is specified, the
909 
  option to keep VCC and GND primitives in the output simulation netlist is
910 
  enabled, and the output file is specified:
911 
 
912 
    write_verilog -mode funcsim -keep_vcc_gnd out.v
913 
 
914 
See Also:
915 
 
916 
   *  write_sdf
917 
   *  write_vhdl
918 
write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim -force -sdf_file ./netlist/aes128_ecb_wrap.sdf -sdf_anno 1
919 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/aes128_ecb_wrap.v
920 
write_verilog ./netlist/aes128_ecb_wrap.v -mode timesim -force
921 
/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/netlist/aes128_ecb_wrap.v
922 
compile_simlib -simulator ies -simulator_exec_path {/opt/cad/Cadence/IC6/XCELIUMMAIN18.09.005_/bin} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
923 
INFO: [Vivado 12-5497] IP library compilation is not applicable for 'simprim' components. To compile IPs, specify either 'all' or 'unisim' value with the -library switch.
924 
INFO: [Vivado 12-5496] Finding simulator executables and checking version...
925 
ERROR: [Vivado 12-3754] Failed to find the 'ies' simulator executable. Make sure to set the 'ies' installation environment and retry this command to compile the libraries for this simulator. For more information on tool setup refer 'ies' user guide.
926 
Library compilation for 'ies' ignored.
927 
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.
928 
compile_simlib -simulator ies -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/bin} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
929 
INFO: [Vivado 12-5497] IP library compilation is not applicable for 'simprim' components. To compile IPs, specify either 'all' or 'unisim' value with the -library switch.
930 
INFO: [Vivado 12-5496] Finding simulator executables and checking version...
931 
ERROR: [Vivado 12-3754] Failed to find the 'ies' simulator executable. Make sure to set the 'ies' installation environment and retry this command to compile the libraries for this simulator. For more information on tool setup refer 'ies' user guide.
932 
Library compilation for 'ies' ignored.
933 
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.
934 
compile_simlib -help
935 
compile_simlib
936 
 
937 
Description:
938 
Compile simulation libraries
939 
 
940 
Syntax:
941 
compile_simlib  [-directory ] [-family ] [-force] [-language ]
942 
                [-library ] [-print_library_info ] -simulator
943 
                [-simulator_exec_path ] [-source_library_path ]
944 
                [-no_ip_compile] [-32bit] [-quiet] [-verbose]
945 
 
946 
Usage:
947 
  Name                    Description
948 
  -----------------------------------
949 
  [-directory]            Directory path for saving the compiled results
950 
                          Default: .
951 
  [-family]               Select device architecture
952 
                          Default: all
953 
  [-force]                Overwrite the pre-compiled libraries
954 
  [-language]             Compile libraries for this language
955 
                          Default: all
956 
  [-library]              Select library to compile
957 
                          Default: all
958 
  [-print_library_info]   Print Pre-Compiled library information
959 
  -simulator              Compile libraries for this simulator
960 
  [-simulator_exec_path]  Use simulator executables from this directory
961 
  [-source_library_path]  If specified, this directory will be searched for
962 
                          the library source files before searching the
963 
                          default path(s) found in environment variable
964 
                          XILINX_VIVADO for Vivado
965 
  [-no_ip_compile]        Do not compile IP static files from repository
966 
  [-32bit]                Perform the 32-bit compilation
967 
  [-quiet]                Ignore command errors
968 
  [-verbose]              Suspend message limits during command execution
969 
 
970 
Categories:
971 
Simulation
972 
 
973 
Description:
974 
 
975 
  Compile Xilinx simulation libraries for the cells and IP used in the
976 
  current project, or from a specified directory for use in multiple design
977 
  projects.
978 
 
979 
  The Vivado Design Suite provides simulation models as a set of files and
980 
  libraries that contain the behavioral and timing models for use by the
981 
  Vivado simulator. The compile_simlib command compiles these libraries for
982 
  use by third-party simulators prior to design simulation. Libraries must
983 
  generally be compiled or recompiled with a new software release to update
984 
  simulation models and to support a new version of a simulator.
985 
 
986 
  Note: You should rerun the compile_simlib command any time a new third
987 
  party simulator will be used, or a new Vivado Design Suite version or
988 
  update is installed.
989 
 
990 
  When this command is run from a current project, the tool will use the
991 
  device family, target language, and library settings specified by the
992 
  project as the default values, rather than the default settings of the
993 
  command defined below. The default settings can be overridden by specifying
994 
  the necessary options when the command is run.
995 
 
996 
  The compile_simlib command uses simulator compilation directives when
997 
  compiling the simulation libraries. You can edit the default configuration
998 
  settings using the config_compile_simlib command.
999 
 
1000 
  The command returns information related to the compiled libraries, or an
1001 
  error if it fails.
1002 
 
1003 
Arguments:
1004 
 
1005 
  -directory  - (Optional) Directory path for saving the compiled
1006 
  library results.
1007 
 
1008 
  Note: By default, the libraries are saved in the current working directory
1009 
  in Non-Project mode, and the libraries are saved in
1010 
  "/.cache/compile_simlib" directory in Project mode. Refer
1011 
  to the Vivado Design Suite User Guide: Design Flows Overview (UG892) for
1012 
  more information on Project and Non-Project modes.
1013 
 
1014 
  -family  - (Optional) Compile selected libraries to the specified
1015 
  device family. All device families will be generated by default. The
1016 
  following are the device families that can be specified:
1017 
 
1018 
   *  all (generate libraries for all device families, the default)
1019 
 
1020 
   *  virtexuplus (for Virtex UltraScale+ devices)
1021 
 
1022 
   *  virtexu (for Virtex UltraScale devices)
1023 
 
1024 
   *  virtex7 (for Virtex-7)
1025 
 
1026 
   *  virtex7l (for Virtex-7 Lower Power)
1027 
 
1028 
   *  qvirtex7 (for Virtex-7 Defense Grade)
1029 
 
1030 
   *  qvirtex7l (for Virtex-7 Lower Power Defense Grade)
1031 
 
1032 
   *  kintexuplus (for Kintex UltraScale+ devices)
1033 
 
1034 
   *  kintexu (for Kintex UltraScale devices)
1035 
 
1036 
   *  kintex7 (for Kintex-7)
1037 
 
1038 
   *  kintex7l (for Kintex-7 Lower Power)
1039 
 
1040 
   *  qkintex7 (for Kintex-7 Defense Grade)
1041 
 
1042 
   *  qkintex7l (for Kintex-7 Lower Power Defense Grade)
1043 
 
1044 
   *  artix7 (for Artix-7)
1045 
 
1046 
   *  artix7l (for Artix-7 Lower Power)
1047 
 
1048 
   *  qartix7 (for Artix-7 Defense Grade)
1049 
 
1050 
   *  qartix7l (for Artix-7 Lower Power Defense Grade)
1051 
 
1052 
   *  zynquplus (for Zynq UltraScale+ devices)
1053 
 
1054 
   *  zynq (for Zynq devices)
1055 
 
1056 
   *  azynq (for Zynq Automotive)
1057 
 
1058 
   *  qzynq (for Zynq Defense Grade)
1059 
 
1060 
  -force - (Optional) Overwrite the current pre-compiled libraries.
1061 
 
1062 
  -language [ verilog | vhdl | all ] - (Optional) This option is only needed
1063 
  for use with -no_ip_compile, and will compile base simulation libraries for
1064 
  the specified language. If this option is not specified then the language
1065 
  will be set according to the simulator selected with -simulator. For
1066 
  multi-language simulators both Verilog and VHDL libraries will be compiled.
1067 
 
1068 
  Note: By default, compile_simlib compiles simulation libraries for IP, and
1069 
  compiles all languages for the IP.
1070 
 
1071 
  -library  - (Optional) Specify the simulation library to compile. As a
1072 
  default, the compile_simlib command will compile all simulation libraries.
1073 
  Valid values are:
1074 
 
1075 
   *  all (the default)
1076 
 
1077 
   *  unisim
1078 
 
1079 
   *  simprim
1080 
 
1081 
  To specify multiple libraries, repeat the -lib options for each library.
1082 
  For example:
1083 
 
1084 
    .. -library unisim -library simprim ..
1085 
 
1086 
  -print_library_info - (Optional) Print the library information for the
1087 
  compiled simulation library.
1088 
 
1089 
  -simulator  - (Required) Compile libraries for the specified
1090 
  simulator. Valid simulator values are:
1091 
 
1092 
   *  modelsim - Version 10.6b and later
1093 
 
1094 
   *  questa - Version 10.6b and later
1095 
 
1096 
   *  ies - (Linux only) Version 15.20.028 or later
1097 
 
1098 
   *  vcs_mx - (Linux only) Version M-2017.03-SP1 or later
1099 
 
1100 
   *  riviera - Version 2017.02 or later
1101 
 
1102 
   *  active_hdl - (Windows only) Version 10.4a
1103 
 
1104 
  -simulator_exec_path  - (Optional) Specify the directory to locate the
1105 
  third-party compiler and simulator executables. This option is required if
1106 
  the target simulator is not specified in the $PATH or %PATH% environment
1107 
  variable; or to override the path from the $PATH or %PATH% environment
1108 
  variable.
1109 
 
1110 
  -source_library_path  - (Optional) If specified, this directory will
1111 
  be searched for the library source files before searching the default
1112 
  path(s) defined by the environment variables ($XILINX or $XILINX_VIVADO).
1113 
 
1114 
  Note: Do not use this option unless explicitly instructed to by Xilinx
1115 
  Technical Support.
1116 
 
1117 
  -no_ip_compile - (Optional) Disables the compilation of simulation files
1118 
  for IP in the design or the specified repositories. By default, the
1119 
  compile_simlib command compiles the static simulation files for all IP in
1120 
  the IP Catalog, including added user and third-party repositories. Use this
1121 
  option to disable that feature.
1122 
 
1123 
  -32bit - (Optional) Perform simulator compilation in 32-bit mode instead of
1124 
  the default 64-bit compilation.
1125 
 
1126 
  -quiet - (Optional) Execute the command quietly, returning no messages from
1127 
  the command. The command also returns TCL_OK regardless of any errors
1128 
  encountered during execution.
1129 
 
1130 
  Note: Any errors encountered on the command-line, while launching the
1131 
  command, will be returned. Only errors occurring inside the command will be
1132 
  trapped.
1133 
 
1134 
  -verbose - (Optional) Temporarily override any message limits and return
1135 
  all messages from this command.
1136 
 
1137 
  Note: Message limits can be defined with the set_msg_config command.
1138 
 
1139 
Examples:
1140 
 
1141 
  The following example shows how to compile UNISIM and SIMPRIM libraries for
1142 
  ModelSim (VHDL) for a design using a Virtex-7 device:
1143 
 
1144 
    compile_simlib -simulator modelsim -family virtex7 -library unisim \
1145 
       -library simprim -language vhdl
1146 
 
1147 
See Also:
1148 
 
1149 
   *  config_compile_simlib
1150 
   *  export_simulation
1151 
   *  launch_simulation
1152 
compile_simlib -simulator ies -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/tools.lnx86/bin/64bit} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
1153 
INFO: [Vivado 12-5497] IP library compilation is not applicable for 'simprim' components. To compile IPs, specify either 'all' or 'unisim' value with the -library switch.
1154 
INFO: [Vivado 12-5496] Finding simulator executables and checking version...
1155 
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) ...
1156 
 
1157 
Compiling libraries for 'ies' simulator in '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib'
1158 
Creating cds.lib file...
1159 
Creating hdl.var file...
1160 
--> Compiling 'verilog.secureip' library...
1161 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip'
1162 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/secureip'
1163 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/secureip/.cxl.verilog.secureip.secureip.lin64.log'
1164 
 
1165 
compile_simlib[verilog.secureip]: 0 error(s), 0 warning(s), 33.33 % complete
1166 
--> Compiling 'verilog.simprim' library...
1167 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims'
1168 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver'
1169 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver/.cxl.verilog.simprim.simprims_ver.lin64.log'
1170 
 
1171 
compile_simlib[verilog.simprim]: 0 error(s), 0 warning(s), 66.67 % complete
1172 
--> Compiling 'verilog.xpm' library...
1173 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm'
1174 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm'
1175 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm/.cxl.verilog.xpm.xpm.lin64.log'
1176 
 
1177 
compile_simlib[verilog.xpm]: 0 error(s), 0 warning(s), 100.00 % complete
1178 
Copying setup file 'cds.lib' to '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/cds.lib' ...
1179 
Copying setup file 'hdl.var' to '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/hdl.var' ...
1180 
 
1181 
********************************************************************************************
1182 
*                                  COMPILATION SUMMARY                                     *
1183 
*                                                                                          *
1184 
*  Simulator used: ies                                                                     *
1185 
*  Compiled on: Tue Jul 28 09:34:44 2020                                                   *
1186 
*                                                                                          *
1187 
********************************************************************************************
1188 
*  Library                        | Language | Mapped Library Name | Error(s) | Warning(s) *
1189 
*------------------------------------------------------------------------------------------*
1190 
*  secureip                       | verilog  | secureip            | 0        | 0          *
1191 
*------------------------------------------------------------------------------------------*
1192 
*  simprim                        | verilog  | simprims_ver        | 0        | 0          *
1193 
*------------------------------------------------------------------------------------------*
1194 
*  xpm                            | verilog  | xpm                 | 0        | 0          *
1195 
*------------------------------------------------------------------------------------------*
1196 
 
1197 
compile_simlib: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 7553.523 ; gain = 0.000 ; free physical = 57968 ; free virtual = 100448
1198 
compile_simlib -help
1199 
compile_simlib
1200 
 
1201 
Description:
1202 
Compile simulation libraries
1203 
 
1204 
Syntax:
1205 
compile_simlib  [-directory ] [-family ] [-force] [-language ]
1206 
                [-library ] [-print_library_info ] -simulator
1207 
                [-simulator_exec_path ] [-source_library_path ]
1208 
                [-no_ip_compile] [-32bit] [-quiet] [-verbose]
1209 
 
1210 
Usage:
1211 
  Name                    Description
1212 
  -----------------------------------
1213 
  [-directory]            Directory path for saving the compiled results
1214 
                          Default: .
1215 
  [-family]               Select device architecture
1216 
                          Default: all
1217 
  [-force]                Overwrite the pre-compiled libraries
1218 
  [-language]             Compile libraries for this language
1219 
                          Default: all
1220 
  [-library]              Select library to compile
1221 
                          Default: all
1222 
  [-print_library_info]   Print Pre-Compiled library information
1223 
  -simulator              Compile libraries for this simulator
1224 
  [-simulator_exec_path]  Use simulator executables from this directory
1225 
  [-source_library_path]  If specified, this directory will be searched for
1226 
                          the library source files before searching the
1227 
                          default path(s) found in environment variable
1228 
                          XILINX_VIVADO for Vivado
1229 
  [-no_ip_compile]        Do not compile IP static files from repository
1230 
  [-32bit]                Perform the 32-bit compilation
1231 
  [-quiet]                Ignore command errors
1232 
  [-verbose]              Suspend message limits during command execution
1233 
 
1234 
Categories:
1235 
Simulation
1236 
 
1237 
Description:
1238 
 
1239 
  Compile Xilinx simulation libraries for the cells and IP used in the
1240 
  current project, or from a specified directory for use in multiple design
1241 
  projects.
1242 
 
1243 
  The Vivado Design Suite provides simulation models as a set of files and
1244 
  libraries that contain the behavioral and timing models for use by the
1245 
  Vivado simulator. The compile_simlib command compiles these libraries for
1246 
  use by third-party simulators prior to design simulation. Libraries must
1247 
  generally be compiled or recompiled with a new software release to update
1248 
  simulation models and to support a new version of a simulator.
1249 
 
1250 
  Note: You should rerun the compile_simlib command any time a new third
1251 
  party simulator will be used, or a new Vivado Design Suite version or
1252 
  update is installed.
1253 
 
1254 
  When this command is run from a current project, the tool will use the
1255 
  device family, target language, and library settings specified by the
1256 
  project as the default values, rather than the default settings of the
1257 
  command defined below. The default settings can be overridden by specifying
1258 
  the necessary options when the command is run.
1259 
 
1260 
  The compile_simlib command uses simulator compilation directives when
1261 
  compiling the simulation libraries. You can edit the default configuration
1262 
  settings using the config_compile_simlib command.
1263 
 
1264 
  The command returns information related to the compiled libraries, or an
1265 
  error if it fails.
1266 
 
1267 
Arguments:
1268 
 
1269 
  -directory  - (Optional) Directory path for saving the compiled
1270 
  library results.
1271 
 
1272 
  Note: By default, the libraries are saved in the current working directory
1273 
  in Non-Project mode, and the libraries are saved in
1274 
  "/.cache/compile_simlib" directory in Project mode. Refer
1275 
  to the Vivado Design Suite User Guide: Design Flows Overview (UG892) for
1276 
  more information on Project and Non-Project modes.
1277 
 
1278 
  -family  - (Optional) Compile selected libraries to the specified
1279 
  device family. All device families will be generated by default. The
1280 
  following are the device families that can be specified:
1281 
 
1282 
   *  all (generate libraries for all device families, the default)
1283 
 
1284 
   *  virtexuplus (for Virtex UltraScale+ devices)
1285 
 
1286 
   *  virtexu (for Virtex UltraScale devices)
1287 
 
1288 
   *  virtex7 (for Virtex-7)
1289 
 
1290 
   *  virtex7l (for Virtex-7 Lower Power)
1291 
 
1292 
   *  qvirtex7 (for Virtex-7 Defense Grade)
1293 
 
1294 
   *  qvirtex7l (for Virtex-7 Lower Power Defense Grade)
1295 
 
1296 
   *  kintexuplus (for Kintex UltraScale+ devices)
1297 
 
1298 
   *  kintexu (for Kintex UltraScale devices)
1299 
 
1300 
   *  kintex7 (for Kintex-7)
1301 
 
1302 
   *  kintex7l (for Kintex-7 Lower Power)
1303 
 
1304 
   *  qkintex7 (for Kintex-7 Defense Grade)
1305 
 
1306 
   *  qkintex7l (for Kintex-7 Lower Power Defense Grade)
1307 
 
1308 
   *  artix7 (for Artix-7)
1309 
 
1310 
   *  artix7l (for Artix-7 Lower Power)
1311 
 
1312 
   *  qartix7 (for Artix-7 Defense Grade)
1313 
 
1314 
   *  qartix7l (for Artix-7 Lower Power Defense Grade)
1315 
 
1316 
   *  zynquplus (for Zynq UltraScale+ devices)
1317 
 
1318 
   *  zynq (for Zynq devices)
1319 
 
1320 
   *  azynq (for Zynq Automotive)
1321 
 
1322 
   *  qzynq (for Zynq Defense Grade)
1323 
 
1324 
  -force - (Optional) Overwrite the current pre-compiled libraries.
1325 
 
1326 
  -language [ verilog | vhdl | all ] - (Optional) This option is only needed
1327 
  for use with -no_ip_compile, and will compile base simulation libraries for
1328 
  the specified language. If this option is not specified then the language
1329 
  will be set according to the simulator selected with -simulator. For
1330 
  multi-language simulators both Verilog and VHDL libraries will be compiled.
1331 
 
1332 
  Note: By default, compile_simlib compiles simulation libraries for IP, and
1333 
  compiles all languages for the IP.
1334 
 
1335 
  -library  - (Optional) Specify the simulation library to compile. As a
1336 
  default, the compile_simlib command will compile all simulation libraries.
1337 
  Valid values are:
1338 
 
1339 
   *  all (the default)
1340 
 
1341 
   *  unisim
1342 
 
1343 
   *  simprim
1344 
 
1345 
  To specify multiple libraries, repeat the -lib options for each library.
1346 
  For example:
1347 
 
1348 
    .. -library unisim -library simprim ..
1349 
 
1350 
  -print_library_info - (Optional) Print the library information for the
1351 
  compiled simulation library.
1352 
 
1353 
  -simulator  - (Required) Compile libraries for the specified
1354 
  simulator. Valid simulator values are:
1355 
 
1356 
   *  modelsim - Version 10.6b and later
1357 
 
1358 
   *  questa - Version 10.6b and later
1359 
 
1360 
   *  ies - (Linux only) Version 15.20.028 or later
1361 
 
1362 
   *  vcs_mx - (Linux only) Version M-2017.03-SP1 or later
1363 
 
1364 
   *  riviera - Version 2017.02 or later
1365 
 
1366 
   *  active_hdl - (Windows only) Version 10.4a
1367 
 
1368 
  -simulator_exec_path  - (Optional) Specify the directory to locate the
1369 
  third-party compiler and simulator executables. This option is required if
1370 
  the target simulator is not specified in the $PATH or %PATH% environment
1371 
  variable; or to override the path from the $PATH or %PATH% environment
1372 
  variable.
1373 
 
1374 
  -source_library_path  - (Optional) If specified, this directory will
1375 
  be searched for the library source files before searching the default
1376 
  path(s) defined by the environment variables ($XILINX or $XILINX_VIVADO).
1377 
 
1378 
  Note: Do not use this option unless explicitly instructed to by Xilinx
1379 
  Technical Support.
1380 
 
1381 
  -no_ip_compile - (Optional) Disables the compilation of simulation files
1382 
  for IP in the design or the specified repositories. By default, the
1383 
  compile_simlib command compiles the static simulation files for all IP in
1384 
  the IP Catalog, including added user and third-party repositories. Use this
1385 
  option to disable that feature.
1386 
 
1387 
  -32bit - (Optional) Perform simulator compilation in 32-bit mode instead of
1388 
  the default 64-bit compilation.
1389 
 
1390 
  -quiet - (Optional) Execute the command quietly, returning no messages from
1391 
  the command. The command also returns TCL_OK regardless of any errors
1392 
  encountered during execution.
1393 
 
1394 
  Note: Any errors encountered on the command-line, while launching the
1395 
  command, will be returned. Only errors occurring inside the command will be
1396 
  trapped.
1397 
 
1398 
  -verbose - (Optional) Temporarily override any message limits and return
1399 
  all messages from this command.
1400 
 
1401 
  Note: Message limits can be defined with the set_msg_config command.
1402 
 
1403 
Examples:
1404 
 
1405 
  The following example shows how to compile UNISIM and SIMPRIM libraries for
1406 
  ModelSim (VHDL) for a design using a Virtex-7 device:
1407 
 
1408 
    compile_simlib -simulator modelsim -family virtex7 -library unisim \
1409 
       -library simprim -language vhdl
1410 
 
1411 
See Also:
1412 
 
1413 
   *  config_compile_simlib
1414 
   *  export_simulation
1415 
   *  launch_simulation
1416 
compile_simlib -simulator xrun -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/tools.lnx86/bin/64bit} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
1417 
INFO: [Vivado 12-5497] IP library compilation is not applicable for 'simprim' components. To compile IPs, specify either 'all' or 'unisim' value with the -library switch.
1418 
ERROR: [Vivado 12-2158] Invalid simulator 'xrun' specified for -simulator.
1419 
 
1420 
 -simulator  : Specify the name of the simulator for which the libraries
1421 
                          are to be compiled. The valid simulator names are :-
1422 
 
1423 
                  modelsim questasim ies vcs_mx xsim riviera active_hdl
1424 
 
1425 
 
1426 
Note: Only specific versions of the simulators are supported. Please verify
1427 
      that the selected simulator version satisfies the following requirement(s):
1428 
                  Modelsim/QuestaSim 10.5c and later
1429 
                  IUS 15.20.014 or later
1430 
                  VCS and VCS MX L-2016.06-SP1 or later
1431 
                  Aldec Riviera PRO 2016.10 or later
1432 
 
1433 
ERROR: [Common 17-39] 'compile_simlib' failed due to earlier errors.
1434 
compile_simlib -simulator xsim -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/tools.lnx86/bin/64bit} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
1435 
INFO: [Vivado 12-5497] IP library compilation is not applicable for 'simprim' components. To compile IPs, specify either 'all' or 'unisim' value with the -library switch.
1436 
INFO: [Vivado 12-5496] Finding simulator executables and checking version...
1437 
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) ...
1438 
 
1439 
Compiling libraries for 'xil_xsim' simulator in '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib'
1440 
Creating xsim.ini file...
1441 
--> Compiling 'verilog.secureip' library...
1442 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip'
1443 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/secureip'
1444 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/secureip/.cxl.verilog.secureip.secureip.lin64.log'
1445 
 
1446 
compile_simlib[verilog.secureip]: 0 error(s), 0 warning(s), 33.33 % complete
1447 
--> Compiling 'verilog.simprim' library...
1448 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims'
1449 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver'
1450 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver/.cxl.verilog.simprim.simprims_ver.lin64.log'
1451 
 
1452 
compile_simlib[verilog.simprim]: 0 error(s), 0 warning(s), 66.67 % complete
1453 
--> Compiling 'verilog.xpm' library...
1454 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm'
1455 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm'
1456 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm/.cxl.verilog.xpm.xpm.lin64.log'
1457 
 
1458 
compile_simlib[verilog.xpm]: 0 error(s), 0 warning(s), 100.00 % complete
1459 
Copying setup file 'xsim.ini' to '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xsim.ini' ...
1460 
 
1461 
********************************************************************************************
1462 
*                                  COMPILATION SUMMARY                                     *
1463 
*                                                                                          *
1464 
*  Simulator used: xil_xsim                                                                *
1465 
*  Compiled on: Tue Jul 28 09:50:01 2020                                                   *
1466 
*                                                                                          *
1467 
********************************************************************************************
1468 
*  Library                        | Language | Mapped Library Name | Error(s) | Warning(s) *
1469 
*------------------------------------------------------------------------------------------*
1470 
*  secureip                       | verilog  | secureip            | 0        | 0          *
1471 
*------------------------------------------------------------------------------------------*
1472 
*  simprim                        | verilog  | simprims_ver        | 0        | 0          *
1473 
*------------------------------------------------------------------------------------------*
1474 
*  xpm                            | verilog  | xpm                 | 0        | 0          *
1475 
*------------------------------------------------------------------------------------------*
1476 
 
1477 
compile_simlib: Time (s): cpu = 00:00:25 ; elapsed = 00:00:58 . Memory (MB): peak = 7553.523 ; gain = 0.000 ; free physical = 55321 ; free virtual = 99280
1478 
compile_simlib -simulator ies -simulator_exec_path {/opt/cad/Cadence/IC6/INCISIV14.10.005_/tools.lnx86/bin/64bit} -family kintex7 -language verilog -library simprim -dir {/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib} -force
1479 
INFO: [Vivado 12-5497] IP library compilation is not applicable for 'simprim' components. To compile IPs, specify either 'all' or 'unisim' value with the -library switch.
1480 
INFO: [Vivado 12-5496] Finding simulator executables and checking version...
1481 
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) ...
1482 
 
1483 
Compiling libraries for 'ies' simulator in '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib'
1484 
--> Compiling 'verilog.secureip' library...
1485 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/secureip'
1486 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/secureip'
1487 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/secureip/.cxl.verilog.secureip.secureip.lin64.log'
1488 
 
1489 
compile_simlib[verilog.secureip]: 0 error(s), 2 warning(s), 33.33 % complete
1490 
--> Compiling 'verilog.simprim' library...
1491 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/verilog/src/unisims'
1492 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver'
1493 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/simprims_ver/.cxl.verilog.simprim.simprims_ver.lin64.log'
1494 
 
1495 
compile_simlib[verilog.simprim]: 0 error(s), 1 warning(s), 66.67 % complete
1496 
--> Compiling 'verilog.xpm' library...
1497 
    > Source Library = '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip/xpm'
1498 
    > Compiled Path  = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm'
1499 
    > Log File       = '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/xpm/.cxl.verilog.xpm.xpm.lin64.log'
1500 
 
1501 
compile_simlib[verilog.xpm]: 0 error(s), 0 warning(s), 100.00 % complete
1502 
Copying setup file 'cds.lib' to '/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/cds.lib' ...
1503 
 
1504 
********************************************************************************************
1505 
*                                  COMPILATION SUMMARY                                     *
1506 
*                                                                                          *
1507 
*  Simulator used: ies                                                                     *
1508 
*  Compiled on: Tue Jul 28 09:51:19 2020                                                   *
1509 
*                                                                                          *
1510 
********************************************************************************************
1511 
*  Library                        | Language | Mapped Library Name | Error(s) | Warning(s) *
1512 
*------------------------------------------------------------------------------------------*
1513 
*  secureip                       | verilog  | secureip            | 0        | 2          *
1514 
*------------------------------------------------------------------------------------------*
1515 
*  simprim                        | verilog  | simprims_ver        | 0        | 1          *
1516 
*------------------------------------------------------------------------------------------*
1517 
*  xpm                            | verilog  | xpm                 | 0        | 0          *
1518 
*------------------------------------------------------------------------------------------*
1519 
 
1520 
compile_simlib: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 7553.523 ; gain = 0.000 ; free physical = 54125 ; free virtual = 98267
1521 
copy_ip -name axi_uartlite_module_sim -dir /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip [get_ips  axi_uartlite_module]
1522 
update_compile_order -fileset sources_1
1523 
generate_target all [get_files  /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci]
1524 
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_uartlite_module_sim'...
1525 
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_uartlite_module_sim'...
1526 
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_uartlite_module_sim'...
1527 
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'axi_uartlite_module_sim'...
1528 
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_uartlite_module_sim'...
1529 
catch { config_ip_cache -export [get_ips -all axi_uartlite_module_sim] }
1530 
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP axi_uartlite_module_sim, cache-ID = 077a94985ac208e4; cache size = 7.190 MB.
1531 
export_ip_user_files -of_objects [get_files /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci] -no_script -sync -force -quiet
1532 
create_ip_run [get_files -of_objects [get_fileset sources_1] /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci]
1533 
INFO: [Vivado 12-3453] The given sub-design is up-to-date, no action was taken.  If a run is still desired, use the '-force' option for the file:'/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci'
1534 
export_simulation -of_objects [get_files /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci] -directory /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.ip_user_files/sim_scripts -ip_user_files_dir /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.ip_user_files -ipstatic_source_dir /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.ip_user_files/ipstatic -lib_map_path [list {modelsim=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/modelsim} {questa=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/questa} {ies=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/ies} {vcs=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/vcs} {riviera=/home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
1535 
set_property used_in_synthesis false [get_files  /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci]
1536 
set_property used_in_implementation false [get_files  /home/v.gulyaev/Project/vozhak/trunk/rtl/aes128/fpga/aes128_ecb/aes128_ecb.srcs/sources_1/ip/axi_uartlite_module_sim/axi_uartlite_module_sim.xci]
1537 
close_project
1538 
open_project /ssd/v.gulyaev/usb_otg/fpga/vivado_proj/otg_and_dev.xpr
1539 
Scanning sources...
1540 
Finished scanning sources
1541 
INFO: [IP_Flow 19-234] Refreshing IP repositories
1542 
INFO: [IP_Flow 19-1704] No user IP repositories specified
1543 
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/cad/xilinx/Vivado2017/Vivado/2017.4/data/ip'.
1544 
update_compile_order -fileset sources_1
1545 
exit
1546 
INFO: [Common 17-206] Exiting Vivado at Tue Jul 28 11:48:51 2020...

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