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vv_gulyaev |
#-----------------------------------------------------------
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# Vivado v2017.4 (64-bit)
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# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
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# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
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# Start of session at: Wed Jul 29 15:27:30 2020
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# Process ID: 2077
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# Current directory: /home/user/aes/fpga/aec128_ecb_2017
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# Command line: vivado
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# Log file: /home/user/aes/fpga/aec128_ecb_2017/vivado.log
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# Journal file: /home/user/aes/fpga/aec128_ecb_2017/vivado.jou
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#-----------------------------------------------------------
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start_gui
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open_project /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.xpr
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2017.4/data/ip'.
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open_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 6033.367 ; gain = 52.977 ; free physical = 4968 ; free virtual = 8475
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update_compile_order -fileset sources_1
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reset_run synth_1
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launch_runs synth_1 -jobs 2
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[Wed Jul 29 15:29:53 2020] Launched synth_1...
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Run output will be captured here: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/synth_1/runme.log
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launch_runs impl_1 -jobs 2
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[Wed Jul 29 15:33:07 2020] Launched impl_1...
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Run output will be captured here: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
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WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
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open_run impl_1
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INFO: [Netlist 29-17] Analyzing 911 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2017.4
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INFO: [Device 21-403] Loading part xc7k325tffg900-2
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap_board.xdc]
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Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap_board.xdc]
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Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap_early.xdc]
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INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
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INFO: [Timing 38-2] Deriving generated clocks [/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.srcs/sources_1/ip/clk_gen/clk_gen.xdc:57]
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get_clocks: Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 6913.031 ; gain = 550.430 ; free physical = 4069 ; free virtual = 7687
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Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap_early.xdc]
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Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap.xdc]
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Finished Parsing XDC File [/home/user/aes/fpga/aec128_ecb_2017/.Xil/Vivado-2077-orme22/dcp4/aes128_ecb_fpga_wrap.xdc]
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Reading XDEF placement.
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Reading placer database...
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Reading XDEF routing.
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Read XDEF File: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6918.031 ; gain = 5.000 ; free physical = 4064 ; free virtual = 7683
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Restored from archive | CPU: 0.160000 secs | Memory: 4.181816 MB |
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Finished XDEF File Restore: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6918.031 ; gain = 5.000 ; free physical = 4064 ; free virtual = 7683
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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open_run: Time (s): cpu = 00:00:30 ; elapsed = 00:00:43 . Memory (MB): peak = 7091.215 ; gain = 986.719 ; free physical = 3984 ; free virtual = 7596
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WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
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launch_runs impl_1 -to_step write_bitstream -jobs 2
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[Wed Jul 29 15:36:50 2020] Launched impl_1...
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Run output will be captured here: /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/runme.log
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write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit" } -force -file "/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.mcs"
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Command: write_cfgmem -format mcs -size 128 -interface BPIx16 -loadbit {up 0x00000000 "/home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit" } -force -file /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.mcs
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Creating config memory files...
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INFO: [Writecfgmem 68-23] Start address provided has been multiplied by a factor of 2 due to the use of interface BPIX16.
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Creating bitstream load up from address 0x00000000
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Loading bitfile /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit
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Writing file /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.mcs
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Writing log file /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.prm
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===================================
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Configuration Memory information
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===================================
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File Format MCS
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Interface BPIX16
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Size 128M
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Start Address 0x00000000
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End Address 0x07FFFFFF
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Addr1 Addr2 Date File(s)
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0x00000000 0x00AE9D9B Jul 29 15:37:54 2020 /home/user/aes/fpga/aec128_ecb_2017/aes128_ecb.runs/impl_1/aes128_ecb_fpga_wrap.bit
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1 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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write_cfgmem completed successfully
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open_hw
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connect_hw_server
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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INFO: [Labtools 27-2222] Launching hw_server...
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INFO: [Labtools 27-2221] Launch Output:
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****** Xilinx hw_server v2017.4
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**** Build date : Dec 15 2017-21:02:11
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** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
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Targets(s) ", jsn1" may be locked by another hw_server.
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disconnect_hw_server localhost:3121
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connect_hw_server
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
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Targets(s) ", jsn1jsn2jsn3jsn4jsn5jsn6jsn7jsn8jsn9jsn10" may be locked by another hw_server.
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exit
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INFO: [Common 17-206] Exiting Vivado at Wed Jul 29 15:45:15 2020...
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